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/linux/drivers/pmdomain/mediatek/
H A Dmt8186-pm-domains.h21 .ctl_offs = 0x308,
22 .pwr_sta_offs = 0x16C,
23 .pwr_sta2nd_offs = 0x170,
31 .ctl_offs = 0x30c,
32 .pwr_sta_offs = 0x16C,
33 .pwr_sta2nd_offs = 0x170,
63 .ctl_offs = 0x310,
64 .pwr_sta_offs = 0x16C,
65 .pwr_sta2nd_offs = 0x170,
73 .ctl_offs = 0x314,
[all …]
H A Dmt8188-pm-domains.h21 .ctl_offs = 0x300,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
31 .ctl_offs = 0x304,
32 .pwr_sta_offs = 0x174,
33 .pwr_sta2nd_offs = 0x178,
73 .ctl_offs = 0x308,
74 .pwr_sta_offs = 0x174,
75 .pwr_sta2nd_offs = 0x178,
83 .ctl_offs = 0x30C,
[all …]
H A Dmt8195-pm-domains.h21 .ctl_offs = 0x328,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
42 .ctl_offs = 0x32C,
43 .pwr_sta_offs = 0x174,
44 .pwr_sta2nd_offs = 0x178,
63 .ctl_offs = 0x330,
64 .pwr_sta_offs = 0x174,
65 .pwr_sta2nd_offs = 0x178,
71 .ctl_offs = 0x334,
[all …]
/linux/drivers/staging/rts5208/
H A Dms.h19 #define MS_EXTRA_SIZE 0x9
21 #define WRT_PRTCT 0x01
24 #define MS_NO_ERROR 0x00
25 #define MS_CRC16_ERROR 0x80
26 #define MS_TO_ERROR 0x40
27 #define MS_NO_CARD 0x20
28 #define MS_NO_MEMORY 0x10
29 #define MS_CMD_NK 0x08
30 #define MS_FLASH_READ_ERROR 0x04
31 #define MS_FLASH_WRITE_ERROR 0x02
[all …]
/linux/arch/mips/mm/
H A Dcex-sb1.S31 * the L1 and L2) since it is fetched as 0xa0000100.
35 * (0x170-0x17f) are used to preserve k0, k1, and ra.
48 sd k0,0x170($0)
49 sd k1,0x178($0)
69 mtc0 $0,C0_CERR_D
101 andi k0,0x1fe0
108 cache Index_Invalidate_I,(0<<13)(k0)
117 ld k0,0x170($0)
118 ld k1,0x178($0)
140 bnezl $0, 1f
/linux/Documentation/fault-injection/
H A Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx-anatop.yaml65 reg = <0x020c8000 0x1000>;
75 anatop-reg-offset = <0x120>;
78 anatop-min-bit-val = <0>;
81 anatop-enable-bit = <0>;
90 anatop-reg-offset = <0x140>;
91 anatop-vol-bit-shift = <0>;
93 anatop-delay-reg-offset = <0x170>;
107 anatop-reg-offset = <0x140>;
110 anatop-delay-reg-offset = <0x170>;
126 #thermal-sensor-cells = <0>;
/linux/arch/sparc/kernel/
H A Dkprobes.c31 * - Set regs->tpc to point to kprobe->ainsn.insn[0]
52 if ((unsigned long) p->addr & 0x3UL) in arch_prepare_kprobe()
55 p->ainsn.insn[0] = *p->addr; in arch_prepare_kprobe()
56 flushi(&p->ainsn.insn[0]); in arch_prepare_kprobe()
62 return 0; in arch_prepare_kprobe()
111 regs->tpc = (unsigned long) &p->ainsn.insn[0]; in prepare_singlestep()
120 int ret = 0; in kprobe_handler()
207 if (regs->tnpc == regs->tpc + 0x4UL) in relbranch_fixup()
208 return real_pc + 0x8UL; in relbranch_fixup()
213 if ((insn & 0xc0000000) == 0x40000000 || in relbranch_fixup()
[all …]
/linux/drivers/staging/vc04_services/interface/
H A DTESTING59 vchi ping (size 0) -> 57.000000us
60 vchi ping (size 0, 0 async, 0 oneway) -> 122.000000us
61 vchi bulk (size 0, 0 async, 0 oneway) -> 546.000000us
62 vchi bulk (size 0, 0 oneway) -> 230.000000us
63 vchi ping (size 0) -> 49.000000us
64 vchi ping (size 0, 0 async, 0 oneway) -> 70.000000us
65 vchi bulk (size 0, 0 async, 0 oneway) -> 296.000000us
66 vchi bulk (size 0, 0 oneway) -> 266.000000us
67 vchi ping (size 0, 1 async, 0 oneway) -> 65.000000us
68 vchi bulk (size 0, 0 oneway) -> 456.000000us
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-v5_20.h9 #define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
10 #define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
11 #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
12 #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
13 #define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
14 #define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
15 #define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
H A Dphy-qcom-qmp-pcs-v6_20.h10 #define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
11 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
12 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
13 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
14 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
15 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
16 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
17 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
H A Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v7.h9 #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
11 #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
12 #define QSERDES_V7_TX_TX_BAND 0x24
13 #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
14 #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
15 #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
16 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
18 #define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
[all …]
H A Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_EN_CENTER 0x010
12 #define QSERDES_PLL_SSC_ADJ_PER1 0x014
13 #define QSERDES_PLL_SSC_ADJ_PER2 0x018
14 #define QSERDES_PLL_SSC_PER1 0x01c
15 #define QSERDES_PLL_SSC_PER2 0x020
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
18 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
19 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v6.h11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v7.h11 #define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V7_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V7_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V7_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V7_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V7_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V7_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V7_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V7_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dsprd-mcdt.txt17 reg = <0 0x41490000 0 0x170>;
/linux/tools/testing/selftests/kvm/lib/x86_64/
H A Dsvm.c48 memset(svm->msr_hva, 0, getpagesize()); in vcpu_alloc_svm()
79 memset(vmcb, 0, sizeof(*vmcb)); in generic_svm_setup()
80 asm volatile ("vmsave %0\n\t" : : "a" (vmcb_gpa) : "memory"); in generic_svm_setup()
81 vmcb_set_seg(&save->es, get_es(), 0, -1U, data_seg_attr); in generic_svm_setup()
82 vmcb_set_seg(&save->cs, get_cs(), 0, -1U, code_seg_attr); in generic_svm_setup()
83 vmcb_set_seg(&save->ss, get_ss(), 0, -1U, data_seg_attr); in generic_svm_setup()
84 vmcb_set_seg(&save->ds, get_ds(), 0, -1U, data_seg_attr); in generic_svm_setup()
85 vmcb_set_seg(&save->gdtr, 0, get_gdt().address, get_gdt().size, 0); in generic_svm_setup()
86 vmcb_set_seg(&save->idtr, 0, get_idt().address, get_idt().size, 0); in generic_svm_setup()
89 save->cpl = 0; in generic_svm_setup()
[all …]
/linux/drivers/ata/
H A Dpata_legacy.c70 module_param(probe_all, int, 0);
74 static int probe_mask = ~0;
75 module_param(probe_mask, int, 0);
79 module_param(autospeed, int, 0);
83 module_param(pio_mask, int, 0);
86 static int iordy_mask = 0xFFFFFFFF;
87 module_param(iordy_mask, int, 0);
91 module_param(ht6560a, int, 0);
95 module_param(ht6560b, int, 0);
99 module_param(opti82c611a, int, 0);
[all …]
/linux/include/dt-bindings/clock/
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]

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