Lines Matching +full:0 +full:x170
10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
22 #define QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3 0x01c
23 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
24 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
25 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
26 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
27 #define QSERDES_V5_20_RX_DFE_1 0x088
28 #define QSERDES_V5_20_RX_DFE_2 0x08c
29 #define QSERDES_V5_20_RX_DFE_3 0x090
30 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
31 #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc
32 #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c0
33 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
34 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
35 #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc
36 #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d0
37 #define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d4
38 #define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d8
39 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
40 #define QSERDES_V5_20_RX_GM_CAL 0x0ec
41 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x100
42 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x104
43 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
44 #define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x118
45 #define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c
46 #define QSERDES_V5_20_RX_SIGDET_ENABLES 0x120
47 #define QSERDES_V5_20_RX_SIGDET_CNTRL 0x124
48 #define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c
49 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x160
50 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
51 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
52 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
53 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x170
54 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
55 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
56 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
57 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
58 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
59 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
60 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
61 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
62 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
63 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
64 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
65 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
66 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
67 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
68 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
69 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
70 #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
71 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b8
72 #define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc
73 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
74 #define QSERDES_V5_20_RX_DCC_CTRL1 0x1c4
75 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
76 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
77 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
78 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
79 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
80 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
81 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
82 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
83 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
84 #define QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x238