Lines Matching +full:0 +full:x170
10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
20 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
21 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
22 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
23 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
24 #define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0
25 #define QPHY_V5_PCS_RX_CONFIG 0x1b0
26 #define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0
27 #define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4
28 #define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0
29 #define QPHY_V5_PCS_EQ_CONFIG1 0x1dc
30 #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
31 #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
32 #define QPHY_V5_PCS_EQ_CONFIG5 0x1ec