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/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852bt_rfk_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
[all …]
H A Drtw8852b_rfk_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
[all …]
H A Drtw8852c_rfk_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
[all …]
H A Drtw8851b_rfk_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
[all …]
H A Drtw8852b_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
[all …]
H A Drtw8852c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * It can be changed with DIP switch(S2-5).
9 * phys address | S2-5 = OFF | S2-5 = ON
10 * -----------------------------+---------------+---------------
11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
H A Dcik.c82 .max_level = 0,
133 switch (adev->asic_type) { in cik_query_video_codecs()
143 return 0; in cik_query_video_codecs()
145 return -EINVAL; in cik_query_video_codecs()
157 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
161 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
169 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
174 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
182 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_rreg()
185 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_rreg()
[all …]
H A Dgfx_v8_0.c63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Imagine for use with the Onyx (PCX-U) CPU interface
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmnv44.c30 u32 pteo = (ptei << 2) & ~0x0000000f; in nv44_vmm_pgt_fill()
33 tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0); in nv44_vmm_pgt_fill()
34 tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4); in nv44_vmm_pgt_fill()
35 tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8); in nv44_vmm_pgt_fill()
36 tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc); in nv44_vmm_pgt_fill()
38 while (ptes--) { in nv44_vmm_pgt_fill()
39 u32 addr = (list ? *list++ : vmm->null) >> 12; in nv44_vmm_pgt_fill()
40 switch (ptei++ & 0x3) { in nv44_vmm_pgt_fill()
41 case 0: in nv44_vmm_pgt_fill()
42 tmp[0] &= ~0x07ffffff; in nv44_vmm_pgt_fill()
[all …]
/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsi.c159 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
160 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
161 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
164 (0x8000 << 16) | (0x98f4 >> 2),
165 0x00000000,
166 (0x8040 << 16) | (0x98f4 >> 2),
167 0x00000000,
168 (0x8000 << 16) | (0xe80 >> 2),
169 0x00000000,
170 (0x8040 << 16) | (0xe80 >> 2),
[all …]
H A Dni.c52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
70 0x98fc,
71 0x98f0,
72 0x9834,
73 0x9838,
74 0x9870,
75 0x9874,
[all …]
H A Dcik.c144 * cik_get_allowed_info_register - fetch the register for the info ioctl
150 * Returns 0 for success or -EINVAL for an invalid register
170 return 0; in cik_get_allowed_info_register()
172 return -EINVAL; in cik_get_allowed_info_register()
184 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
187 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
195 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
198 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
205 int actual_temp = 0; in ci_get_temp()
210 if (temp & 0x200) in ci_get_temp()
[all …]
H A Devergreen.c50 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
52 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
62 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
63 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
65 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
73 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
74 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
76 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
84 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Copyright (C) 2007-2016 Broadcom Corporation.
9 * Copyright (C) 2016-2017 Broadcom Limited.
17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
[all …]
/linux/drivers/scsi/elx/libefc_sli/
H A Dsli4.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * All common SLI-4 structures and function prototypes.
22 * Common SLI-4 register offsets and field definitions
25 /* SLI_INTF - SLI Interface Definition Register */
26 #define SLI4_INTF_REG 0x0058
29 SLI4_INTF_REV_MASK = 0xf0,
31 SLI4_INTF_REV_S3 = 0x30,
32 SLI4_INTF_REV_S4 = 0x40,
35 SLI4_INTF_FAMILY_MASK = 0x0f00,
37 SLI4_FAMILY_CHECK_ASIC_TYPE = 0x0f00,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_ethtool.c3 * Copyright (c) 2007-2013 Broadcom Corporation
32 /* Note: in the format strings below %s is replaced by the queue-name which is
34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
196 switch (bp->link_params.phy[phy_idx].media_type) { in bnx2x_get_port_type()
228 cmd->link_modes.supported); in bnx2x_get_vf_link_ksettings()
230 cmd->link_modes.advertising); in bnx2x_get_vf_link_ksettings()
232 if (bp->state == BNX2X_STATE_OPEN) { in bnx2x_get_vf_link_ksettings()
234 &bp->vf_link_vars.link_report_flags)) in bnx2x_get_vf_link_ksettings()
235 cmd->base.duplex = DUPLEX_FULL; in bnx2x_get_vf_link_ksettings()
237 cmd->base.duplex = DUPLEX_HALF; in bnx2x_get_vf_link_ksettings()
[all …]