Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x07ffffff
1 /* SPDX-License-Identifier: GPL-2.0 */
9 * All common SLI-4 structures and function prototypes.
22 * Common SLI-4 register offsets and field definitions
25 /* SLI_INTF - SLI Interface Definition Register */
26 #define SLI4_INTF_REG 0x0058
29 SLI4_INTF_REV_MASK = 0xf0,
31 SLI4_INTF_REV_S3 = 0x30,
32 SLI4_INTF_REV_S4 = 0x40,
35 SLI4_INTF_FAMILY_MASK = 0x0f00,
37 SLI4_FAMILY_CHECK_ASIC_TYPE = 0x0f00,
40 SLI4_INTF_IF_TYPE_MASK = 0xf000,
42 SLI4_INTF_IF_TYPE_2 = 0x2000,
43 SLI4_INTF_IF_TYPE_6 = 0x6000,
46 SLI4_INTF_VALID_MASK = 0xe0000000,
48 SLI4_INTF_VALID_VALUE = 0xc0000000,
51 /* ASIC_ID - SLI ASIC Type and Revision Register */
52 #define SLI4_ASIC_ID_REG 0x009c
55 SLI4_ASIC_GEN_MASK = 0xff00,
56 SLI4_ASIC_GEN_5 = 0x0b00,
57 SLI4_ASIC_GEN_6 = 0x0c00,
58 SLI4_ASIC_GEN_7 = 0x0d00,
62 SLI4_ASIC_REV_A0 = 0x00,
63 SLI4_ASIC_REV_A1 = 0x01,
64 SLI4_ASIC_REV_A2 = 0x02,
65 SLI4_ASIC_REV_A3 = 0x03,
66 SLI4_ASIC_REV_B0 = 0x10,
67 SLI4_ASIC_REV_B1 = 0x11,
68 SLI4_ASIC_REV_B2 = 0x12,
69 SLI4_ASIC_REV_C0 = 0x20,
70 SLI4_ASIC_REV_C1 = 0x21,
71 SLI4_ASIC_REV_C2 = 0x22,
72 SLI4_ASIC_REV_D0 = 0x30,
80 /* BMBX - Bootstrap Mailbox Register */
81 #define SLI4_BMBX_REG 0x0160
83 SLI4_BMBX_MASK_HI = 0x3,
84 SLI4_BMBX_MASK_LO = 0xf,
85 SLI4_BMBX_RDY = 1 << 0,
110 /* SLIPORT_CONTROL - SLI Port Control Register */
111 #define SLI4_PORT_CTRL_REG 0x0408
118 /* SLI4_SLIPORT_ERROR - SLI Port Error Register */
119 #define SLI4_PORT_ERROR1 0x040c
120 #define SLI4_PORT_ERROR2 0x0410
122 /* EQCQ_DOORBELL - EQ and CQ Doorbell Register */
123 #define SLI4_EQCQ_DB_REG 0x120
125 SLI4_EQ_ID_LO_MASK = 0x01ff,
127 SLI4_CQ_ID_LO_MASK = 0x03ff,
129 SLI4_EQCQ_CI_EQ = 0x0200,
131 SLI4_EQCQ_QT_EQ = 0x00000400,
132 SLI4_EQCQ_QT_CQ = 0x00000000,
135 SLI4_EQCQ_ID_HI_MASK = 0xf800,
138 SLI4_EQCQ_NUM_MASK = 0x1fff0000,
140 SLI4_EQCQ_ARM = 0x20000000,
141 SLI4_EQCQ_UNARM = 0x00000000,
168 /* EQ_DOORBELL - EQ Doorbell Register for IF_TYPE = 6*/
169 #define SLI4_IF6_EQ_DB_REG 0x120
171 SLI4_IF6_EQ_ID_MASK = 0x0fff,
174 SLI4_IF6_EQ_NUM_MASK = 0x1fff0000,
188 /* CQ_DOORBELL - CQ Doorbell Register for IF_TYPE = 6 */
189 #define SLI4_IF6_CQ_DB_REG 0xc0
191 SLI4_IF6_CQ_ID_MASK = 0xffff,
194 SLI4_IF6_CQ_NUM_MASK = 0x1fff0000,
208 /* MQ_DOORBELL - MQ Doorbell Register */
209 #define SLI4_MQ_DB_REG 0x0140
210 #define SLI4_IF6_MQ_DB_REG 0x0160
212 SLI4_MQ_ID_MASK = 0xffff,
215 SLI4_MQ_NUM_MASK = 0x3fff0000,
228 /* RQ_DOORBELL - RQ Doorbell Register */
229 #define SLI4_RQ_DB_REG 0x0a0
230 #define SLI4_IF6_RQ_DB_REG 0x0080
232 SLI4_RQ_DB_ID_MASK = 0xffff,
235 SLI4_RQ_DB_NUM_MASK = 0x3fff0000,
248 /* WQ_DOORBELL - WQ Doorbell Register */
249 #define SLI4_IO_WQ_DB_REG 0x040
250 #define SLI4_IF6_WQ_DB_REG 0x040
252 SLI4_WQ_ID_MASK = 0xffff,
255 SLI4_WQ_IDX_MASK = 0xff0000,
258 SLI4_WQ_NUM_MASK = 0x0ff00000,
271 /* SLIPORT_STATUS - SLI Port Status Register */
272 #define SLI4_PORT_STATUS_REGOFF 0x0404
282 #define SLI4_PHYDEV_CTRL_REG 0x0414
314 * a 3-word Buffer Descriptor Entry with
324 SLI4_BDE_LEN_MASK = 0x00ffffff,
325 SLI4_BDE_TYPE_MASK = 0xff000000,
343 SLI4_BDE_TYPE_64 = 0x00, /* Generic 64-bit data */
344 SLI4_BDE_TYPE_IMM = 0x01, /* Immediate data */
345 SLI4_BDE_TYPE_BLP = 0x40, /* Buffer List Pointer */
351 /* Scatter-Gather Entry (SGE) */
356 SLI4_SGE_DATA_OFFSET_MASK = 0x07ffffff,
359 SLI4_SGE_TYPE_MASK = 0x78000000,
361 SLI4_SGE_TYPE_DATA = 0x00,
362 SLI4_SGE_TYPE_DIF = 0x04, /* Data Integrity Field */
363 SLI4_SGE_TYPE_LSP = 0x05, /* List Segment Pointer */
364 SLI4_SGE_TYPE_PEDIF = 0x06, /* Post Encryption Engine DIF */
365 SLI4_SGE_TYPE_PESEED = 0x07, /* Post Encryption DIF Seed */
366 SLI4_SGE_TYPE_DISEED = 0x08, /* DIF Seed */
367 SLI4_SGE_TYPE_ENC = 0x09, /* Encryption */
368 SLI4_SGE_TYPE_ATM = 0x0a, /* DIF Application Tag Mask */
369 SLI4_SGE_TYPE_SKIP = 0x0c, /* SKIP */
381 /* T10 DIF Scatter-Gather Entry (SGE) */
403 SLI4_DISEED_SGE_BS_MASK = 0x0007,
411 SLI4_DISEED_SGE_OP_RX_MASK = 0x0f00,
413 SLI4_DISEED_SGE_OP_TX_MASK = 0xf000,
443 /* List Segment Pointer Scatter-Gather Entry (SGE) */
444 #define SLI4_LSP_SGE_SEGLEN 0x00ffffff
455 SLI4_EQE_MJCODE = 0xe,
456 SLI4_EQE_MNCODE = 0xfff0,
464 #define SLI4_MAJOR_CODE_STANDARD 0
478 #define SLI4_MCQE_STATUS_NOT_COMPLETED -2
489 SLI4_ACQE_AE = 1 << 6, /* async event - this is an ACQE */
490 SLI4_ACQE_VAL = 1 << 7, /* valid - contents of CQE are valid */
502 SLI4_ACQE_EVENT_CODE_LINK_STATE = 0x01,
503 SLI4_ACQE_EVENT_CODE_FIP = 0x02,
504 SLI4_ACQE_EVENT_CODE_DCBX = 0x03,
505 SLI4_ACQE_EVENT_CODE_ISCSI = 0x04,
506 SLI4_ACQE_EVENT_CODE_GRP_5 = 0x05,
507 SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT = 0x10,
508 SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT = 0x11,
509 SLI4_ACQE_EVENT_CODE_VF_EVENT = 0x12,
510 SLI4_ACQE_EVENT_CODE_MR_EVENT = 0x13,
539 SLI4_QUEUE_FLAG_MQ = 1 << 0, /* CQ has MQ/Async completion */
578 cpu_to_le32(sizeof(struct sli4_rqst_##stype) - \
583 varpyld) - sizeof(struct sli4_rqst_hdr))
591 SLI4_CREATE_CQV2_CLSWM_MASK = 0x00003000,
592 SLI4_CREATE_CQV2_NODELAY = 0x00004000,
593 SLI4_CREATE_CQV2_AUTOVALID = 0x00008000,
594 SLI4_CREATE_CQV2_CQECNT_MASK = 0x18000000,
595 SLI4_CREATE_CQV2_VALID = 0x20000000,
596 SLI4_CREATE_CQV2_EVT = 0x80000000,
598 SLI4_CREATE_CQV2_ARM = 0x8000,
617 SLI4_CREATE_CQSETV0_CLSWM_MASK = 0x00003000,
618 SLI4_CREATE_CQSETV0_NODELAY = 0x00004000,
619 SLI4_CREATE_CQSETV0_AUTOVALID = 0x00008000,
620 SLI4_CREATE_CQSETV0_CQECNT_MASK = 0x18000000,
621 SLI4_CREATE_CQSETV0_VALID = 0x20000000,
622 SLI4_CREATE_CQSETV0_EVT = 0x80000000,
624 SLI4_CREATE_CQSETV0_CQE_COUNT = 0x7fff,
625 SLI4_CREATE_CQSETV0_ARM = 0x8000,
710 SLI4_CREATE_EQ_DELAYMULTI_MASK = 0x007fe000,
711 SLI4_CREATE_EQ_DELAYMULTI = 0x00040000,
741 #define SLI4_EQE_SIZE_4 0
747 SLI4_CREATE_MQEXT_RINGSIZE = 0xf,
749 SLI4_CREATE_MQEXT_CQIDV0_MASK = 0xffc0,
753 SLI4_CREATE_MQEXT_ACQV = 1u << 0,
754 SLI4_CREATE_MQEXT_ASYNC_CQIDV0 = 0x7fe,
775 SLI4_MQE_SIZE_16 = 0x05,
809 SLI4_RQ_CREATE_DUA = 0x1,
810 SLI4_RQ_CREATE_BQU = 0x2,
813 SLI4_RQE_SIZE_8 = 0x2,
814 SLI4_RQE_SIZE_16 = 0x3,
815 SLI4_RQE_SIZE_32 = 0x4,
816 SLI4_RQE_SIZE_64 = 0x5,
817 SLI4_RQE_SIZE_128 = 0x6,
819 SLI4_RQ_PAGE_SIZE_4096 = 0x1,
820 SLI4_RQ_PAGE_SIZE_8192 = 0x2,
821 SLI4_RQ_PAGE_SIZE_16384 = 0x4,
822 SLI4_RQ_PAGE_SIZE_32768 = 0x8,
823 SLI4_RQ_PAGE_SIZE_64536 = 0x10,
850 SLI4_RQ_CREATE_V1_DNB = 0x80,
875 #define SLI4_RQCREATEV2_DNB 0x80
900 SLI4_CQE_CODE_WORK_REQUEST_COMPLETION = 0x01,
932 SLI4_LNK_ATTN_TYPE_LINK_UP = 0x01,
933 SLI4_LNK_ATTN_TYPE_LINK_DOWN = 0x02,
934 SLI4_LNK_ATTN_TYPE_NO_HARD_ALPA = 0x03,
936 SLI4_LNK_ATTN_P2P = 0x01,
937 SLI4_LNK_ATTN_FC_AL = 0x02,
938 SLI4_LNK_ATTN_INTERNAL_LOOPBACK = 0x03,
939 SLI4_LNK_ATTN_SERDES_LOOPBACK = 0x04,
958 SLI4_EVENT_LINK_ATTENTION = 0x01,
959 SLI4_EVENT_SHARED_LINK_ATTENTION = 0x02,
963 SLI4_WCQE_XB = 0x10,
964 SLI4_WCQE_QX = 0x80,
1022 SLI4_FC_WCQE_STATUS_DISPATCH_ERROR = 0xfd,
1023 SLI4_FC_WCQE_STATUS_SHUTDOWN = 0xfe,
1024 SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT = 0xff,
1029 SLI4_FC_DI_ERROR_GE = 1 << 0,
1047 SLI4_WQE_ABORT = 0x0f,
1048 SLI4_WQE_ELS_REQUEST64 = 0x8a,
1049 SLI4_WQE_FCP_IBIDIR64 = 0xac,
1050 SLI4_WQE_FCP_IREAD64 = 0x9a,
1051 SLI4_WQE_FCP_IWRITE64 = 0x98,
1052 SLI4_WQE_FCP_ICMND64 = 0x9c,
1053 SLI4_WQE_FCP_TRECEIVE64 = 0xa1,
1054 SLI4_WQE_FCP_CONT_TRECEIVE64 = 0xe5,
1055 SLI4_WQE_FCP_TRSP64 = 0xa3,
1056 SLI4_WQE_FCP_TSEND64 = 0x9f,
1057 SLI4_WQE_GEN_REQUEST64 = 0xc2,
1058 SLI4_WQE_SEND_FRAME = 0xe1,
1059 SLI4_WQE_XMIT_BCAST64 = 0x84,
1060 SLI4_WQE_XMIT_BLS_RSP = 0x97,
1061 SLI4_WQE_ELS_RSP64 = 0x95,
1062 SLI4_WQE_XMIT_SEQUENCE64 = 0x82,
1063 SLI4_WQE_REQUEUE_XRI = 0x93,
1068 SLI4_CMD_FCP_IREAD64_WQE = 0x00,
1069 SLI4_CMD_FCP_ICMND64_WQE = 0x00,
1070 SLI4_CMD_FCP_IWRITE64_WQE = 0x01,
1071 SLI4_CMD_FCP_TRECEIVE64_WQE = 0x02,
1072 SLI4_CMD_FCP_TRSP64_WQE = 0x03,
1073 SLI4_CMD_FCP_TSEND64_WQE = 0x07,
1074 SLI4_CMD_GEN_REQUEST64_WQE = 0x08,
1075 SLI4_CMD_XMIT_BCAST64_WQE = 0x08,
1076 SLI4_CMD_XMIT_BLS_RSP64_WQE = 0x08,
1077 SLI4_CMD_ABORT_WQE = 0x08,
1078 SLI4_CMD_XMIT_SEQUENCE64_WQE = 0x08,
1079 SLI4_CMD_REQUEUE_XRI_WQE = 0x0a,
1080 SLI4_CMD_SEND_FRAME_WQE = 0x0a,
1083 #define SLI4_WQE_SIZE 0x05
1084 #define SLI4_WQE_EXT_SIZE 0x06
1090 #define SLI4_MASK_CCP 0xfe
1094 SLI4_GEN_WQE_EBDECNT = 0xf,
1095 SLI4_GEN_WQE_LEN_LOC = 0x3 << 7,
1103 SLI4_GEN_WQE_PRI = 0x7,
1109 SLI4_GEN_WQE_CMDTYPE = 0xf,
1134 SLI4_ABRT_WQE_IR = 0x02,
1136 SLI4_ABRT_WQE_EBDECNT = 0xf,
1137 SLI4_ABRT_WQE_LEN_LOC = 0x3 << 7,
1144 SLI4_ABRT_WQE_PRI = 0x7,
1150 SLI4_ABRT_WQE_CMDTYPE = 0xf,
1181 SLI4_ABORT_CRITERIA_XRI_TAG = 0x01,
1196 SLI4_REQ_WQE_QOSD = 0x2,
1197 SLI4_REQ_WQE_DBDE = 0x40,
1198 SLI4_REQ_WQE_XBL = 0x8,
1199 SLI4_REQ_WQE_XC = 0x20,
1200 SLI4_REQ_WQE_IOD = 0x20,
1201 SLI4_REQ_WQE_HLM = 0x10,
1202 SLI4_REQ_WQE_CCPE = 0x80,
1203 SLI4_REQ_WQE_EAT = 0x10,
1204 SLI4_REQ_WQE_WQES = 0x80,
1207 SLI4_REQ_WQE_CT = 0xc,
1210 SLI4_REQ_WQE_LEN_LOC_BIT1 = 0x80,
1211 SLI4_REQ_WQE_LEN_LOC_BIT2 = 0x1,
1241 SLI4_ICMD_WQE_DBDE = 0x40,
1242 SLI4_ICMD_WQE_XBL = 0x8,
1243 SLI4_ICMD_WQE_XC = 0x20,
1244 SLI4_ICMD_WQE_IOD = 0x20,
1245 SLI4_ICMD_WQE_HLM = 0x10,
1246 SLI4_ICMD_WQE_CCPE = 0x80,
1247 SLI4_ICMD_WQE_EAT = 0x10,
1248 SLI4_ICMD_WQE_APPID = 0x10,
1249 SLI4_ICMD_WQE_WQES = 0x80,
1253 SLI4_ICMD_WQE_LEN_LOC_BIT1 = 0x80,
1254 SLI4_ICMD_WQE_LEN_LOC_BIT2 = 0x1,
1287 SLI4_IR_WQE_DBDE = 0x40,
1288 SLI4_IR_WQE_XBL = 0x8,
1289 SLI4_IR_WQE_XC = 0x20,
1290 SLI4_IR_WQE_IOD = 0x20,
1291 SLI4_IR_WQE_HLM = 0x10,
1292 SLI4_IR_WQE_CCPE = 0x80,
1293 SLI4_IR_WQE_EAT = 0x10,
1294 SLI4_IR_WQE_APPID = 0x10,
1295 SLI4_IR_WQE_WQES = 0x80,
1299 SLI4_IR_WQE_LEN_LOC_BIT1 = 0x80,
1300 SLI4_IR_WQE_LEN_LOC_BIT2 = 0x1,
1340 SLI4_IWR_WQE_DBDE = 0x40,
1341 SLI4_IWR_WQE_XBL = 0x8,
1342 SLI4_IWR_WQE_XC = 0x20,
1343 SLI4_IWR_WQE_IOD = 0x20,
1344 SLI4_IWR_WQE_HLM = 0x10,
1345 SLI4_IWR_WQE_DNRX = 0x10,
1346 SLI4_IWR_WQE_CCPE = 0x80,
1347 SLI4_IWR_WQE_EAT = 0x10,
1348 SLI4_IWR_WQE_APPID = 0x10,
1349 SLI4_IWR_WQE_WQES = 0x80,
1353 SLI4_IWR_WQE_LEN_LOC_BIT1 = 0x80,
1354 SLI4_IWR_WQE_LEN_LOC_BIT2 = 0x1,
1389 SLI4_TRCV_WQE_DBDE = 0x40,
1390 SLI4_TRCV_WQE_XBL = 0x8,
1391 SLI4_TRCV_WQE_AR = 0x8,
1392 SLI4_TRCV_WQE_XC = 0x20,
1393 SLI4_TRCV_WQE_IOD = 0x20,
1394 SLI4_TRCV_WQE_HLM = 0x10,
1395 SLI4_TRCV_WQE_DNRX = 0x10,
1396 SLI4_TRCV_WQE_CCPE = 0x80,
1397 SLI4_TRCV_WQE_EAT = 0x10,
1398 SLI4_TRCV_WQE_APPID = 0x10,
1399 SLI4_TRCV_WQE_WQES = 0x80,
1403 SLI4_TRCV_WQE_LEN_LOC_BIT2 = 0x1,
1437 SLI4_TRSP_WQE_AG = 0x8,
1438 SLI4_TRSP_WQE_DBDE = 0x40,
1439 SLI4_TRSP_WQE_XBL = 0x8,
1440 SLI4_TRSP_WQE_XC = 0x20,
1441 SLI4_TRSP_WQE_HLM = 0x10,
1442 SLI4_TRSP_WQE_DNRX = 0x10,
1443 SLI4_TRSP_WQE_CCPE = 0x80,
1444 SLI4_TRSP_WQE_EAT = 0x10,
1445 SLI4_TRSP_WQE_APPID = 0x10,
1446 SLI4_TRSP_WQE_WQES = 0x80,
1478 SLI4_TSEND_WQE_XBL = 0x8,
1479 SLI4_TSEND_WQE_DBDE = 0x40,
1480 SLI4_TSEND_WQE_IOD = 0x20,
1481 SLI4_TSEND_WQE_QOSD = 0x2,
1482 SLI4_TSEND_WQE_HLM = 0x10,
1484 SLI4_TSEND_WQE_AR = 0x8,
1487 SLI4_TSEND_LEN_LOC_BIT2 = 0x1,
1488 SLI4_TSEND_CCPE = 0x80,
1489 SLI4_TSEND_APPID_VALID = 0x20,
1490 SLI4_TSEND_WQES = 0x80,
1491 SLI4_TSEND_XC = 0x20,
1492 SLI4_TSEND_EAT = 0x10,
1522 SLI4_GEN_REQ64_WQE_XBL = 0x8,
1523 SLI4_GEN_REQ64_WQE_DBDE = 0x40,
1524 SLI4_GEN_REQ64_WQE_IOD = 0x20,
1525 SLI4_GEN_REQ64_WQE_QOSD = 0x2,
1526 SLI4_GEN_REQ64_WQE_HLM = 0x10,
1562 SLI4_SF_WQE_DBDE = 0x40,
1563 SLI4_SF_PU = 0x30,
1564 SLI4_SF_CT = 0xc,
1565 SLI4_SF_QOSD = 0x2,
1566 SLI4_SF_LEN_LOC_BIT1 = 0x80,
1567 SLI4_SF_LEN_LOC_BIT2 = 0x1,
1568 SLI4_SF_XC = 0x20,
1569 SLI4_SF_XBL = 0x8,
1598 SLI4_SEQ_WQE_DBDE = 0x4000,
1599 SLI4_SEQ_WQE_XBL = 0x800,
1600 SLI4_SEQ_WQE_SI = 0x4,
1601 SLI4_SEQ_WQE_FT = 0x8,
1602 SLI4_SEQ_WQE_XO = 0x40,
1603 SLI4_SEQ_WQE_LS = 0x80,
1604 SLI4_SEQ_WQE_DIF = 0x3,
1605 SLI4_SEQ_WQE_BS = 0x70,
1606 SLI4_SEQ_WQE_PU = 0x30,
1607 SLI4_SEQ_WQE_HLM = 0x1000,
1647 SLI4_REQU_XRI_WQE_XC = 0x20,
1648 SLI4_REQU_XRI_WQE_QOSD = 0x2,
1682 SLI4_BLS_RSP_RID = 0xffffff,
1683 SLI4_BLS_RSP_WQE_AR = 0x40000000,
1685 SLI4_BLS_RSP_WQE_QOSD = 0x2,
1686 SLI4_BLS_RSP_WQE_HLM = 0x10,
1755 SLI4_ELS_SID = 0xffffff,
1756 SLI4_ELS_RID = 0xffffff,
1757 SLI4_ELS_DBDE = 0x40,
1758 SLI4_ELS_XBL = 0x8,
1759 SLI4_ELS_IOD = 0x20,
1760 SLI4_ELS_QOSD = 0x2,
1761 SLI4_ELS_XC = 0x20,
1762 SLI4_ELS_CT_OFFSET = 0X2,
1763 SLI4_ELS_SP = 0X1000000,
1764 SLI4_ELS_HLM = 0X10,
1814 SLI4_FC_LOCAL_REJECT_NO_RESOURCES, //0x11
1829 SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME, //0x20
1835 SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE = 0x28,
1837 SLI4_FC_LOCAL_REJECT_INVALID_VPI = 0x2e,
1842 SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET = 0x40,
1860 SLI4_RACQE_RQ_EL_INDX = 0xfff,
1861 SLI4_RACQE_FCFI = 0x3f,
1862 SLI4_RACQE_HDPL = 0x3f,
1863 SLI4_RACQE_RQ_ID = 0xffc0,
1895 SLI4_FC_ASYNC_RQ_SUCCESS = 0x10,
1902 #define SLI4_RCQE_RQ_EL_INDX 0xfff
1916 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10
1917 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18
1920 SLI4_OCQE_RQ_EL_INDX = 0x7f, /* DW0 bits 16:30 */
1921 SLI4_OCQE_FCFI = 0x3f, /* DW1 bits 0:6 */
1924 SLI4_OCQE_HDPL = 0x3f, /* DW3 bits 24:29*/
1941 #define SLI4_OCQE_XB 0x10
1973 #define SLI4_GENERIC_CLASS_CLASS_2 0x1
1974 #define SLI4_GENERIC_CLASS_CLASS_3 0x2
1976 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0
1977 #define SLI4_ELS_REQUEST64_DIR_READ 0x1
1988 SLI4_ELS_REQUEST64_CMD_GEN = 0x08,
1989 SLI4_ELS_REQUEST64_CMD_NON_FABRIC = 0x0c,
1990 SLI4_ELS_REQUEST64_CMD_FABRIC = 0x0d,
2005 return 0; in sli_page_count()
2007 return (bytes + (page_size - 1)) >> __ffs(page_size); in sli_page_count()
2011 * SLI-4 mailbox command formats and definitions
2021 SLI4_MBX_CMD_CONFIG_LINK = 0x07,
2022 SLI4_MBX_CMD_DUMP = 0x17,
2023 SLI4_MBX_CMD_DOWN_LINK = 0x06,
2024 SLI4_MBX_CMD_INIT_LINK = 0x05,
2025 SLI4_MBX_CMD_INIT_VFI = 0xa3,
2026 SLI4_MBX_CMD_INIT_VPI = 0xa4,
2027 SLI4_MBX_CMD_POST_XRI = 0xa7,
2028 SLI4_MBX_CMD_RELEASE_XRI = 0xac,
2029 SLI4_MBX_CMD_READ_CONFIG = 0x0b,
2030 SLI4_MBX_CMD_READ_STATUS = 0x0e,
2031 SLI4_MBX_CMD_READ_NVPARMS = 0x02,
2032 SLI4_MBX_CMD_READ_REV = 0x11,
2033 SLI4_MBX_CMD_READ_LNK_STAT = 0x12,
2034 SLI4_MBX_CMD_READ_SPARM64 = 0x8d,
2035 SLI4_MBX_CMD_READ_TOPOLOGY = 0x95,
2036 SLI4_MBX_CMD_REG_FCFI = 0xa0,
2037 SLI4_MBX_CMD_REG_FCFI_MRQ = 0xaf,
2038 SLI4_MBX_CMD_REG_RPI = 0x93,
2039 SLI4_MBX_CMD_REG_RX_RQ = 0xa6,
2040 SLI4_MBX_CMD_REG_VFI = 0x9f,
2041 SLI4_MBX_CMD_REG_VPI = 0x96,
2042 SLI4_MBX_CMD_RQST_FEATURES = 0x9d,
2043 SLI4_MBX_CMD_SLI_CONFIG = 0x9b,
2044 SLI4_MBX_CMD_UNREG_FCFI = 0xa2,
2045 SLI4_MBX_CMD_UNREG_RPI = 0x14,
2046 SLI4_MBX_CMD_UNREG_VFI = 0xa1,
2047 SLI4_MBX_CMD_UNREG_VPI = 0x97,
2048 SLI4_MBX_CMD_WRITE_NVPARMS = 0x03,
2049 SLI4_MBX_CMD_CFG_AUTO_XFER_RDY = 0xad,
2053 SLI4_MBX_STATUS_SUCCESS = 0x0000,
2054 SLI4_MBX_STATUS_FAILURE = 0x0001,
2055 SLI4_MBX_STATUS_RPI_NOT_REG = 0x1400,
2058 /* CONFIG_LINK - configure link-oriented parameters,
2062 SLI4_CFG_LINK_BBSCN = 0xf00,
2063 SLI4_CFG_LINK_CSCN = 0x1000,
2085 #define SLI4_DUMP4_TYPE 0xf
2087 #define SLI4_WKI_TAG_SAT_TEM 0x1040
2099 /* INIT_LINK - initialize the link for a FC port */
2101 SLI4_INIT_LINK_F_LOOPBACK = 1 << 0,
2105 SLI4_INIT_LINK_F_FCAL_FAIL_OVER = 0 << 1,
2155 /* INIT_VFI - initialize the VFI resource */
2157 SLI4_INIT_VFI_FLAG_VP = 0x1000,
2158 SLI4_INIT_VFI_FLAG_VF = 0x2000,
2159 SLI4_INIT_VFI_FLAG_VT = 0x4000,
2160 SLI4_INIT_VFI_FLAG_VR = 0x8000,
2162 SLI4_INIT_VFI_VFID = 0x1fff,
2163 SLI4_INIT_VFI_PRI = 0xe000,
2165 SLI4_INIT_VFI_HOP_COUNT = 0xff000000,
2178 /* INIT_VPI - initialize the VPI resource */
2185 /* POST_XRI - post XRI resources to the SLI Port */
2187 SLI4_POST_XRI_COUNT = 0xfff,
2188 SLI4_POST_XRI_FLAG_ENX = 0x1000,
2189 SLI4_POST_XRI_FLAG_DL = 0x2000,
2190 SLI4_POST_XRI_FLAG_DI = 0x4000,
2191 SLI4_POST_XRI_FLAG_VAL = 0x8000,
2200 /* RELEASE_XRI - Release XRI resources from the SLI Port */
2202 SLI4_RELEASE_XRI_REL_XRI_CNT = 0x1f,
2203 SLI4_RELEASE_XRI_COUNT = 0x1f,
2217 /* READ_CONFIG - read SLI port configuration parameters */
2223 SLI4_READ_CFG_RESP_RESOURCE_EXT = 0x80000000, /* DW1 */
2224 SLI4_READ_CFG_RESP_TOPOLOGY = 0xff000000, /* DW2 */
2228 SLI4_READ_CFG_TOPO_FC = 0x1, /* FC topology unknown */
2229 SLI4_READ_CFG_TOPO_NON_FC_AL = 0x2, /* FC point-to-point or fabric */
2230 SLI4_READ_CFG_TOPO_FC_AL = 0x3, /* FC-AL topology */
2235 SLI4_LINK_MODULE_TYPE_1GB = 0x0004,
2236 SLI4_LINK_MODULE_TYPE_2GB = 0x0008,
2237 SLI4_LINK_MODULE_TYPE_4GB = 0x0040,
2238 SLI4_LINK_MODULE_TYPE_8GB = 0x0080,
2239 SLI4_LINK_MODULE_TYPE_16GB = 0x0200,
2240 SLI4_LINK_MODULE_TYPE_32GB = 0x0400,
2241 SLI4_LINK_MODULE_TYPE_64GB = 0x0800,
2242 SLI4_LINK_MODULE_TYPE_128GB = 0x1000,
2278 /* READ_NVPARMS - read SLI port configuration parameters */
2280 SLI4_READ_NVPARAMS_HARD_ALPA = 0xff,
2281 SLI4_READ_NVPARAMS_PREFERRED_D_ID = 0xffffff00,
2295 /* WRITE_NVPARMS - write SLI port configuration parameters */
2307 /* READ_REV - read the Port revision levels */
2309 SLI4_READ_REV_FLAG_SLI_LEVEL = 0xf,
2310 SLI4_READ_REV_FLAG_FCOEM = 0x10,
2311 SLI4_READ_REV_FLAG_CEEV = 0x60,
2312 SLI4_READ_REV_FLAG_VPD = 0x2000,
2314 SLI4_READ_REV_AVAILABLE_LENGTH = 0xffffff,
2341 /* READ_SPARM64 - read the Port service parameters */
2358 /* READ_TOPOLOGY - read the link event information */
2360 SLI4_READTOPO_ATTEN_TYPE = 0xff,
2361 SLI4_READTOPO_FLAG_IL = 0x100,
2362 SLI4_READTOPO_FLAG_PB_RECVD = 0x200,
2364 SLI4_READTOPO_LINKSTATE_RECV = 0x3,
2365 SLI4_READTOPO_LINKSTATE_TRANS = 0xc,
2366 SLI4_READTOPO_LINKSTATE_MACHINE = 0xf0,
2367 SLI4_READTOPO_LINKSTATE_SPEED = 0xff00,
2368 SLI4_READTOPO_LINKSTATE_TF = 0x40000000,
2369 SLI4_READTOPO_LINKSTATE_LU = 0x80000000,
2371 SLI4_READTOPO_SCN_BBSCN = 0xf,
2372 SLI4_READTOPO_SCN_CBBSCN = 0xf0,
2374 SLI4_READTOPO_R_T_TOV = 0x1ff,
2375 SLI4_READTOPO_AL_TOV = 0xf000,
2377 SLI4_READTOPO_PB_FLAG = 0x80,
2379 SLI4_READTOPO_INIT_N_PORTID = 0xffffff,
2408 SLI4_READ_TOPOLOGY_LINK_UP = 0x1,
2414 SLI4_READ_TOPO_UNKNOWN = 0x0,
2420 SLI4_READ_TOPOLOGY_SPEED_NONE = 0x00,
2421 SLI4_READ_TOPOLOGY_SPEED_1G = 0x04,
2422 SLI4_READ_TOPOLOGY_SPEED_2G = 0x08,
2423 SLI4_READ_TOPOLOGY_SPEED_4G = 0x10,
2424 SLI4_READ_TOPOLOGY_SPEED_8G = 0x20,
2425 SLI4_READ_TOPOLOGY_SPEED_10G = 0x40,
2426 SLI4_READ_TOPOLOGY_SPEED_16G = 0x80,
2427 SLI4_READ_TOPOLOGY_SPEED_32G = 0x90,
2428 SLI4_READ_TOPOLOGY_SPEED_64G = 0xa0,
2429 SLI4_READ_TOPOLOGY_SPEED_128G = 0xb0,
2432 /* REG_FCFI - activate a FC Forwarder */
2441 SLI4_REGFCFI_VLAN_TAG = 0xfff,
2442 SLI4_REGFCFI_VLANTAG_VALID = 0x1000,
2461 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0
2465 SLI4_REGFCFI_MRQ_VLAN_TAG = 0xfff,
2466 SLI4_REGFCFI_MRQ_VLANTAG_VALID = 0x1000,
2467 SLI4_REGFCFI_MRQ_MODE = 0x2000,
2469 SLI4_REGFCFI_MRQ_MASK_NUM_PAIRS = 0xff,
2470 SLI4_REGFCFI_MRQ_FILTER_BITMASK = 0xf00,
2471 SLI4_REGFCFI_MRQ_RQ_SEL_POLICY = 0xf000,
2496 /* REG_RPI - register a Remote Port Indicator */
2498 SLI4_REGRPI_REMOTE_N_PORTID = 0xffffff, /* DW2 */
2499 SLI4_REGRPI_UPD = 0x1000000,
2500 SLI4_REGRPI_ETOW = 0x8000000,
2501 SLI4_REGRPI_TERP = 0x20000000,
2502 SLI4_REGRPI_CI = 0x80000000,
2515 #define SLI4_REG_RPI_BUF_LEN 0x70
2517 /* REG_VFI - register a Virtual Fabric Indicator */
2519 SLI4_REGVFI_VP = 0x1000, /* DW1 */
2520 SLI4_REGVFI_UPD = 0x2000,
2522 SLI4_REGVFI_LOCAL_N_PORTID = 0xffffff, /* DW10 */
2538 /* REG_VPI - register a Virtual Port Indicator */
2540 SLI4_REGVPI_LOCAL_N_PORTID = 0xffffff,
2541 SLI4_REGVPI_UPD = 0x1000000,
2554 /* REQUEST_FEATURES - request / query SLI features */
2556 SLI4_REQFEAT_QRY = 0x1, /* Dw1 */
2558 SLI4_REQFEAT_IAAB = 1 << 0, /* DW2 & DW3 */
2585 * SLI_CONFIG - submit a configuration command to Port
2591 SLI4_SLICONF_EMB = 0x1, /* DW1 */
2593 SLI4_SLICONF_PMDCMD_MASK = 0xf8,
2595 SLI4_SLICONF_PMDCNT = 0xf8,
2597 SLI4_SLICONF_PMD_LEN = 0x00ffffff,
2611 /* READ_STATUS - read tx/rx status of a particular port */
2612 #define SLI4_READSTATUS_CLEAR_COUNTERS 0x1
2634 /* READ_LNK_STAT - read link status of a particular port */
2636 SLI4_READ_LNKSTAT_REC = 1u << 0,
2694 * Set Word 10, bit 0 to zero in sli_set_wq_id_association()
2697 wqe[10] &= ~0xffff; in sli_set_wq_id_association()
2701 /* UNREG_FCFI - unregister a FCFI */
2709 /* UNREG_RPI - unregister one or more RPI */
2711 SLI4_UNREG_RPI_DP = 0x2000,
2713 SLI4_UNREG_RPI_II_MASK = 0xc000,
2714 SLI4_UNREG_RPI_II_RPI = 0x0000,
2715 SLI4_UNREG_RPI_II_VPI = 0x4000,
2716 SLI4_UNREG_RPI_II_VFI = 0x8000,
2717 SLI4_UNREG_RPI_II_FCFI = 0xc000,
2719 SLI4_UNREG_RPI_DEST_N_PORTID_MASK = 0x00ffffff,
2729 /* UNREG_VFI - unregister one or more VFI */
2732 SLI4_UNREG_VFI_II_MASK = 0xc000,
2733 SLI4_UNREG_VFI_II_VFI = 0x0000,
2734 SLI4_UNREG_VFI_II_FCFI = 0xc000,
2751 /* UNREG_VPI - unregister one or more VPI */
2754 SLI4_UNREG_VPI_II_MASK = 0xc000,
2755 SLI4_UNREG_VPI_II_VPI = 0x0000,
2756 SLI4_UNREG_VPI_II_VFI = 0x8000,
2757 SLI4_UNREG_VPI_II_FCFI = 0xc000,
2767 /* AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature */
2774 #define SLI4_CONFIG_AUTO_XFERRDY_BLKSIZE 0xffff
2786 * SLI-4 common configuration command formats and definitions
2793 SLI4_SUBSYSTEM_COMMON = 0x01,
2794 SLI4_SUBSYSTEM_LOWLEVEL = 0x0b,
2795 SLI4_SUBSYSTEM_FC = 0x0c,
2796 SLI4_SUBSYSTEM_DMTF = 0x11,
2799 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36
2805 SLI4_CMN_FUNCTION_RESET = 0x3d,
2806 SLI4_CMN_CREATE_CQ = 0x0c,
2807 SLI4_CMN_CREATE_CQ_SET = 0x1d,
2808 SLI4_CMN_DESTROY_CQ = 0x36,
2809 SLI4_CMN_MODIFY_EQ_DELAY = 0x29,
2810 SLI4_CMN_CREATE_EQ = 0x0d,
2811 SLI4_CMN_DESTROY_EQ = 0x37,
2812 SLI4_CMN_CREATE_MQ_EXT = 0x5a,
2813 SLI4_CMN_DESTROY_MQ = 0x35,
2814 SLI4_CMN_GET_CNTL_ATTRIBUTES = 0x20,
2815 SLI4_CMN_NOP = 0x21,
2816 SLI4_CMN_GET_RSC_EXTENT_INFO = 0x9a,
2817 SLI4_CMN_GET_SLI4_PARAMS = 0xb5,
2818 SLI4_CMN_QUERY_FW_CONFIG = 0x3a,
2819 SLI4_CMN_GET_PORT_NAME = 0x4d,
2821 SLI4_CMN_WRITE_FLASHROM = 0x07,
2823 SLI4_CMN_READ_TRANS_DATA = 0x49,
2824 SLI4_CMN_GET_CNTL_ADDL_ATTRS = 0x79,
2825 SLI4_CMN_GET_FUNCTION_CFG = 0xa0,
2826 SLI4_CMN_GET_PROFILE_CFG = 0xa4,
2827 SLI4_CMN_SET_PROFILE_CFG = 0xa5,
2828 SLI4_CMN_GET_PROFILE_LIST = 0xa6,
2829 SLI4_CMN_GET_ACTIVE_PROFILE = 0xa7,
2830 SLI4_CMN_SET_ACTIVE_PROFILE = 0xa8,
2831 SLI4_CMN_READ_OBJECT = 0xab,
2832 SLI4_CMN_WRITE_OBJECT = 0xac,
2833 SLI4_CMN_DELETE_OBJECT = 0xae,
2834 SLI4_CMN_READ_OBJECT_LIST = 0xad,
2835 SLI4_CMN_SET_DUMP_LOCATION = 0xb8,
2836 SLI4_CMN_SET_FEATURES = 0xbf,
2837 SLI4_CMN_GET_RECFG_LINK_INFO = 0xc9,
2838 SLI4_CMN_SET_RECNG_LINK_ID = 0xca,
2842 #define DMTF_EXEC_CLP_CMD 0x01
2847 * Resets the Port, returning it to a power-on state. This configuration
2865 SLI4_CNTL_ATTR_PORTNUM = 0x3f,
2866 SLI4_CNTL_ATTR_PORTTYPE = 0xc0,
2984 SLI4_RSC_TYPE_VFI = 0x20,
2985 SLI4_RSC_TYPE_VPI = 0x21,
2986 SLI4_RSC_TYPE_RPI = 0x22,
2987 SLI4_RSC_TYPE_XRI = 0x23,
2996 #define SLI4_128BYTE_WQE_SUPPORT 0x02
3006 SLI4_PARAM_Q_CNT_MTHD_MASK = 0xf << 24,
3011 SLI4_PARAM_PROTO_TYPE_MASK = 0xff,
3013 SLI4_PARAM_FT = 1 << 0,
3014 SLI4_PARAM_SLI_REV_MASK = 0xf << 4,
3015 SLI4_PARAM_SLI_FAM_MASK = 0xf << 8,
3016 SLI4_PARAM_IF_TYPE_MASK = 0xf << 12,
3017 SLI4_PARAM_SLI_HINT1_MASK = 0xff << 16,
3018 SLI4_PARAM_SLI_HINT2_MASK = 0x1f << 24,
3020 SLI4_PARAM_EQ_PAGE_CNT_MASK = 0xf << 0,
3021 SLI4_PARAM_EQE_SZS_MASK = 0xf << 8,
3022 SLI4_PARAM_EQ_PAGE_SZS_MASK = 0xff << 16,
3024 SLI4_PARAM_CQ_PAGE_CNT_MASK = 0xf << 0,
3025 SLI4_PARAM_CQE_SZS_MASK = 0xf << 8,
3026 SLI4_PARAM_CQ_PAGE_SZS_MASK = 0xff << 16,
3028 SLI4_PARAM_MQ_PAGE_CNT_MASK = 0xf << 0,
3029 SLI4_PARAM_MQ_PAGE_SZS_MASK = 0xff << 16,
3031 SLI4_PARAM_WQ_PAGE_CNT_MASK = 0xf << 0,
3032 SLI4_PARAM_WQE_SZS_MASK = 0xf << 8,
3033 SLI4_PARAM_WQ_PAGE_SZS_MASK = 0xff << 16,
3035 SLI4_PARAM_RQ_PAGE_CNT_MASK = 0xf << 0,
3036 SLI4_PARAM_RQE_SZS_MASK = 0xf << 8,
3037 SLI4_PARAM_RQ_PAGE_SZS_MASK = 0xff << 16,
3039 SLI4_PARAM_RQ_DB_WINDOW_MASK = 0xf000,
3041 SLI4_PARAM_FC = 1 << 0,
3068 SLI4_PARAM_LOOPBACK_MASK = 0xf << 28,
3070 SLI4_PARAM_SGL_PAGE_CNT_MASK = 0xf << 0,
3071 SLI4_PARAM_SGL_PAGE_SZS_MASK = 0xff << 8,
3072 SLI4_PARAM_SGL_PP_ALIGN_MASK = 0xff << 16,
3119 SLI4_PORT_TYPE_ETH = 0,
3147 * by the SFF-8472 specification).
3163 #define SLI4_REQ_DESIRE_READLEN 0xffffff
3174 #define RSP_COM_READ_OBJ_EOF 0x80000000
3183 SLI4_RQ_DES_WRITE_LEN = 0xffffff,
3184 SLI4_RQ_DES_WRITE_LEN_NOC = 0x40000000,
3185 SLI4_RQ_DES_WRITE_LEN_EOF = 0x80000000,
3197 #define RSP_CHANGE_STATUS 0xff
3212 #define SLI4_RQ_OBJ_LIST_READ_LEN 0xffffff
3224 SLI4_CMN_SET_DUMP_BUFFER_LEN = 0xffffff,
3225 SLI4_CMN_SET_DUMP_FDB = 0x20000000,
3226 SLI4_CMN_SET_DUMP_BLP = 0x40000000,
3227 SLI4_CMN_SET_DUMP_QRY = 0x80000000,
3259 SLI4_DUMP_READY_STATUS_FAILED = -1,
3263 SLI4_SET_FEATURES_DIF_SEED = 0x01,
3264 SLI4_SET_FEATURES_XRI_TIMER = 0x03,
3265 SLI4_SET_FEATURES_MAX_PCIE_SPEED = 0x04,
3266 SLI4_SET_FEATURES_FCTL_CHECK = 0x05,
3267 SLI4_SET_FEATURES_FEC = 0x06,
3268 SLI4_SET_FEATURES_PCIE_RECV_DETECT = 0x07,
3269 SLI4_SET_FEATURES_DIF_MEMORY_MODE = 0x08,
3270 SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE = 0x09,
3271 SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS = 0x0a,
3272 SLI4_SET_FEAT_CFG_AUTO_XFER_RDY_T10PI = 0x0c,
3273 SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE = 0x0d,
3274 SLI4_SET_FEATURES_SET_FTD_XFER_HINT = 0x0f,
3275 SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK = 0x11,
3291 SLI4_RQ_MULTIRQ_ISR = 0x1,
3292 SLI4_RQ_MULTIRQ_AUTOGEN_XFER_RDY = 0x2,
3294 SLI4_RQ_MULTIRQ_NUM_RQS = 0xff,
3295 SLI4_RQ_MULTIRQ_RQ_SELECT = 0xf00,
3304 SLI4_RQ_HEALTH_CHECK_ENABLE = 0x1,
3305 SLI4_RQ_HEALTH_CHECK_QUERY = 0x2,
3338 #define SLI4_PROTOCOL_FC 0x10
3339 #define SLI4_PROTOCOL_DEFAULT 0xff
3349 SLI4_PCIE_DESC_IMM = 0x4000,
3350 SLI4_PCIE_DESC_NOSV = 0x8000,
3352 SLI4_PCIE_DESC_PF_NO = 0x3ff0000,
3354 SLI4_PCIE_DESC_MISSN_ROLE = 0xff,
3355 SLI4_PCIE_DESC_PCHG = 0x8000000,
3356 SLI4_PCIE_DESC_SCHG = 0x10000000,
3357 SLI4_PCIE_DESC_XCHG = 0x20000000,
3358 SLI4_PCIE_DESC_XROM = 0xc0000000
3412 SLI4_SET_RECONFIG_LINKID_NEXT = 0xff,
3438 SLI4_OPC_WQ_CREATE = 0x1,
3439 SLI4_OPC_WQ_DESTROY = 0x2,
3440 SLI4_OPC_POST_SGL_PAGES = 0x3,
3441 SLI4_OPC_RQ_CREATE = 0x5,
3442 SLI4_OPC_RQ_DESTROY = 0x6,
3443 SLI4_OPC_READ_FCF_TABLE = 0x8,
3444 SLI4_OPC_POST_HDR_TEMPLATES = 0xb,
3445 SLI4_OPC_REDISCOVER_FCF = 0x10,
3449 #define SLI4_CQ_DEFAULT 0xffff
3484 SLI4_IO_CONTINUATION = 1 << 0,
3713 /* Save pointer to physical memory descriptor for non-embedded
3724 hdr->opcode = opc; in sli_cmd_fill_hdr()
3725 hdr->subsystem = sub; in sli_cmd_fill_hdr()
3726 hdr->dw3_version = cpu_to_le32(ver); in sli_cmd_fill_hdr()
3727 hdr->request_length = len; in sli_cmd_fill_hdr()
3737 return sli4->sge_supported_length; in sli_get_max_sge()
3743 if (sli4->sgl_page_sizes != 1) { in sli_get_max_sgl()
3745 sli4->sgl_page_sizes); in sli_get_max_sgl()
3746 return 0; in sli_get_max_sgl()
3749 return (sli4->max_sgl_pages * SLI_PAGE_SIZE) / sizeof(struct sli4_sge); in sli_get_max_sgl()
3755 switch (sli4->topology) { in sli_get_medium()
3768 return sli4->link_module_type; in sli_get_lmt()
3774 int rc = 0; in sli_set_topology()
3780 sli4->topology = value; in sli_set_topology()
3784 rc = -1; in sli_set_topology()
3793 u32 count = 0; in sli_convert_mask_to_count()
3796 count = 1 << (31 - __builtin_clz(mask)); in sli_convert_mask_to_count()
3808 return readl(sli->reg[0] + SLI4_PORT_STATUS_REGOFF); in sli_reg_read_status()
3814 return (sli_reg_read_status(sli4) & SLI4_PORT_STATUS_ERR) ? 1 : 0; in sli_fw_error_status()
3820 return readl(sli->reg[0] + SLI4_PORT_ERROR1); in sli_reg_read_err1()
3826 return readl(sli->reg[0] + SLI4_PORT_ERROR2); in sli_reg_read_err2()
3835 *len_hdr = *len_data = 0; in sli_fc_rqe_length()
3837 if (rcqe->status == SLI4_FC_ASYNC_RQ_SUCCESS) { in sli_fc_rqe_length()
3838 *len_hdr = rcqe->hdpl_byte & SLI4_RACQE_HDPL; in sli_fc_rqe_length()
3839 *len_data = le16_to_cpu(rcqe->data_placement_length); in sli_fc_rqe_length()
3840 return 0; in sli_fc_rqe_length()
3842 return -1; in sli_fc_rqe_length()
3856 fcfi = le16_to_cpu(rcqe->fcfi_rq_id_word) & SLI4_RACQE_FCFI; in sli_fc_rqe_fcfi()
3862 fcfi = rcqev1->fcfi_byte & SLI4_RACQE_FCFI; in sli_fc_rqe_fcfi()
3868 fcfi = opt_wr->flags0 & SLI4_OCQE_FCFI; in sli_fc_rqe_fcfi()