50 #define DC_HPDx_CONTROL(x)        (DC_HPD1_CONTROL     + (x * 0xc))
51 #define DC_HPDx_INT_CONTROL(x)    (DC_HPD1_INT_CONTROL + (x * 0xc))
52 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS  + (x * 0xc))
62 	spin_lock_irqsave(&rdev->cg_idx_lock, flags);  in eg_cg_rreg()
63 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_rreg()
65 	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);  in eg_cg_rreg()
73 	spin_lock_irqsave(&rdev->cg_idx_lock, flags);  in eg_cg_wreg()
74 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_wreg()
76 	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);  in eg_cg_wreg()
84 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_rreg()
85 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_rreg()
87 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_rreg()
95 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_wreg()
96 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_wreg()
98 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_wreg()
106 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_rreg()
107 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_rreg()
109 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_rreg()
117 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_wreg()
118 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_wreg()
120 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_wreg()
137 	0x98fc,
138 	0x9830,
139 	0x9834,
140 	0x9838,
141 	0x9870,
142 	0x9874,
143 	0x8a14,
144 	0x8b24,
145 	0x8bcc,
146 	0x8b10,
147 	0x8d00,
148 	0x8d04,
149 	0x8c00,
150 	0x8c04,
151 	0x8c08,
152 	0x8c0c,
153 	0x8d8c,
154 	0x8c20,
155 	0x8c24,
156 	0x8c28,
157 	0x8c18,
158 	0x8c1c,
159 	0x8cf0,
160 	0x8e2c,
161 	0x8e38,
162 	0x8c30,
163 	0x9508,
164 	0x9688,
165 	0x9608,
166 	0x960c,
167 	0x9610,
168 	0x9614,
169 	0x88c4,
170 	0x88d4,
171 	0xa008,
172 	0x900c,
173 	0x9100,
174 	0x913c,
175 	0x98f8,
176 	0x98f4,
177 	0x9b7c,
178 	0x3f8c,
179 	0x8950,
180 	0x8954,
181 	0x8a18,
182 	0x8b28,
183 	0x9144,
184 	0x9148,
185 	0x914c,
186 	0x3f90,
187 	0x3f94,
188 	0x915c,
189 	0x9160,
190 	0x9178,
191 	0x917c,
192 	0x9180,
193 	0x918c,
194 	0x9190,
195 	0x9194,
196 	0x9198,
197 	0x919c,
198 	0x91a8,
199 	0x91ac,
200 	0x91b0,
201 	0x91b4,
202 	0x91b8,
203 	0x91c4,
204 	0x91c8,
205 	0x91cc,
206 	0x91d0,
207 	0x91d4,
208 	0x91e0,
209 	0x91e4,
210 	0x91ec,
211 	0x91f0,
212 	0x91f4,
213 	0x9200,
214 	0x9204,
215 	0x929c,
216 	0x9150,
217 	0x802c,
227 	0x3f90, 0xffff0000, 0xff000000,
228 	0x9148, 0xffff0000, 0xff000000,
229 	0x3f94, 0xffff0000, 0xff000000,
230 	0x914c, 0xffff0000, 0xff000000,
231 	0x9b7c, 0xffffffff, 0x00000000,
232 	0x8a14, 0xffffffff, 0x00000007,
233 	0x8b10, 0xffffffff, 0x00000000,
234 	0x960c, 0xffffffff, 0x54763210,
235 	0x88c4, 0xffffffff, 0x000000c2,
236 	0x88d4, 0xffffffff, 0x00000010,
237 	0x8974, 0xffffffff, 0x00000000,
238 	0xc78, 0x00000080, 0x00000080,
239 	0x5eb4, 0xffffffff, 0x00000002,
240 	0x5e78, 0xffffffff, 0x001000f0,
241 	0x6104, 0x01000300, 0x00000000,
242 	0x5bc0, 0x00300000, 0x00000000,
243 	0x7030, 0xffffffff, 0x00000011,
244 	0x7c30, 0xffffffff, 0x00000011,
245 	0x10830, 0xffffffff, 0x00000011,
246 	0x11430, 0xffffffff, 0x00000011,
247 	0x12030, 0xffffffff, 0x00000011,
248 	0x12c30, 0xffffffff, 0x00000011,
249 	0xd02c, 0xffffffff, 0x08421000,
250 	0x240c, 0xffffffff, 0x00000380,
251 	0x8b24, 0xffffffff, 0x00ff0fff,
252 	0x28a4c, 0x06000000, 0x06000000,
253 	0x10c, 0x00000001, 0x00000001,
254 	0x8d00, 0xffffffff, 0x100e4848,
255 	0x8d04, 0xffffffff, 0x00164745,
256 	0x8c00, 0xffffffff, 0xe4000003,
257 	0x8c04, 0xffffffff, 0x40600060,
258 	0x8c08, 0xffffffff, 0x001c001c,
259 	0x8cf0, 0xffffffff, 0x08e00620,
260 	0x8c20, 0xffffffff, 0x00800080,
261 	0x8c24, 0xffffffff, 0x00800080,
262 	0x8c18, 0xffffffff, 0x20202078,
263 	0x8c1c, 0xffffffff, 0x00001010,
264 	0x28350, 0xffffffff, 0x00000000,
265 	0xa008, 0xffffffff, 0x00010000,
266 	0x5c4, 0xffffffff, 0x00000001,
267 	0x9508, 0xffffffff, 0x00000002,
268 	0x913c, 0x0000000f, 0x0000000a
273 	0x2f4c, 0xffffffff, 0x00000000,
274 	0x54f4, 0xffffffff, 0x00000000,
275 	0x54f0, 0xffffffff, 0x00000000,
276 	0x5498, 0xffffffff, 0x00000000,
277 	0x549c, 0xffffffff, 0x00000000,
278 	0x5494, 0xffffffff, 0x00000000,
279 	0x53cc, 0xffffffff, 0x00000000,
280 	0x53c8, 0xffffffff, 0x00000000,
281 	0x53c4, 0xffffffff, 0x00000000,
282 	0x53c0, 0xffffffff, 0x00000000,
283 	0x53bc, 0xffffffff, 0x00000000,
284 	0x53b8, 0xffffffff, 0x00000000,
285 	0x53b4, 0xffffffff, 0x00000000,
286 	0x53b0, 0xffffffff, 0x00000000
291 	0x802c, 0xffffffff, 0xc0000000,
292 	0x5448, 0xffffffff, 0x00000100,
293 	0x55e4, 0xffffffff, 0x00000100,
294 	0x160c, 0xffffffff, 0x00000100,
295 	0x5644, 0xffffffff, 0x00000100,
296 	0xc164, 0xffffffff, 0x00000100,
297 	0x8a18, 0xffffffff, 0x00000100,
298 	0x897c, 0xffffffff, 0x06000100,
299 	0x8b28, 0xffffffff, 0x00000100,
300 	0x9144, 0xffffffff, 0x00000100,
301 	0x9a60, 0xffffffff, 0x00000100,
302 	0x9868, 0xffffffff, 0x00000100,
303 	0x8d58, 0xffffffff, 0x00000100,
304 	0x9510, 0xffffffff, 0x00000100,
305 	0x949c, 0xffffffff, 0x00000100,
306 	0x9654, 0xffffffff, 0x00000100,
307 	0x9030, 0xffffffff, 0x00000100,
308 	0x9034, 0xffffffff, 0x00000100,
309 	0x9038, 0xffffffff, 0x00000100,
310 	0x903c, 0xffffffff, 0x00000100,
311 	0x9040, 0xffffffff, 0x00000100,
312 	0xa200, 0xffffffff, 0x00000100,
313 	0xa204, 0xffffffff, 0x00000100,
314 	0xa208, 0xffffffff, 0x00000100,
315 	0xa20c, 0xffffffff, 0x00000100,
316 	0x971c, 0xffffffff, 0x00000100,
317 	0x977c, 0xffffffff, 0x00000100,
318 	0x3f80, 0xffffffff, 0x00000100,
319 	0xa210, 0xffffffff, 0x00000100,
320 	0xa214, 0xffffffff, 0x00000100,
321 	0x4d8, 0xffffffff, 0x00000100,
322 	0x9784, 0xffffffff, 0x00000100,
323 	0x9698, 0xffffffff, 0x00000100,
324 	0x4d4, 0xffffffff, 0x00000200,
325 	0x30cc, 0xffffffff, 0x00000100,
326 	0xd0c0, 0xffffffff, 0xff000100,
327 	0x802c, 0xffffffff, 0x40000000,
328 	0x915c, 0xffffffff, 0x00010000,
329 	0x9160, 0xffffffff, 0x00030002,
330 	0x9178, 0xffffffff, 0x00070000,
331 	0x917c, 0xffffffff, 0x00030002,
332 	0x9180, 0xffffffff, 0x00050004,
333 	0x918c, 0xffffffff, 0x00010006,
334 	0x9190, 0xffffffff, 0x00090008,
335 	0x9194, 0xffffffff, 0x00070000,
336 	0x9198, 0xffffffff, 0x00030002,
337 	0x919c, 0xffffffff, 0x00050004,
338 	0x91a8, 0xffffffff, 0x00010006,
339 	0x91ac, 0xffffffff, 0x00090008,
340 	0x91b0, 0xffffffff, 0x00070000,
341 	0x91b4, 0xffffffff, 0x00030002,
342 	0x91b8, 0xffffffff, 0x00050004,
343 	0x91c4, 0xffffffff, 0x00010006,
344 	0x91c8, 0xffffffff, 0x00090008,
345 	0x91cc, 0xffffffff, 0x00070000,
346 	0x91d0, 0xffffffff, 0x00030002,
347 	0x91d4, 0xffffffff, 0x00050004,
348 	0x91e0, 0xffffffff, 0x00010006,
349 	0x91e4, 0xffffffff, 0x00090008,
350 	0x91e8, 0xffffffff, 0x00000000,
351 	0x91ec, 0xffffffff, 0x00070000,
352 	0x91f0, 0xffffffff, 0x00030002,
353 	0x91f4, 0xffffffff, 0x00050004,
354 	0x9200, 0xffffffff, 0x00010006,
355 	0x9204, 0xffffffff, 0x00090008,
356 	0x9208, 0xffffffff, 0x00070000,
357 	0x920c, 0xffffffff, 0x00030002,
358 	0x9210, 0xffffffff, 0x00050004,
359 	0x921c, 0xffffffff, 0x00010006,
360 	0x9220, 0xffffffff, 0x00090008,
361 	0x9224, 0xffffffff, 0x00070000,
362 	0x9228, 0xffffffff, 0x00030002,
363 	0x922c, 0xffffffff, 0x00050004,
364 	0x9238, 0xffffffff, 0x00010006,
365 	0x923c, 0xffffffff, 0x00090008,
366 	0x9240, 0xffffffff, 0x00070000,
367 	0x9244, 0xffffffff, 0x00030002,
368 	0x9248, 0xffffffff, 0x00050004,
369 	0x9254, 0xffffffff, 0x00010006,
370 	0x9258, 0xffffffff, 0x00090008,
371 	0x925c, 0xffffffff, 0x00070000,
372 	0x9260, 0xffffffff, 0x00030002,
373 	0x9264, 0xffffffff, 0x00050004,
374 	0x9270, 0xffffffff, 0x00010006,
375 	0x9274, 0xffffffff, 0x00090008,
376 	0x9278, 0xffffffff, 0x00070000,
377 	0x927c, 0xffffffff, 0x00030002,
378 	0x9280, 0xffffffff, 0x00050004,
379 	0x928c, 0xffffffff, 0x00010006,
380 	0x9290, 0xffffffff, 0x00090008,
381 	0x9294, 0xffffffff, 0x00000000,
382 	0x929c, 0xffffffff, 0x00000001,
383 	0x802c, 0xffffffff, 0x40010000,
384 	0x915c, 0xffffffff, 0x00010000,
385 	0x9160, 0xffffffff, 0x00030002,
386 	0x9178, 0xffffffff, 0x00070000,
387 	0x917c, 0xffffffff, 0x00030002,
388 	0x9180, 0xffffffff, 0x00050004,
389 	0x918c, 0xffffffff, 0x00010006,
390 	0x9190, 0xffffffff, 0x00090008,
391 	0x9194, 0xffffffff, 0x00070000,
392 	0x9198, 0xffffffff, 0x00030002,
393 	0x919c, 0xffffffff, 0x00050004,
394 	0x91a8, 0xffffffff, 0x00010006,
395 	0x91ac, 0xffffffff, 0x00090008,
396 	0x91b0, 0xffffffff, 0x00070000,
397 	0x91b4, 0xffffffff, 0x00030002,
398 	0x91b8, 0xffffffff, 0x00050004,
399 	0x91c4, 0xffffffff, 0x00010006,
400 	0x91c8, 0xffffffff, 0x00090008,
401 	0x91cc, 0xffffffff, 0x00070000,
402 	0x91d0, 0xffffffff, 0x00030002,
403 	0x91d4, 0xffffffff, 0x00050004,
404 	0x91e0, 0xffffffff, 0x00010006,
405 	0x91e4, 0xffffffff, 0x00090008,
406 	0x91e8, 0xffffffff, 0x00000000,
407 	0x91ec, 0xffffffff, 0x00070000,
408 	0x91f0, 0xffffffff, 0x00030002,
409 	0x91f4, 0xffffffff, 0x00050004,
410 	0x9200, 0xffffffff, 0x00010006,
411 	0x9204, 0xffffffff, 0x00090008,
412 	0x9208, 0xffffffff, 0x00070000,
413 	0x920c, 0xffffffff, 0x00030002,
414 	0x9210, 0xffffffff, 0x00050004,
415 	0x921c, 0xffffffff, 0x00010006,
416 	0x9220, 0xffffffff, 0x00090008,
417 	0x9224, 0xffffffff, 0x00070000,
418 	0x9228, 0xffffffff, 0x00030002,
419 	0x922c, 0xffffffff, 0x00050004,
420 	0x9238, 0xffffffff, 0x00010006,
421 	0x923c, 0xffffffff, 0x00090008,
422 	0x9240, 0xffffffff, 0x00070000,
423 	0x9244, 0xffffffff, 0x00030002,
424 	0x9248, 0xffffffff, 0x00050004,
425 	0x9254, 0xffffffff, 0x00010006,
426 	0x9258, 0xffffffff, 0x00090008,
427 	0x925c, 0xffffffff, 0x00070000,
428 	0x9260, 0xffffffff, 0x00030002,
429 	0x9264, 0xffffffff, 0x00050004,
430 	0x9270, 0xffffffff, 0x00010006,
431 	0x9274, 0xffffffff, 0x00090008,
432 	0x9278, 0xffffffff, 0x00070000,
433 	0x927c, 0xffffffff, 0x00030002,
434 	0x9280, 0xffffffff, 0x00050004,
435 	0x928c, 0xffffffff, 0x00010006,
436 	0x9290, 0xffffffff, 0x00090008,
437 	0x9294, 0xffffffff, 0x00000000,
438 	0x929c, 0xffffffff, 0x00000001,
439 	0x802c, 0xffffffff, 0xc0000000
444 	0x802c, 0xffffffff, 0xc0000000,
445 	0x5448, 0xffffffff, 0x00000100,
446 	0x55e4, 0xffffffff, 0x00000100,
447 	0x160c, 0xffffffff, 0x00000100,
448 	0x5644, 0xffffffff, 0x00000100,
449 	0xc164, 0xffffffff, 0x00000100,
450 	0x8a18, 0xffffffff, 0x00000100,
451 	0x897c, 0xffffffff, 0x06000100,
452 	0x8b28, 0xffffffff, 0x00000100,
453 	0x9144, 0xffffffff, 0x00000100,
454 	0x9a60, 0xffffffff, 0x00000100,
455 	0x9868, 0xffffffff, 0x00000100,
456 	0x8d58, 0xffffffff, 0x00000100,
457 	0x9510, 0xffffffff, 0x00000100,
458 	0x949c, 0xffffffff, 0x00000100,
459 	0x9654, 0xffffffff, 0x00000100,
460 	0x9030, 0xffffffff, 0x00000100,
461 	0x9034, 0xffffffff, 0x00000100,
462 	0x9038, 0xffffffff, 0x00000100,
463 	0x903c, 0xffffffff, 0x00000100,
464 	0x9040, 0xffffffff, 0x00000100,
465 	0xa200, 0xffffffff, 0x00000100,
466 	0xa204, 0xffffffff, 0x00000100,
467 	0xa208, 0xffffffff, 0x00000100,
468 	0xa20c, 0xffffffff, 0x00000100,
469 	0x971c, 0xffffffff, 0x00000100,
470 	0x977c, 0xffffffff, 0x00000100,
471 	0x3f80, 0xffffffff, 0x00000100,
472 	0xa210, 0xffffffff, 0x00000100,
473 	0xa214, 0xffffffff, 0x00000100,
474 	0x4d8, 0xffffffff, 0x00000100,
475 	0x9784, 0xffffffff, 0x00000100,
476 	0x9698, 0xffffffff, 0x00000100,
477 	0x4d4, 0xffffffff, 0x00000200,
478 	0x30cc, 0xffffffff, 0x00000100,
479 	0xd0c0, 0xffffffff, 0xff000100,
480 	0x802c, 0xffffffff, 0x40000000,
481 	0x915c, 0xffffffff, 0x00010000,
482 	0x9160, 0xffffffff, 0x00030002,
483 	0x9178, 0xffffffff, 0x00070000,
484 	0x917c, 0xffffffff, 0x00030002,
485 	0x9180, 0xffffffff, 0x00050004,
486 	0x918c, 0xffffffff, 0x00010006,
487 	0x9190, 0xffffffff, 0x00090008,
488 	0x9194, 0xffffffff, 0x00070000,
489 	0x9198, 0xffffffff, 0x00030002,
490 	0x919c, 0xffffffff, 0x00050004,
491 	0x91a8, 0xffffffff, 0x00010006,
492 	0x91ac, 0xffffffff, 0x00090008,
493 	0x91b0, 0xffffffff, 0x00070000,
494 	0x91b4, 0xffffffff, 0x00030002,
495 	0x91b8, 0xffffffff, 0x00050004,
496 	0x91c4, 0xffffffff, 0x00010006,
497 	0x91c8, 0xffffffff, 0x00090008,
498 	0x91cc, 0xffffffff, 0x00070000,
499 	0x91d0, 0xffffffff, 0x00030002,
500 	0x91d4, 0xffffffff, 0x00050004,
501 	0x91e0, 0xffffffff, 0x00010006,
502 	0x91e4, 0xffffffff, 0x00090008,
503 	0x91e8, 0xffffffff, 0x00000000,
504 	0x91ec, 0xffffffff, 0x00070000,
505 	0x91f0, 0xffffffff, 0x00030002,
506 	0x91f4, 0xffffffff, 0x00050004,
507 	0x9200, 0xffffffff, 0x00010006,
508 	0x9204, 0xffffffff, 0x00090008,
509 	0x9294, 0xffffffff, 0x00000000,
510 	0x929c, 0xffffffff, 0x00000001,
511 	0x802c, 0xffffffff, 0xc0000000
516 	0x3f90, 0xffff0000, 0xff000000,
517 	0x9148, 0xffff0000, 0xff000000,
518 	0x3f94, 0xffff0000, 0xff000000,
519 	0x914c, 0xffff0000, 0xff000000,
520 	0x9b7c, 0xffffffff, 0x00000000,
521 	0x8a14, 0xffffffff, 0x00000007,
522 	0x8b10, 0xffffffff, 0x00000000,
523 	0x960c, 0xffffffff, 0x54763210,
524 	0x88c4, 0xffffffff, 0x000000c2,
525 	0x88d4, 0xffffffff, 0x00000000,
526 	0x8974, 0xffffffff, 0x00000000,
527 	0xc78, 0x00000080, 0x00000080,
528 	0x5eb4, 0xffffffff, 0x00000002,
529 	0x5e78, 0xffffffff, 0x001000f0,
530 	0x6104, 0x01000300, 0x00000000,
531 	0x5bc0, 0x00300000, 0x00000000,
532 	0x7030, 0xffffffff, 0x00000011,
533 	0x7c30, 0xffffffff, 0x00000011,
534 	0x10830, 0xffffffff, 0x00000011,
535 	0x11430, 0xffffffff, 0x00000011,
536 	0xd02c, 0xffffffff, 0x08421000,
537 	0x240c, 0xffffffff, 0x00000380,
538 	0x8b24, 0xffffffff, 0x00ff0fff,
539 	0x28a4c, 0x06000000, 0x06000000,
540 	0x10c, 0x00000001, 0x00000001,
541 	0x8d00, 0xffffffff, 0x100e4848,
542 	0x8d04, 0xffffffff, 0x00164745,
543 	0x8c00, 0xffffffff, 0xe4000003,
544 	0x8c04, 0xffffffff, 0x40600060,
545 	0x8c08, 0xffffffff, 0x001c001c,
546 	0x8cf0, 0xffffffff, 0x08e00410,
547 	0x8c20, 0xffffffff, 0x00800080,
548 	0x8c24, 0xffffffff, 0x00800080,
549 	0x8c18, 0xffffffff, 0x20202078,
550 	0x8c1c, 0xffffffff, 0x00001010,
551 	0x28350, 0xffffffff, 0x00000000,
552 	0xa008, 0xffffffff, 0x00010000,
553 	0x5c4, 0xffffffff, 0x00000001,
554 	0x9508, 0xffffffff, 0x00000002
559 	0x802c, 0xffffffff, 0xc0000000,
560 	0x5448, 0xffffffff, 0x00000100,
561 	0x55e4, 0xffffffff, 0x00000100,
562 	0x160c, 0xffffffff, 0x00000100,
563 	0x5644, 0xffffffff, 0x00000100,
564 	0xc164, 0xffffffff, 0x00000100,
565 	0x8a18, 0xffffffff, 0x00000100,
566 	0x897c, 0xffffffff, 0x06000100,
567 	0x8b28, 0xffffffff, 0x00000100,
568 	0x9144, 0xffffffff, 0x00000100,
569 	0x9a60, 0xffffffff, 0x00000100,
570 	0x9868, 0xffffffff, 0x00000100,
571 	0x8d58, 0xffffffff, 0x00000100,
572 	0x9510, 0xffffffff, 0x00000100,
573 	0x949c, 0xffffffff, 0x00000100,
574 	0x9654, 0xffffffff, 0x00000100,
575 	0x9030, 0xffffffff, 0x00000100,
576 	0x9034, 0xffffffff, 0x00000100,
577 	0x9038, 0xffffffff, 0x00000100,
578 	0x903c, 0xffffffff, 0x00000100,
579 	0x9040, 0xffffffff, 0x00000100,
580 	0xa200, 0xffffffff, 0x00000100,
581 	0xa204, 0xffffffff, 0x00000100,
582 	0xa208, 0xffffffff, 0x00000100,
583 	0xa20c, 0xffffffff, 0x00000100,
584 	0x971c, 0xffffffff, 0x00000100,
585 	0x977c, 0xffffffff, 0x00000100,
586 	0x3f80, 0xffffffff, 0x00000100,
587 	0xa210, 0xffffffff, 0x00000100,
588 	0xa214, 0xffffffff, 0x00000100,
589 	0x4d8, 0xffffffff, 0x00000100,
590 	0x9784, 0xffffffff, 0x00000100,
591 	0x9698, 0xffffffff, 0x00000100,
592 	0x4d4, 0xffffffff, 0x00000200,
593 	0x30cc, 0xffffffff, 0x00000100,
594 	0xd0c0, 0xffffffff, 0xff000100,
595 	0x802c, 0xffffffff, 0x40000000,
596 	0x915c, 0xffffffff, 0x00010000,
597 	0x9178, 0xffffffff, 0x00050000,
598 	0x917c, 0xffffffff, 0x00030002,
599 	0x918c, 0xffffffff, 0x00010004,
600 	0x9190, 0xffffffff, 0x00070006,
601 	0x9194, 0xffffffff, 0x00050000,
602 	0x9198, 0xffffffff, 0x00030002,
603 	0x91a8, 0xffffffff, 0x00010004,
604 	0x91ac, 0xffffffff, 0x00070006,
605 	0x91e8, 0xffffffff, 0x00000000,
606 	0x9294, 0xffffffff, 0x00000000,
607 	0x929c, 0xffffffff, 0x00000001,
608 	0x802c, 0xffffffff, 0xc0000000
613 	0x802c, 0xffffffff, 0xc0000000,
614 	0x5448, 0xffffffff, 0x00000100,
615 	0x55e4, 0xffffffff, 0x00000100,
616 	0x160c, 0xffffffff, 0x00000100,
617 	0x5644, 0xffffffff, 0x00000100,
618 	0xc164, 0xffffffff, 0x00000100,
619 	0x8a18, 0xffffffff, 0x00000100,
620 	0x897c, 0xffffffff, 0x06000100,
621 	0x8b28, 0xffffffff, 0x00000100,
622 	0x9144, 0xffffffff, 0x00000100,
623 	0x9a60, 0xffffffff, 0x00000100,
624 	0x9868, 0xffffffff, 0x00000100,
625 	0x8d58, 0xffffffff, 0x00000100,
626 	0x9510, 0xffffffff, 0x00000100,
627 	0x949c, 0xffffffff, 0x00000100,
628 	0x9654, 0xffffffff, 0x00000100,
629 	0x9030, 0xffffffff, 0x00000100,
630 	0x9034, 0xffffffff, 0x00000100,
631 	0x9038, 0xffffffff, 0x00000100,
632 	0x903c, 0xffffffff, 0x00000100,
633 	0x9040, 0xffffffff, 0x00000100,
634 	0xa200, 0xffffffff, 0x00000100,
635 	0xa204, 0xffffffff, 0x00000100,
636 	0xa208, 0xffffffff, 0x00000100,
637 	0xa20c, 0xffffffff, 0x00000100,
638 	0x971c, 0xffffffff, 0x00000100,
639 	0xd0c0, 0xffffffff, 0xff000100,
640 	0x802c, 0xffffffff, 0x40000000,
641 	0x915c, 0xffffffff, 0x00010000,
642 	0x9160, 0xffffffff, 0x00030002,
643 	0x9178, 0xffffffff, 0x00070000,
644 	0x917c, 0xffffffff, 0x00030002,
645 	0x9180, 0xffffffff, 0x00050004,
646 	0x918c, 0xffffffff, 0x00010006,
647 	0x9190, 0xffffffff, 0x00090008,
648 	0x9194, 0xffffffff, 0x00070000,
649 	0x9198, 0xffffffff, 0x00030002,
650 	0x919c, 0xffffffff, 0x00050004,
651 	0x91a8, 0xffffffff, 0x00010006,
652 	0x91ac, 0xffffffff, 0x00090008,
653 	0x91b0, 0xffffffff, 0x00070000,
654 	0x91b4, 0xffffffff, 0x00030002,
655 	0x91b8, 0xffffffff, 0x00050004,
656 	0x91c4, 0xffffffff, 0x00010006,
657 	0x91c8, 0xffffffff, 0x00090008,
658 	0x91cc, 0xffffffff, 0x00070000,
659 	0x91d0, 0xffffffff, 0x00030002,
660 	0x91d4, 0xffffffff, 0x00050004,
661 	0x91e0, 0xffffffff, 0x00010006,
662 	0x91e4, 0xffffffff, 0x00090008,
663 	0x91e8, 0xffffffff, 0x00000000,
664 	0x91ec, 0xffffffff, 0x00070000,
665 	0x91f0, 0xffffffff, 0x00030002,
666 	0x91f4, 0xffffffff, 0x00050004,
667 	0x9200, 0xffffffff, 0x00010006,
668 	0x9204, 0xffffffff, 0x00090008,
669 	0x9208, 0xffffffff, 0x00070000,
670 	0x920c, 0xffffffff, 0x00030002,
671 	0x9210, 0xffffffff, 0x00050004,
672 	0x921c, 0xffffffff, 0x00010006,
673 	0x9220, 0xffffffff, 0x00090008,
674 	0x9224, 0xffffffff, 0x00070000,
675 	0x9228, 0xffffffff, 0x00030002,
676 	0x922c, 0xffffffff, 0x00050004,
677 	0x9238, 0xffffffff, 0x00010006,
678 	0x923c, 0xffffffff, 0x00090008,
679 	0x9240, 0xffffffff, 0x00070000,
680 	0x9244, 0xffffffff, 0x00030002,
681 	0x9248, 0xffffffff, 0x00050004,
682 	0x9254, 0xffffffff, 0x00010006,
683 	0x9258, 0xffffffff, 0x00090008,
684 	0x925c, 0xffffffff, 0x00070000,
685 	0x9260, 0xffffffff, 0x00030002,
686 	0x9264, 0xffffffff, 0x00050004,
687 	0x9270, 0xffffffff, 0x00010006,
688 	0x9274, 0xffffffff, 0x00090008,
689 	0x9278, 0xffffffff, 0x00070000,
690 	0x927c, 0xffffffff, 0x00030002,
691 	0x9280, 0xffffffff, 0x00050004,
692 	0x928c, 0xffffffff, 0x00010006,
693 	0x9290, 0xffffffff, 0x00090008,
694 	0x9294, 0xffffffff, 0x00000000,
695 	0x929c, 0xffffffff, 0x00000001,
696 	0x802c, 0xffffffff, 0xc0000000,
697 	0x977c, 0xffffffff, 0x00000100,
698 	0x3f80, 0xffffffff, 0x00000100,
699 	0xa210, 0xffffffff, 0x00000100,
700 	0xa214, 0xffffffff, 0x00000100,
701 	0x4d8, 0xffffffff, 0x00000100,
702 	0x9784, 0xffffffff, 0x00000100,
703 	0x9698, 0xffffffff, 0x00000100,
704 	0x4d4, 0xffffffff, 0x00000200,
705 	0x30cc, 0xffffffff, 0x00000100,
706 	0x802c, 0xffffffff, 0xc0000000
711 	0x5eb4, 0xffffffff, 0x00000002,
712 	0x5c4, 0xffffffff, 0x00000001,
713 	0x7030, 0xffffffff, 0x00000011,
714 	0x7c30, 0xffffffff, 0x00000011,
715 	0x6104, 0x01000300, 0x00000000,
716 	0x5bc0, 0x00300000, 0x00000000,
717 	0x8c04, 0xffffffff, 0x40600060,
718 	0x8c08, 0xffffffff, 0x001c001c,
719 	0x8c20, 0xffffffff, 0x00800080,
720 	0x8c24, 0xffffffff, 0x00800080,
721 	0x8c18, 0xffffffff, 0x20202078,
722 	0x8c1c, 0xffffffff, 0x00001010,
723 	0x918c, 0xffffffff, 0x00010006,
724 	0x91a8, 0xffffffff, 0x00010006,
725 	0x91c4, 0xffffffff, 0x00010006,
726 	0x91e0, 0xffffffff, 0x00010006,
727 	0x9200, 0xffffffff, 0x00010006,
728 	0x9150, 0xffffffff, 0x6e944040,
729 	0x917c, 0xffffffff, 0x00030002,
730 	0x9180, 0xffffffff, 0x00050004,
731 	0x9198, 0xffffffff, 0x00030002,
732 	0x919c, 0xffffffff, 0x00050004,
733 	0x91b4, 0xffffffff, 0x00030002,
734 	0x91b8, 0xffffffff, 0x00050004,
735 	0x91d0, 0xffffffff, 0x00030002,
736 	0x91d4, 0xffffffff, 0x00050004,
737 	0x91f0, 0xffffffff, 0x00030002,
738 	0x91f4, 0xffffffff, 0x00050004,
739 	0x915c, 0xffffffff, 0x00010000,
740 	0x9160, 0xffffffff, 0x00030002,
741 	0x3f90, 0xffff0000, 0xff000000,
742 	0x9178, 0xffffffff, 0x00070000,
743 	0x9194, 0xffffffff, 0x00070000,
744 	0x91b0, 0xffffffff, 0x00070000,
745 	0x91cc, 0xffffffff, 0x00070000,
746 	0x91ec, 0xffffffff, 0x00070000,
747 	0x9148, 0xffff0000, 0xff000000,
748 	0x9190, 0xffffffff, 0x00090008,
749 	0x91ac, 0xffffffff, 0x00090008,
750 	0x91c8, 0xffffffff, 0x00090008,
751 	0x91e4, 0xffffffff, 0x00090008,
752 	0x9204, 0xffffffff, 0x00090008,
753 	0x3f94, 0xffff0000, 0xff000000,
754 	0x914c, 0xffff0000, 0xff000000,
755 	0x929c, 0xffffffff, 0x00000001,
756 	0x8a18, 0xffffffff, 0x00000100,
757 	0x8b28, 0xffffffff, 0x00000100,
758 	0x9144, 0xffffffff, 0x00000100,
759 	0x5644, 0xffffffff, 0x00000100,
760 	0x9b7c, 0xffffffff, 0x00000000,
761 	0x8030, 0xffffffff, 0x0000100a,
762 	0x8a14, 0xffffffff, 0x00000007,
763 	0x8b24, 0xffffffff, 0x00ff0fff,
764 	0x8b10, 0xffffffff, 0x00000000,
765 	0x28a4c, 0x06000000, 0x06000000,
766 	0x4d8, 0xffffffff, 0x00000100,
767 	0x913c, 0xffff000f, 0x0100000a,
768 	0x960c, 0xffffffff, 0x54763210,
769 	0x88c4, 0xffffffff, 0x000000c2,
770 	0x88d4, 0xffffffff, 0x00000010,
771 	0x8974, 0xffffffff, 0x00000000,
772 	0xc78, 0x00000080, 0x00000080,
773 	0x5e78, 0xffffffff, 0x001000f0,
774 	0xd02c, 0xffffffff, 0x08421000,
775 	0xa008, 0xffffffff, 0x00010000,
776 	0x8d00, 0xffffffff, 0x100e4848,
777 	0x8d04, 0xffffffff, 0x00164745,
778 	0x8c00, 0xffffffff, 0xe4000003,
779 	0x8cf0, 0x1fffffff, 0x08e00620,
780 	0x28350, 0xffffffff, 0x00000000,
781 	0x9508, 0xffffffff, 0x00000002
786 	0x900c, 0x00ffffff, 0x0017071f,
787 	0x8c18, 0xffffffff, 0x10101060,
788 	0x8c1c, 0xffffffff, 0x00001010,
789 	0x8c30, 0x0000000f, 0x00000005,
790 	0x9688, 0x0000000f, 0x00000007
795 	0x5eb4, 0xffffffff, 0x00000002,
796 	0x5c4, 0xffffffff, 0x00000001,
797 	0x7030, 0xffffffff, 0x00000011,
798 	0x7c30, 0xffffffff, 0x00000011,
799 	0x6104, 0x01000300, 0x00000000,
800 	0x5bc0, 0x00300000, 0x00000000,
801 	0x918c, 0xffffffff, 0x00010006,
802 	0x91a8, 0xffffffff, 0x00010006,
803 	0x9150, 0xffffffff, 0x6e944040,
804 	0x917c, 0xffffffff, 0x00030002,
805 	0x9198, 0xffffffff, 0x00030002,
806 	0x915c, 0xffffffff, 0x00010000,
807 	0x3f90, 0xffff0000, 0xff000000,
808 	0x9178, 0xffffffff, 0x00070000,
809 	0x9194, 0xffffffff, 0x00070000,
810 	0x9148, 0xffff0000, 0xff000000,
811 	0x9190, 0xffffffff, 0x00090008,
812 	0x91ac, 0xffffffff, 0x00090008,
813 	0x3f94, 0xffff0000, 0xff000000,
814 	0x914c, 0xffff0000, 0xff000000,
815 	0x929c, 0xffffffff, 0x00000001,
816 	0x8a18, 0xffffffff, 0x00000100,
817 	0x8b28, 0xffffffff, 0x00000100,
818 	0x9144, 0xffffffff, 0x00000100,
819 	0x9b7c, 0xffffffff, 0x00000000,
820 	0x8030, 0xffffffff, 0x0000100a,
821 	0x8a14, 0xffffffff, 0x00000001,
822 	0x8b24, 0xffffffff, 0x00ff0fff,
823 	0x8b10, 0xffffffff, 0x00000000,
824 	0x28a4c, 0x06000000, 0x06000000,
825 	0x4d8, 0xffffffff, 0x00000100,
826 	0x913c, 0xffff000f, 0x0100000a,
827 	0x960c, 0xffffffff, 0x54763210,
828 	0x88c4, 0xffffffff, 0x000000c2,
829 	0x88d4, 0xffffffff, 0x00000010,
830 	0x8974, 0xffffffff, 0x00000000,
831 	0xc78, 0x00000080, 0x00000080,
832 	0x5e78, 0xffffffff, 0x001000f0,
833 	0xd02c, 0xffffffff, 0x08421000,
834 	0xa008, 0xffffffff, 0x00010000,
835 	0x8d00, 0xffffffff, 0x100e4848,
836 	0x8d04, 0xffffffff, 0x00164745,
837 	0x8c00, 0xffffffff, 0xe4000003,
838 	0x8cf0, 0x1fffffff, 0x08e00410,
839 	0x28350, 0xffffffff, 0x00000000,
840 	0x9508, 0xffffffff, 0x00000002,
841 	0x900c, 0xffffffff, 0x0017071f,
842 	0x8c18, 0xffffffff, 0x10101060,
843 	0x8c1c, 0xffffffff, 0x00001010
848 	0x5eb4, 0xffffffff, 0x00000002,
849 	0x5e78, 0x8f311ff1, 0x001000f0,
850 	0x3f90, 0xffff0000, 0xff000000,
851 	0x9148, 0xffff0000, 0xff000000,
852 	0x3f94, 0xffff0000, 0xff000000,
853 	0x914c, 0xffff0000, 0xff000000,
854 	0xc78, 0x00000080, 0x00000080,
855 	0xbd4, 0x70073777, 0x00010001,
856 	0xd02c, 0xbfffff1f, 0x08421000,
857 	0xd0b8, 0x03773777, 0x02011003,
858 	0x5bc0, 0x00200000, 0x50100000,
859 	0x98f8, 0x33773777, 0x02011003,
860 	0x98fc, 0xffffffff, 0x76543210,
861 	0x7030, 0x31000311, 0x00000011,
862 	0x2f48, 0x00000007, 0x02011003,
863 	0x6b28, 0x00000010, 0x00000012,
864 	0x7728, 0x00000010, 0x00000012,
865 	0x10328, 0x00000010, 0x00000012,
866 	0x10f28, 0x00000010, 0x00000012,
867 	0x11b28, 0x00000010, 0x00000012,
868 	0x12728, 0x00000010, 0x00000012,
869 	0x240c, 0x000007ff, 0x00000380,
870 	0x8a14, 0xf000001f, 0x00000007,
871 	0x8b24, 0x3fff3fff, 0x00ff0fff,
872 	0x8b10, 0x0000ff0f, 0x00000000,
873 	0x28a4c, 0x07ffffff, 0x06000000,
874 	0x10c, 0x00000001, 0x00010003,
875 	0xa02c, 0xffffffff, 0x0000009b,
876 	0x913c, 0x0000000f, 0x0100000a,
877 	0x8d00, 0xffff7f7f, 0x100e4848,
878 	0x8d04, 0x00ffffff, 0x00164745,
879 	0x8c00, 0xfffc0003, 0xe4000003,
880 	0x8c04, 0xf8ff00ff, 0x40600060,
881 	0x8c08, 0x00ff00ff, 0x001c001c,
882 	0x8cf0, 0x1fff1fff, 0x08e00620,
883 	0x8c20, 0x0fff0fff, 0x00800080,
884 	0x8c24, 0x0fff0fff, 0x00800080,
885 	0x8c18, 0xffffffff, 0x20202078,
886 	0x8c1c, 0x0000ffff, 0x00001010,
887 	0x28350, 0x00000f01, 0x00000000,
888 	0x9508, 0x3700001f, 0x00000002,
889 	0x960c, 0xffffffff, 0x54763210,
890 	0x88c4, 0x001f3ae3, 0x000000c2,
891 	0x88d4, 0x0000001f, 0x00000010,
892 	0x8974, 0xffffffff, 0x00000000
897 	0x5eb4, 0xffffffff, 0x00000002,
898 	0x5e78, 0x8f311ff1, 0x001000f0,
899 	0x8c8, 0x00003000, 0x00001070,
900 	0x8cc, 0x000fffff, 0x00040035,
901 	0x3f90, 0xffff0000, 0xfff00000,
902 	0x9148, 0xffff0000, 0xfff00000,
903 	0x3f94, 0xffff0000, 0xfff00000,
904 	0x914c, 0xffff0000, 0xfff00000,
905 	0xc78, 0x00000080, 0x00000080,
906 	0xbd4, 0x00073007, 0x00010002,
907 	0xd02c, 0xbfffff1f, 0x08421000,
908 	0xd0b8, 0x03773777, 0x02010002,
909 	0x5bc0, 0x00200000, 0x50100000,
910 	0x98f8, 0x33773777, 0x00010002,
911 	0x98fc, 0xffffffff, 0x33221100,
912 	0x7030, 0x31000311, 0x00000011,
913 	0x2f48, 0x33773777, 0x00010002,
914 	0x6b28, 0x00000010, 0x00000012,
915 	0x7728, 0x00000010, 0x00000012,
916 	0x10328, 0x00000010, 0x00000012,
917 	0x10f28, 0x00000010, 0x00000012,
918 	0x11b28, 0x00000010, 0x00000012,
919 	0x12728, 0x00000010, 0x00000012,
920 	0x240c, 0x000007ff, 0x00000380,
921 	0x8a14, 0xf000001f, 0x00000007,
922 	0x8b24, 0x3fff3fff, 0x00ff0fff,
923 	0x8b10, 0x0000ff0f, 0x00000000,
924 	0x28a4c, 0x07ffffff, 0x06000000,
925 	0x10c, 0x00000001, 0x00010003,
926 	0xa02c, 0xffffffff, 0x0000009b,
927 	0x913c, 0x0000000f, 0x0100000a,
928 	0x8d00, 0xffff7f7f, 0x100e4848,
929 	0x8d04, 0x00ffffff, 0x00164745,
930 	0x8c00, 0xfffc0003, 0xe4000003,
931 	0x8c04, 0xf8ff00ff, 0x40600060,
932 	0x8c08, 0x00ff00ff, 0x001c001c,
933 	0x8cf0, 0x1fff1fff, 0x08e00410,
934 	0x8c20, 0x0fff0fff, 0x00800080,
935 	0x8c24, 0x0fff0fff, 0x00800080,
936 	0x8c18, 0xffffffff, 0x20202078,
937 	0x8c1c, 0x0000ffff, 0x00001010,
938 	0x28350, 0x00000f01, 0x00000000,
939 	0x9508, 0x3700001f, 0x00000002,
940 	0x960c, 0xffffffff, 0x54763210,
941 	0x88c4, 0x001f3ae3, 0x000000c2,
942 	0x88d4, 0x0000001f, 0x00000010,
943 	0x8974, 0xffffffff, 0x00000000
948 	0x5eb4, 0xffffffff, 0x00000002,
949 	0x5e78, 0x8f311ff1, 0x001000f0,
950 	0x8c8, 0x00003420, 0x00001450,
951 	0x8cc, 0x000fffff, 0x00040035,
952 	0x3f90, 0xffff0000, 0xfffc0000,
953 	0x9148, 0xffff0000, 0xfffc0000,
954 	0x3f94, 0xffff0000, 0xfffc0000,
955 	0x914c, 0xffff0000, 0xfffc0000,
956 	0xc78, 0x00000080, 0x00000080,
957 	0xbd4, 0x00073007, 0x00010001,
958 	0xd02c, 0xbfffff1f, 0x08421000,
959 	0xd0b8, 0x03773777, 0x02010001,
960 	0x5bc0, 0x00200000, 0x50100000,
961 	0x98f8, 0x33773777, 0x02010001,
962 	0x98fc, 0xffffffff, 0x33221100,
963 	0x7030, 0x31000311, 0x00000011,
964 	0x2f48, 0x33773777, 0x02010001,
965 	0x6b28, 0x00000010, 0x00000012,
966 	0x7728, 0x00000010, 0x00000012,
967 	0x10328, 0x00000010, 0x00000012,
968 	0x10f28, 0x00000010, 0x00000012,
969 	0x11b28, 0x00000010, 0x00000012,
970 	0x12728, 0x00000010, 0x00000012,
971 	0x240c, 0x000007ff, 0x00000380,
972 	0x8a14, 0xf000001f, 0x00000001,
973 	0x8b24, 0x3fff3fff, 0x00ff0fff,
974 	0x8b10, 0x0000ff0f, 0x00000000,
975 	0x28a4c, 0x07ffffff, 0x06000000,
976 	0x10c, 0x00000001, 0x00010003,
977 	0xa02c, 0xffffffff, 0x0000009b,
978 	0x913c, 0x0000000f, 0x0100000a,
979 	0x8d00, 0xffff7f7f, 0x100e4848,
980 	0x8d04, 0x00ffffff, 0x00164745,
981 	0x8c00, 0xfffc0003, 0xe4000003,
982 	0x8c04, 0xf8ff00ff, 0x40600060,
983 	0x8c08, 0x00ff00ff, 0x001c001c,
984 	0x8cf0, 0x1fff1fff, 0x08e00410,
985 	0x8c20, 0x0fff0fff, 0x00800080,
986 	0x8c24, 0x0fff0fff, 0x00800080,
987 	0x8c18, 0xffffffff, 0x20202078,
988 	0x8c1c, 0x0000ffff, 0x00001010,
989 	0x28350, 0x00000f01, 0x00000000,
990 	0x9508, 0x3700001f, 0x00000002,
991 	0x960c, 0xffffffff, 0x54763210,
992 	0x88c4, 0x001f3ae3, 0x000000c2,
993 	0x88d4, 0x0000001f, 0x00000010,
994 	0x8974, 0xffffffff, 0x00000000
999 	switch (rdev->family) {  in evergreen_init_golden_registers()
1084  * evergreen_get_allowed_info_register - fetch the register for the info ioctl
1090  * Returns 0 for success or -EINVAL for an invalid register
1105 		return 0;  in evergreen_get_allowed_info_register()
1107 		return -EINVAL;  in evergreen_get_allowed_info_register()
1155 	for (i = 0; i < 100; i++) {  in sumo_set_uvd_clock()
1161 		return -ETIMEDOUT;  in sumo_set_uvd_clock()
1163 	return 0;  in sumo_set_uvd_clock()
1168 	int r = 0;  in sumo_set_uvd_clocks()
1174 	cg_scratch &= 0xffff0000;  in sumo_set_uvd_clocks()
1180 	cg_scratch &= 0x0000ffff;  in sumo_set_uvd_clocks()
1192 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;  in evergreen_set_uvd_clocks()
1206 		return 0;  in evergreen_set_uvd_clocks()
1210 					  16384, 0x03FFFFFF, 0, 128, 5,  in evergreen_set_uvd_clocks()
1218 	/* toggle UPLL_SLEEP to 1 then back to 0 */  in evergreen_set_uvd_clocks()
1220 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in evergreen_set_uvd_clocks()
1223 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1235 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in evergreen_set_uvd_clocks()
1240 	/* set ref divider to 0 */  in evergreen_set_uvd_clocks()
1241 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in evergreen_set_uvd_clocks()
1244 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in evergreen_set_uvd_clocks()
1257 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1262 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in evergreen_set_uvd_clocks()
1275 	return 0;  in evergreen_set_uvd_clocks()
1283 	readrq = pcie_get_readrq(rdev->pdev);  in evergreen_fix_pci_max_read_req_size()
1284 	v = ffs(readrq) - 8;  in evergreen_fix_pci_max_read_req_size()
1288 	if ((v == 0) || (v == 6) || (v == 7))  in evergreen_fix_pci_max_read_req_size()
1289 		pcie_set_readrq(rdev->pdev, 512);  in evergreen_fix_pci_max_read_req_size()
1294 	struct drm_device *dev = encoder->dev;  in dce4_program_fmt()
1295 	struct radeon_device *rdev = dev->dev_private;  in dce4_program_fmt()
1297 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()
1299 	int bpc = 0;  in dce4_program_fmt()
1300 	u32 tmp = 0;  in dce4_program_fmt()
1306 		dither = radeon_connector->dither;  in dce4_program_fmt()
1310 	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)  in dce4_program_fmt()
1314 	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||  in dce4_program_fmt()
1315 	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))  in dce4_program_fmt()
1318 	if (bpc == 0)  in dce4_program_fmt()
1345 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1370  * dce4_wait_for_vblank - vblank wait asic callback.
1379 	unsigned i = 0;  in dce4_wait_for_vblank()
1381 	if (crtc >= rdev->num_crtc)  in dce4_wait_for_vblank()
1391 		if (i++ % 100 == 0) {  in dce4_wait_for_vblank()
1398 		if (i++ % 100 == 0) {  in dce4_wait_for_vblank()
1406  * evergreen_page_flip - pageflip callback.
1419 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()
1420 	struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;  in evergreen_page_flip()
1423 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1424 	       async ? EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);  in evergreen_page_flip()
1426 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1427 	       fb->pitches[0] / fb->format->cpp[0]);  in evergreen_page_flip()
1429 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1431 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1434 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1438  * evergreen_page_flip_pending - check if page flip is still pending
1447 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()
1450 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1458 	int actual_temp = 0;  in evergreen_get_temp()
1460 	if (rdev->family == CHIP_JUNIPER) {  in evergreen_get_temp()
1466 		if (toffset & 0x100)  in evergreen_get_temp()
1467 			actual_temp = temp / 2 - (0x200 - toffset);  in evergreen_get_temp()
1477 		if (temp & 0x400)  in evergreen_get_temp()
1478 			actual_temp = -256;  in evergreen_get_temp()
1479 		else if (temp & 0x200)  in evergreen_get_temp()
1481 		else if (temp & 0x100) {  in evergreen_get_temp()
1482 			actual_temp = temp & 0x1ff;  in evergreen_get_temp()
1483 			actual_temp |= ~0x1ff;  in evergreen_get_temp()
1485 			actual_temp = temp & 0xff;  in evergreen_get_temp()
1495 	u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;  in sumo_get_temp()
1496 	int actual_temp = temp - 49;  in sumo_get_temp()
1502  * sumo_pm_init_profile - Initialize power profiles callback.
1515 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;  in sumo_pm_init_profile()
1516 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in sumo_pm_init_profile()
1517 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1518 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1521 	if (rdev->flags & RADEON_IS_MOBILITY)  in sumo_pm_init_profile()
1522 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);  in sumo_pm_init_profile()
1524 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in sumo_pm_init_profile()
1526 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1527 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1528 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1529 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1531 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1532 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1533 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1534 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1536 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1537 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1538 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1539 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1541 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1542 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1543 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1544 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1547 	idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in sumo_pm_init_profile()
1548 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1549 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1550 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1551 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =  in sumo_pm_init_profile()
1552 		rdev->pm.power_state[idx].num_clock_modes - 1;  in sumo_pm_init_profile()
1554 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1555 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1556 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1557 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =  in sumo_pm_init_profile()
1558 		rdev->pm.power_state[idx].num_clock_modes - 1;  in sumo_pm_init_profile()
1562  * btc_pm_init_profile - Initialize power profiles callback.
1575 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;  in btc_pm_init_profile()
1576 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in btc_pm_init_profile()
1577 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1578 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1583 	if (rdev->flags & RADEON_IS_MOBILITY)  in btc_pm_init_profile()
1584 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);  in btc_pm_init_profile()
1586 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in btc_pm_init_profile()
1588 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1589 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1590 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1591 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;  in btc_pm_init_profile()
1593 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1594 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1595 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1596 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;  in btc_pm_init_profile()
1598 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1599 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1600 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1601 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1603 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1604 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1605 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1606 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;  in btc_pm_init_profile()
1608 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1609 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1610 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1611 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;  in btc_pm_init_profile()
1613 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1614 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1615 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1616 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1620  * evergreen_pm_misc - set additional pm hw parameters callback.
1624  * Set non-clock parameters associated with a power state
1629 	int req_ps_idx = rdev->pm.requested_power_state_index;  in evergreen_pm_misc()
1630 	int req_cm_idx = rdev->pm.requested_clock_mode_index;  in evergreen_pm_misc()
1631 	struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];  in evergreen_pm_misc()
1632 	struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;  in evergreen_pm_misc()
1634 	if (voltage->type == VOLTAGE_SW) {  in evergreen_pm_misc()
1635 		/* 0xff0x are flags rather then an actual voltage */  in evergreen_pm_misc()
1636 		if ((voltage->voltage & 0xff00) == 0xff00)  in evergreen_pm_misc()
1638 		if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {  in evergreen_pm_misc()
1639 			radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);  in evergreen_pm_misc()
1640 			rdev->pm.current_vddc = voltage->voltage;  in evergreen_pm_misc()
1641 			DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);  in evergreen_pm_misc()
1648 		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&  in evergreen_pm_misc()
1649 		    (rdev->family >= CHIP_BARTS) &&  in evergreen_pm_misc()
1650 		    rdev->pm.active_crtc_count &&  in evergreen_pm_misc()
1651 		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||  in evergreen_pm_misc()
1652 		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))  in evergreen_pm_misc()
1653 			voltage = &rdev->pm.power_state[req_ps_idx].  in evergreen_pm_misc()
1654 				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;  in evergreen_pm_misc()
1656 		/* 0xff0x are flags rather then an actual voltage */  in evergreen_pm_misc()
1657 		if ((voltage->vddci & 0xff00) == 0xff00)  in evergreen_pm_misc()
1659 		if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {  in evergreen_pm_misc()
1660 			radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);  in evergreen_pm_misc()
1661 			rdev->pm.current_vddci = voltage->vddci;  in evergreen_pm_misc()
1662 			DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);  in evergreen_pm_misc()
1668  * evergreen_pm_prepare - pre-power state change callback.
1682 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {  in evergreen_pm_prepare()
1684 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1685 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1687 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1693  * evergreen_pm_finish - post-power state change callback.
1707 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {  in evergreen_pm_finish()
1709 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1710 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1712 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1718  * evergreen_hpd_sense - hpd sense callback.
1735  * evergreen_hpd_set_polarity - hpd set polarity callback.
1757  * evergreen_hpd_init - hpd setup callback.
1768 	unsigned enabled = 0;  in evergreen_hpd_init()
1769 	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |  in evergreen_hpd_init()
1770 		DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;  in evergreen_hpd_init()
1772 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {  in evergreen_hpd_init()
1774 			to_radeon_connector(connector)->hpd.hpd;  in evergreen_hpd_init()
1776 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||  in evergreen_hpd_init()
1777 		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {  in evergreen_hpd_init()
1798  * evergreen_hpd_fini - hpd tear down callback.
1809 	unsigned disabled = 0;  in evergreen_hpd_fini()
1811 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {  in evergreen_hpd_fini()
1813 			to_radeon_connector(connector)->hpd.hpd;  in evergreen_hpd_fini()
1818 		WREG32(DC_HPDx_CONTROL(hpd), 0);  in evergreen_hpd_fini()
1832 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1838 	 * preset allocations specified in bits 2:0:  in evergreen_line_buffer_adjust()
1840 	 *  0 - first half of lb (3840 * 2)  in evergreen_line_buffer_adjust()
1841 	 *  1 - first 3/4 of lb (5760 * 2)  in evergreen_line_buffer_adjust()
1842 	 *  2 - whole lb (7680 * 2), other crtc must be disabled  in evergreen_line_buffer_adjust()
1843 	 *  3 - first 1/4 of lb (1920 * 2)  in evergreen_line_buffer_adjust()
1845 	 *  4 - second half of lb (3840 * 2)  in evergreen_line_buffer_adjust()
1846 	 *  5 - second 3/4 of lb (5760 * 2)  in evergreen_line_buffer_adjust()
1847 	 *  6 - whole lb (7680 * 2), other crtc must be disabled  in evergreen_line_buffer_adjust()
1848 	 *  7 - last 1/4 of lb (1920 * 2)  in evergreen_line_buffer_adjust()
1852 	 * non-linked crtcs for maximum line buffer allocation.  in evergreen_line_buffer_adjust()
1854 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1856 			tmp = 0; /* 1/2 */  in evergreen_line_buffer_adjust()
1863 		tmp = 0;  in evergreen_line_buffer_adjust()
1864 		buffer_alloc = 0;  in evergreen_line_buffer_adjust()
1868 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1870 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1875 		for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_line_buffer_adjust()
1883 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1885 		case 0:  in evergreen_line_buffer_adjust()
1914 	return 0;  in evergreen_line_buffer_adjust()
1922 	case 0:  in evergreen_get_number_of_dram_channels()
1958 	yclk.full = dfixed_const(wm->yclk);  in evergreen_dram_bandwidth()
1960 	dram_channels.full = dfixed_const(wm->dram_channels * 4);  in evergreen_dram_bandwidth()
1978 	yclk.full = dfixed_const(wm->yclk);  in evergreen_dram_bandwidth_for_display()
1980 	dram_channels.full = dfixed_const(wm->dram_channels * 4);  in evergreen_dram_bandwidth_for_display()
1998 	sclk.full = dfixed_const(wm->sclk);  in evergreen_data_return_bandwidth()
2018 	disp_clk.full = dfixed_const(wm->disp_clk);  in evergreen_dmif_request_bandwidth()
2053 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);  in evergreen_average_bandwidth()
2055 	bpp.full = dfixed_const(wm->bytes_per_pixel);  in evergreen_average_bandwidth()
2056 	src_width.full = dfixed_const(wm->src_width);  in evergreen_average_bandwidth()
2058 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);  in evergreen_average_bandwidth()
2071 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */  in evergreen_latency_watermark()
2072 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +  in evergreen_latency_watermark()
2073 		(wm->num_heads * cursor_line_pair_return_time);  in evergreen_latency_watermark()
2078 	if (wm->num_heads == 0)  in evergreen_latency_watermark()
2079 		return 0;  in evergreen_latency_watermark()
2083 	if ((wm->vsc.full > a.full) ||  in evergreen_latency_watermark()
2084 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||  in evergreen_latency_watermark()
2085 	    (wm->vtaps >= 5) ||  in evergreen_latency_watermark()
2086 	    ((wm->vsc.full >= a.full) && wm->interlaced))  in evergreen_latency_watermark()
2092 	b.full = dfixed_const(wm->num_heads);  in evergreen_latency_watermark()
2095 	lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel / 1000);  in evergreen_latency_watermark()
2097 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);  in evergreen_latency_watermark()
2104 	if (line_fill_time < wm->active_time)  in evergreen_latency_watermark()
2107 		return latency + (line_fill_time - wm->active_time);  in evergreen_latency_watermark()
2114 	    (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))  in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2123 	    (evergreen_available_bandwidth(wm) / wm->num_heads))  in evergreen_average_bandwidth_vs_available_bandwidth()
2131 	u32 lb_partitions = wm->lb_size / wm->src_width;  in evergreen_check_latency_hiding()
2132 	u32 line_time = wm->active_time + wm->blank_time;  in evergreen_check_latency_hiding()
2138 	if (wm->vsc.full > a.full)  in evergreen_check_latency_hiding()
2141 		if (lb_partitions <= (wm->vtaps + 1))  in evergreen_check_latency_hiding()
2147 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);  in evergreen_check_latency_hiding()
2159 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2163 	u32 line_time = 0;  in evergreen_program_watermarks()
2164 	u32 latency_watermark_a = 0, latency_watermark_b = 0;  in evergreen_program_watermarks()
2165 	u32 priority_a_mark = 0, priority_b_mark = 0;  in evergreen_program_watermarks()
2168 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2172 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2173 		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,  in evergreen_program_watermarks()
2174 					    (u32)mode->clock);  in evergreen_program_watermarks()
2175 		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,  in evergreen_program_watermarks()
2176 					  (u32)mode->clock);  in evergreen_program_watermarks()
2178 		priority_a_cnt = 0;  in evergreen_program_watermarks()
2179 		priority_b_cnt = 0;  in evergreen_program_watermarks()
2183 		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {  in evergreen_program_watermarks()
2189 			wm_high.yclk = rdev->pm.current_mclk * 10;  in evergreen_program_watermarks()
2190 			wm_high.sclk = rdev->pm.current_sclk * 10;  in evergreen_program_watermarks()
2193 		wm_high.disp_clk = mode->clock;  in evergreen_program_watermarks()
2194 		wm_high.src_width = mode->crtc_hdisplay;  in evergreen_program_watermarks()
2196 		wm_high.blank_time = line_time - wm_high.active_time;  in evergreen_program_watermarks()
2198 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)  in evergreen_program_watermarks()
2200 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2202 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2210 		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {  in evergreen_program_watermarks()
2216 			wm_low.yclk = rdev->pm.current_mclk * 10;  in evergreen_program_watermarks()
2217 			wm_low.sclk = rdev->pm.current_sclk * 10;  in evergreen_program_watermarks()
2220 		wm_low.disp_clk = mode->clock;  in evergreen_program_watermarks()
2221 		wm_low.src_width = mode->crtc_hdisplay;  in evergreen_program_watermarks()
2223 		wm_low.blank_time = line_time - wm_low.active_time;  in evergreen_program_watermarks()
2225 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)  in evergreen_program_watermarks()
2227 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2229 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2246 		    (rdev->disp_priority == 2)) {  in evergreen_program_watermarks()
2253 		    (rdev->disp_priority == 2)) {  in evergreen_program_watermarks()
2259 		b.full = dfixed_const(mode->clock);  in evergreen_program_watermarks()
2263 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2271 		b.full = dfixed_const(mode->clock);  in evergreen_program_watermarks()
2275 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2283 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in evergreen_program_watermarks()
2307 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2308 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2311 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2312 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2313 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()
2317  * evergreen_bandwidth_update - update display watermarks callback.
2328 	u32 num_heads = 0, lb_size;  in evergreen_bandwidth_update()
2331 	if (!rdev->mode_info.mode_config_initialized)  in evergreen_bandwidth_update()
2336 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_bandwidth_update()
2337 		if (rdev->mode_info.crtcs[i]->base.enabled)  in evergreen_bandwidth_update()
2340 	for (i = 0; i < rdev->num_crtc; i += 2) {  in evergreen_bandwidth_update()
2341 		mode0 = &rdev->mode_info.crtcs[i]->base.mode;  in evergreen_bandwidth_update()
2342 		mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;  in evergreen_bandwidth_update()
2343 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);  in evergreen_bandwidth_update()
2344 		evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);  in evergreen_bandwidth_update()
2345 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);  in evergreen_bandwidth_update()
2346 		evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);  in evergreen_bandwidth_update()
2351  * evergreen_mc_wait_for_idle - wait for MC idle callback.
2357  * Returns 0 if the MC is idle, -1 if not.
2364 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_mc_wait_for_idle()
2366 		tmp = RREG32(SRBM_STATUS) & 0x1F00;  in evergreen_mc_wait_for_idle()
2368 			return 0;  in evergreen_mc_wait_for_idle()
2371 	return -1;  in evergreen_mc_wait_for_idle()
2382 	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);  in evergreen_pcie_gart_tlb_flush()
2385 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_pcie_gart_tlb_flush()
2405 	if (rdev->gart.robj == NULL) {  in evergreen_pcie_gart_enable()
2406 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");  in evergreen_pcie_gart_enable()
2407 		return -EINVAL;  in evergreen_pcie_gart_enable()
2416 	WREG32(VM_L2_CNTL2, 0);  in evergreen_pcie_gart_enable()
2417 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_pcie_gart_enable()
2423 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_pcie_gart_enable()
2431 		if ((rdev->family == CHIP_JUNIPER) ||  in evergreen_pcie_gart_enable()
2432 		    (rdev->family == CHIP_CYPRESS) ||  in evergreen_pcie_gart_enable()
2433 		    (rdev->family == CHIP_HEMLOCK) ||  in evergreen_pcie_gart_enable()
2434 		    (rdev->family == CHIP_BARTS))  in evergreen_pcie_gart_enable()
2441 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in evergreen_pcie_gart_enable()
2442 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in evergreen_pcie_gart_enable()
2443 	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);  in evergreen_pcie_gart_enable()
2444 	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |  in evergreen_pcie_gart_enable()
2447 			(u32)(rdev->dummy_page.addr >> 12));  in evergreen_pcie_gart_enable()
2448 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_pcie_gart_enable()
2451 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",  in evergreen_pcie_gart_enable()
2452 		 (unsigned)(rdev->mc.gtt_size >> 20),  in evergreen_pcie_gart_enable()
2453 		 (unsigned long long)rdev->gart.table_addr);  in evergreen_pcie_gart_enable()
2454 	rdev->gart.ready = true;  in evergreen_pcie_gart_enable()
2455 	return 0;  in evergreen_pcie_gart_enable()
2463 	WREG32(VM_CONTEXT0_CNTL, 0);  in evergreen_pcie_gart_disable()
2464 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_pcie_gart_disable()
2469 	WREG32(VM_L2_CNTL2, 0);  in evergreen_pcie_gart_disable()
2470 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_pcie_gart_disable()
2499 	WREG32(VM_L2_CNTL2, 0);  in evergreen_agp_enable()
2500 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_agp_enable()
2513 	WREG32(VM_CONTEXT0_CNTL, 0);  in evergreen_agp_enable()
2514 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_agp_enable()
2578 	for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {  in evergreen_is_dp_sst_stream_enabled()
2592 		for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {  in evergreen_is_dp_sst_stream_enabled()
2628 	unsigned counter = 0;  in evergreen_blank_dp_output()
2670 		save->vga_render_control = RREG32(VGA_RENDER_CONTROL);  in evergreen_mc_stop()
2671 		save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);  in evergreen_mc_stop()
2674 		WREG32(VGA_RENDER_CONTROL, 0);  in evergreen_mc_stop()
2677 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_stop()
2680 			save->crtc_enabled[i] = true;  in evergreen_mc_stop()
2688 					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2697 					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2702 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_stop()
2723 			WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2724 			save->crtc_enabled[i] = false;  in evergreen_mc_stop()
2727 			save->crtc_enabled[i] = false;  in evergreen_mc_stop()
2736 		WREG32(BIF_FB_EN, 0);  in evergreen_mc_stop()
2745 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_stop()
2746 		if (save->crtc_enabled[i]) {  in evergreen_mc_stop()
2767 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2769 		       upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2771 		       upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2773 		       (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2775 		       (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2779 		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2780 		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2784 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2785 		if (save->crtc_enabled[i]) {  in evergreen_mc_resume()
2787 			if ((tmp & 0x7) != 0) {  in evergreen_mc_resume()
2788 				tmp &= ~0x7;  in evergreen_mc_resume()
2801 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_resume()
2803 				if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)  in evergreen_mc_resume()
2817 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2818 		if (save->crtc_enabled[i]) {  in evergreen_mc_resume()
2824 				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_resume()
2830 				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_resume()
2834 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_resume()
2843 		WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);  in evergreen_mc_resume()
2845 		WREG32(VGA_RENDER_CONTROL, save->vga_render_control);  in evergreen_mc_resume()
2856 	for (i = 0, j = 0; i < 32; i++, j += 0x18) {  in evergreen_mc_program()
2857 		WREG32((0x2c14 + j), 0x00000000);  in evergreen_mc_program()
2858 		WREG32((0x2c18 + j), 0x00000000);  in evergreen_mc_program()
2859 		WREG32((0x2c1c + j), 0x00000000);  in evergreen_mc_program()
2860 		WREG32((0x2c20 + j), 0x00000000);  in evergreen_mc_program()
2861 		WREG32((0x2c24 + j), 0x00000000);  in evergreen_mc_program()
2863 	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);  in evergreen_mc_program()
2867 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_mc_program()
2872 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_mc_program()
2873 		if (rdev->mc.vram_start < rdev->mc.gtt_start) {  in evergreen_mc_program()
2876 				rdev->mc.vram_start >> 12);  in evergreen_mc_program()
2878 				rdev->mc.gtt_end >> 12);  in evergreen_mc_program()
2882 				rdev->mc.gtt_start >> 12);  in evergreen_mc_program()
2884 				rdev->mc.vram_end >> 12);  in evergreen_mc_program()
2888 			rdev->mc.vram_start >> 12);  in evergreen_mc_program()
2890 			rdev->mc.vram_end >> 12);  in evergreen_mc_program()
2892 	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);  in evergreen_mc_program()
2894 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_program()
2895 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_program()
2896 	    (rdev->family == CHIP_SUMO2)) {  in evergreen_mc_program()
2897 		tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;  in evergreen_mc_program()
2898 		tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;  in evergreen_mc_program()
2899 		tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;  in evergreen_mc_program()
2902 	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;  in evergreen_mc_program()
2903 	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);  in evergreen_mc_program()
2905 	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));  in evergreen_mc_program()
2907 	WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in evergreen_mc_program()
2908 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_mc_program()
2909 		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);  in evergreen_mc_program()
2910 		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);  in evergreen_mc_program()
2911 		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);  in evergreen_mc_program()
2913 		WREG32(MC_VM_AGP_BASE, 0);  in evergreen_mc_program()
2914 		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);  in evergreen_mc_program()
2915 		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);  in evergreen_mc_program()
2918 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_mc_program()
2931 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in evergreen_ring_ib_execute()
2935 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in evergreen_ring_ib_execute()
2938 	if (ring->rptr_save_reg) {  in evergreen_ring_ib_execute()
2939 		next_rptr = ring->wptr + 3 + 4;  in evergreen_ring_ib_execute()
2941 		radeon_ring_write(ring, ((ring->rptr_save_reg -   in evergreen_ring_ib_execute()
2944 	} else if (rdev->wb.enabled) {  in evergreen_ring_ib_execute()
2945 		next_rptr = ring->wptr + 5 + 4;  in evergreen_ring_ib_execute()
2947 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_ring_ib_execute()
2948 		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));  in evergreen_ring_ib_execute()
2950 		radeon_ring_write(ring, 0);  in evergreen_ring_ib_execute()
2956 			  (2 << 0) |  in evergreen_ring_ib_execute()
2958 			  (ib->gpu_addr & 0xFFFFFFFC));  in evergreen_ring_ib_execute()
2959 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);  in evergreen_ring_ib_execute()
2960 	radeon_ring_write(ring, ib->length_dw);  in evergreen_ring_ib_execute()
2969 	if (!rdev->me_fw || !rdev->pfp_fw)  in evergreen_cp_load_microcode()
2970 		return -EINVAL;  in evergreen_cp_load_microcode()
2979 	fw_data = (const __be32 *)rdev->pfp_fw->data;  in evergreen_cp_load_microcode()
2980 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2981 	for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)  in evergreen_cp_load_microcode()
2983 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2985 	fw_data = (const __be32 *)rdev->me_fw->data;  in evergreen_cp_load_microcode()
2986 	WREG32(CP_ME_RAM_WADDR, 0);  in evergreen_cp_load_microcode()
2987 	for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)  in evergreen_cp_load_microcode()
2990 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2991 	WREG32(CP_ME_RAM_WADDR, 0);  in evergreen_cp_load_microcode()
2992 	WREG32(CP_ME_RAM_RADDR, 0);  in evergreen_cp_load_microcode()
2993 	return 0;  in evergreen_cp_load_microcode()
2998 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_start()
3008 	radeon_ring_write(ring, 0x1);  in evergreen_cp_start()
3009 	radeon_ring_write(ring, 0x0);  in evergreen_cp_start()
3010 	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);  in evergreen_cp_start()
3012 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3013 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3016 	cp_me = 0xff;  in evergreen_cp_start()
3026 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3029 	for (i = 0; i < evergreen_default_size; i++)  in evergreen_cp_start()
3032 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3036 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in evergreen_cp_start()
3037 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3040 	radeon_ring_write(ring, 0xc0026f00);  in evergreen_cp_start()
3041 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3042 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3043 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3046 	radeon_ring_write(ring, 0xc0036f00);  in evergreen_cp_start()
3047 	radeon_ring_write(ring, 0x00000bc4);  in evergreen_cp_start()
3048 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3049 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3050 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3052 	radeon_ring_write(ring, 0xc0026900);  in evergreen_cp_start()
3053 	radeon_ring_write(ring, 0x00000316);  in evergreen_cp_start()
3054 	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */  in evergreen_cp_start()
3055 	radeon_ring_write(ring, 0x00000010); /*  */  in evergreen_cp_start()
3059 	return 0;  in evergreen_cp_start()
3064 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_resume()
3078 	WREG32(GRBM_SOFT_RESET, 0);  in evergreen_cp_resume()
3082 	rb_bufsz = order_base_2(ring->ring_size / 8);  in evergreen_cp_resume()
3088 	WREG32(CP_SEM_WAIT_TIMER, 0x0);  in evergreen_cp_resume()
3089 	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);  in evergreen_cp_resume()
3092 	WREG32(CP_RB_WPTR_DELAY, 0);  in evergreen_cp_resume()
3096 	WREG32(CP_RB_RPTR_WR, 0);  in evergreen_cp_resume()
3097 	ring->wptr = 0;  in evergreen_cp_resume()
3098 	WREG32(CP_RB_WPTR, ring->wptr);  in evergreen_cp_resume()
3102 	       ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));  in evergreen_cp_resume()
3103 	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in evergreen_cp_resume()
3104 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in evergreen_cp_resume()
3106 	if (rdev->wb.enabled)  in evergreen_cp_resume()
3107 		WREG32(SCRATCH_UMSK, 0xff);  in evergreen_cp_resume()
3110 		WREG32(SCRATCH_UMSK, 0);  in evergreen_cp_resume()
3116 	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);  in evergreen_cp_resume()
3120 	ring->ready = true;  in evergreen_cp_resume()
3123 		ring->ready = false;  in evergreen_cp_resume()
3126 	return 0;  in evergreen_cp_resume()
3153 	switch (rdev->family) {  in evergreen_gpu_init()
3156 		rdev->config.evergreen.num_ses = 2;  in evergreen_gpu_init()
3157 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3158 		rdev->config.evergreen.max_tile_pipes = 8;  in evergreen_gpu_init()
3159 		rdev->config.evergreen.max_simds = 10;  in evergreen_gpu_init()
3160 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3161 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3162 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3163 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3164 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3165 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3166 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3167 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3168 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3169 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3170 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3172 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3173 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3174 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3178 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3179 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3180 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3181 		rdev->config.evergreen.max_simds = 10;  in evergreen_gpu_init()
3182 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3183 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3184 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3185 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3186 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3187 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3188 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3189 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3190 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3191 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3192 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3194 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3195 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3196 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3200 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3201 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3202 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3203 		rdev->config.evergreen.max_simds = 5;  in evergreen_gpu_init()
3204 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3205 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3206 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3207 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3208 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3209 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3210 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3211 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3212 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3213 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3214 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3216 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3217 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3218 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3223 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3224 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3225 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3226 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3227 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3228 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3229 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3230 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3231 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3232 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3233 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3234 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3235 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3236 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3237 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3239 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3240 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3241 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3245 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3246 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3247 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3248 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3249 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3250 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3251 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3252 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3253 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3254 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3255 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3256 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3257 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3258 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3259 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3261 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3262 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3263 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3267 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3268 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3269 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3270 		if (rdev->pdev->device == 0x9648)  in evergreen_gpu_init()
3271 			rdev->config.evergreen.max_simds = 3;  in evergreen_gpu_init()
3272 		else if ((rdev->pdev->device == 0x9647) ||  in evergreen_gpu_init()
3273 			 (rdev->pdev->device == 0x964a))  in evergreen_gpu_init()
3274 			rdev->config.evergreen.max_simds = 4;  in evergreen_gpu_init()
3276 			rdev->config.evergreen.max_simds = 5;  in evergreen_gpu_init()
3277 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3278 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3279 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3280 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3281 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3282 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3283 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3284 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3285 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3286 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3287 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3289 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3290 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3291 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3295 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3296 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3297 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3298 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3299 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3300 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3301 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3302 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3303 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3304 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3305 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3306 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3307 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3308 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3309 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3311 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3312 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3313 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3317 		rdev->config.evergreen.num_ses = 2;  in evergreen_gpu_init()
3318 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3319 		rdev->config.evergreen.max_tile_pipes = 8;  in evergreen_gpu_init()
3320 		rdev->config.evergreen.max_simds = 7;  in evergreen_gpu_init()
3321 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3322 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3323 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3324 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3325 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3326 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3327 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3328 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3329 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3330 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3331 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3333 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3334 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3335 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3339 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3340 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3341 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3342 		rdev->config.evergreen.max_simds = 6;  in evergreen_gpu_init()
3343 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3344 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3345 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3346 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3347 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3348 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3349 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3350 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3351 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3352 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3353 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3355 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3356 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3357 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3361 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3362 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3363 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3364 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3365 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3366 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3367 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3368 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3369 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3370 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3371 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3372 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3373 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3374 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3375 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3377 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3378 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3379 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3385 	for (i = 0, j = 0; i < 32; i++, j += 0x18) {  in evergreen_gpu_init()
3386 		WREG32((0x2c14 + j), 0x00000000);  in evergreen_gpu_init()
3387 		WREG32((0x2c18 + j), 0x00000000);  in evergreen_gpu_init()
3388 		WREG32((0x2c1c + j), 0x00000000);  in evergreen_gpu_init()
3389 		WREG32((0x2c20 + j), 0x00000000);  in evergreen_gpu_init()
3390 		WREG32((0x2c24 + j), 0x00000000);  in evergreen_gpu_init()
3393 	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));  in evergreen_gpu_init()
3394 	WREG32(SRBM_INT_CNTL, 0x1);  in evergreen_gpu_init()
3395 	WREG32(SRBM_INT_ACK, 0x1);  in evergreen_gpu_init()
3400 	if ((rdev->family == CHIP_PALM) ||  in evergreen_gpu_init()
3401 	    (rdev->family == CHIP_SUMO) ||  in evergreen_gpu_init()
3402 	    (rdev->family == CHIP_SUMO2))  in evergreen_gpu_init()
3409 	 * bits 3:0   num_pipes  in evergreen_gpu_init()
3414 	rdev->config.evergreen.tile_config = 0;  in evergreen_gpu_init()
3415 	switch (rdev->config.evergreen.max_tile_pipes) {  in evergreen_gpu_init()
3418 		rdev->config.evergreen.tile_config |= (0 << 0);  in evergreen_gpu_init()
3421 		rdev->config.evergreen.tile_config |= (1 << 0);  in evergreen_gpu_init()
3424 		rdev->config.evergreen.tile_config |= (2 << 0);  in evergreen_gpu_init()
3427 		rdev->config.evergreen.tile_config |= (3 << 0);  in evergreen_gpu_init()
3430 	/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */  in evergreen_gpu_init()
3431 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_gpu_init()
3432 		rdev->config.evergreen.tile_config |= 1 << 4;  in evergreen_gpu_init()
3435 		case 0: /* four banks */  in evergreen_gpu_init()
3436 			rdev->config.evergreen.tile_config |= 0 << 4;  in evergreen_gpu_init()
3439 			rdev->config.evergreen.tile_config |= 1 << 4;  in evergreen_gpu_init()
3443 			rdev->config.evergreen.tile_config |= 2 << 4;  in evergreen_gpu_init()
3447 	rdev->config.evergreen.tile_config |= 0 << 8;  in evergreen_gpu_init()
3448 	rdev->config.evergreen.tile_config |=  in evergreen_gpu_init()
3449 		((gb_addr_config & 0x30000000) >> 28) << 12;  in evergreen_gpu_init()
3451 	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {  in evergreen_gpu_init()
3455 		efuse_straps_4 = RREG32_RCU(0x204);  in evergreen_gpu_init()
3456 		efuse_straps_3 = RREG32_RCU(0x203);  in evergreen_gpu_init()
3457 		tmp = (((efuse_straps_4 & 0xf) << 4) |  in evergreen_gpu_init()
3458 		      ((efuse_straps_3 & 0xf0000000) >> 28));  in evergreen_gpu_init()
3460 		tmp = 0;  in evergreen_gpu_init()
3461 		for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {  in evergreen_gpu_init()
3466 			rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;  in evergreen_gpu_init()
3473 	tmp = 0;  in evergreen_gpu_init()
3474 	for (i = 0; i < rdev->config.evergreen.max_backends; i++)  in evergreen_gpu_init()
3478 		for (i = 0; i < rdev->config.evergreen.max_backends; i++)  in evergreen_gpu_init()
3482 	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {  in evergreen_gpu_init()
3487 		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in evergreen_gpu_init()
3488 		simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;  in evergreen_gpu_init()
3492 	rdev->config.evergreen.active_simds = hweight32(~tmp);  in evergreen_gpu_init()
3505 	if ((rdev->config.evergreen.max_backends == 1) &&  in evergreen_gpu_init()
3506 	    (rdev->flags & RADEON_IS_IGP)) {  in evergreen_gpu_init()
3509 			tmp = 0x11111111;  in evergreen_gpu_init()
3512 			tmp = 0x00000000;  in evergreen_gpu_init()
3516 		tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,  in evergreen_gpu_init()
3519 	rdev->config.evergreen.backend_map = tmp;  in evergreen_gpu_init()
3522 	WREG32(CGTS_SYS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3523 	WREG32(CGTS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3524 	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3525 	WREG32(CGTS_USER_TCC_DISABLE, 0);  in evergreen_gpu_init()
3528 	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |  in evergreen_gpu_init()
3529 				     ROQ_IB2_START(0x2b)));  in evergreen_gpu_init()
3531 	WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));  in evergreen_gpu_init()
3544 	smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);  in evergreen_gpu_init()
3545 	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);  in evergreen_gpu_init()
3548 	if (rdev->family <= CHIP_SUMO2)  in evergreen_gpu_init()
3549 		WREG32(SMX_SAR_CTL0, 0x00010000);  in evergreen_gpu_init()
3551 …REG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) -…  in evergreen_gpu_init()
3552 					POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |  in evergreen_gpu_init()
3553 					SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));  in evergreen_gpu_init()
3555 	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |  in evergreen_gpu_init()
3556 				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |  in evergreen_gpu_init()
3557 				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));  in evergreen_gpu_init()
3560 	WREG32(SPI_CONFIG_CNTL, 0);  in evergreen_gpu_init()
3562 	WREG32(CP_PERFMON_CNTL, 0);  in evergreen_gpu_init()
3564 	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |  in evergreen_gpu_init()
3565 				  FETCH_FIFO_HIWATER(0x4) |  in evergreen_gpu_init()
3566 				  DONE_FIFO_HIWATER(0xe0) |  in evergreen_gpu_init()
3567 				  ALU_UPDATE_FIFO_HIWATER(0x8)));  in evergreen_gpu_init()
3576 		      PS_PRIO(0) |  in evergreen_gpu_init()
3581 	switch (rdev->family) {  in evergreen_gpu_init()
3596 	sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 12 / 32);  in evergreen_gpu_init()
3597 	sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);  in evergreen_gpu_init()
3599 	sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);  in evergreen_gpu_init()
3600 	sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);  in evergreen_gpu_init()
3601 	sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);  in evergreen_gpu_init()
3602 	sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);  in evergreen_gpu_init()
3604 	switch (rdev->family) {  in evergreen_gpu_init()
3617 …sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3618 …sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3619 …sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3620 …sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count…  in evergreen_gpu_init()
3621 …sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_coun…  in evergreen_gpu_init()
3623 …sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3624 …sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3625 …sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3626 …sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3627 …sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3628 …sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3639 	WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);  in evergreen_gpu_init()
3645 	switch (rdev->family) {  in evergreen_gpu_init()
3661 	WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);  in evergreen_gpu_init()
3662 	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);  in evergreen_gpu_init()
3667 	WREG32(CB_PERF_CTR0_SEL_0, 0);  in evergreen_gpu_init()
3668 	WREG32(CB_PERF_CTR0_SEL_1, 0);  in evergreen_gpu_init()
3669 	WREG32(CB_PERF_CTR1_SEL_0, 0);  in evergreen_gpu_init()
3670 	WREG32(CB_PERF_CTR1_SEL_1, 0);  in evergreen_gpu_init()
3671 	WREG32(CB_PERF_CTR2_SEL_0, 0);  in evergreen_gpu_init()
3672 	WREG32(CB_PERF_CTR2_SEL_1, 0);  in evergreen_gpu_init()
3673 	WREG32(CB_PERF_CTR3_SEL_0, 0);  in evergreen_gpu_init()
3674 	WREG32(CB_PERF_CTR3_SEL_1, 0);  in evergreen_gpu_init()
3677 	WREG32(CB_COLOR0_BASE, 0);  in evergreen_gpu_init()
3678 	WREG32(CB_COLOR1_BASE, 0);  in evergreen_gpu_init()
3679 	WREG32(CB_COLOR2_BASE, 0);  in evergreen_gpu_init()
3680 	WREG32(CB_COLOR3_BASE, 0);  in evergreen_gpu_init()
3681 	WREG32(CB_COLOR4_BASE, 0);  in evergreen_gpu_init()
3682 	WREG32(CB_COLOR5_BASE, 0);  in evergreen_gpu_init()
3683 	WREG32(CB_COLOR6_BASE, 0);  in evergreen_gpu_init()
3684 	WREG32(CB_COLOR7_BASE, 0);  in evergreen_gpu_init()
3685 	WREG32(CB_COLOR8_BASE, 0);  in evergreen_gpu_init()
3686 	WREG32(CB_COLOR9_BASE, 0);  in evergreen_gpu_init()
3687 	WREG32(CB_COLOR10_BASE, 0);  in evergreen_gpu_init()
3688 	WREG32(CB_COLOR11_BASE, 0);  in evergreen_gpu_init()
3690 	/* set the shader const cache sizes to 0 */  in evergreen_gpu_init()
3691 	for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)  in evergreen_gpu_init()
3692 		WREG32(i, 0);  in evergreen_gpu_init()
3693 	for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)  in evergreen_gpu_init()
3694 		WREG32(i, 0);  in evergreen_gpu_init()
3715 	rdev->mc.vram_is_ddr = true;  in evergreen_mc_init()
3716 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_init()
3717 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_init()
3718 	    (rdev->family == CHIP_SUMO2))  in evergreen_mc_init()
3731 	case 0:  in evergreen_mc_init()
3745 	rdev->mc.vram_width = numchan * chansize;  in evergreen_mc_init()
3746 	/* Could aper size report 0 ? */  in evergreen_mc_init()
3747 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in evergreen_mc_init()
3748 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in evergreen_mc_init()
3750 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_init()
3751 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_init()
3752 	    (rdev->family == CHIP_SUMO2)) {  in evergreen_mc_init()
3754 		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);  in evergreen_mc_init()
3755 		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);  in evergreen_mc_init()
3758 		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in evergreen_mc_init()
3759 		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in evergreen_mc_init()
3761 	rdev->mc.visible_vram_size = rdev->mc.aper_size;  in evergreen_mc_init()
3762 	r700_vram_gtt_location(rdev, &rdev->mc);  in evergreen_mc_init()
3765 	return 0;  in evergreen_mc_init()
3770 	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3772 	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3774 	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3776 	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3778 	dev_info(rdev->dev, "  SRBM_STATUS2              = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3780 	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3782 	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3784 	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3786 	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3788 	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3790 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_print_gpu_status_regs()
3791 		dev_info(rdev->dev, "  R_00D834_DMA_STATUS_REG   = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3792 			 RREG32(DMA_STATUS_REG + 0x800));  in evergreen_print_gpu_status_regs()
3798 	u32 crtc_hung = 0;  in evergreen_is_display_hung()
3802 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_is_display_hung()
3809 	for (j = 0; j < 10; j++) {  in evergreen_is_display_hung()
3810 		for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_is_display_hung()
3817 		if (crtc_hung == 0)  in evergreen_is_display_hung()
3827 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()
3887 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3897 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in evergreen_gpu_soft_reset()
3900 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3903 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3921 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_gpu_soft_reset()
3966 	if (!(rdev->flags & RADEON_IS_IGP)) {  in evergreen_gpu_soft_reset()
3974 		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in evergreen_gpu_soft_reset()
3988 		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in evergreen_gpu_soft_reset()
4013 	dev_info(rdev->dev, "GPU pci config reset\n");  in evergreen_gpu_pci_config_reset()
4034 	pci_clear_master(rdev->pdev);  in evergreen_gpu_pci_config_reset()
4038 		dev_warn(rdev->dev, "Wait for MC idle timed out !\n");  in evergreen_gpu_pci_config_reset()
4043 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_gpu_pci_config_reset()
4044 		if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)  in evergreen_gpu_pci_config_reset()
4056 		return 0;  in evergreen_asic_reset()
4078 	return 0;  in evergreen_asic_reset()
4082  * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
4106 #define RLC_SAVE_RESTORE_LIST_END_MARKER    0x00000000
4107 #define RLC_CLEAR_STATE_END_MARKER          0x00000001
4114 	if (rdev->rlc.save_restore_obj) {  in sumo_rlc_fini()
4115 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_fini()
4116 		if (unlikely(r != 0))  in sumo_rlc_fini()
4117 			dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);  in sumo_rlc_fini()
4118 		radeon_bo_unpin(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4119 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4121 		radeon_bo_unref(&rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4122 		rdev->rlc.save_restore_obj = NULL;  in sumo_rlc_fini()
4126 	if (rdev->rlc.clear_state_obj) {  in sumo_rlc_fini()
4127 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_fini()
4128 		if (unlikely(r != 0))  in sumo_rlc_fini()
4129 			dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);  in sumo_rlc_fini()
4130 		radeon_bo_unpin(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4131 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4133 		radeon_bo_unref(&rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4134 		rdev->rlc.clear_state_obj = NULL;  in sumo_rlc_fini()
4138 	if (rdev->rlc.cp_table_obj) {  in sumo_rlc_fini()
4139 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_fini()
4140 		if (unlikely(r != 0))  in sumo_rlc_fini()
4141 			dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);  in sumo_rlc_fini()
4142 		radeon_bo_unpin(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4143 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4145 		radeon_bo_unref(&rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4146 		rdev->rlc.cp_table_obj = NULL;  in sumo_rlc_fini()
4157 	u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index = 0;  in sumo_rlc_init()
4162 	src_ptr = rdev->rlc.reg_list;  in sumo_rlc_init()
4163 	dws = rdev->rlc.reg_list_size;  in sumo_rlc_init()
4164 	if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4167 	cs_data = rdev->rlc.cs_data;  in sumo_rlc_init()
4171 		if (rdev->rlc.save_restore_obj == NULL) {  in sumo_rlc_init()
4173 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4174 					     NULL, &rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4176 				dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);  in sumo_rlc_init()
4181 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_init()
4182 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4186 		r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4187 				  &rdev->rlc.save_restore_gpu_addr);  in sumo_rlc_init()
4189 			radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4190 			dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);  in sumo_rlc_init()
4195 		r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);  in sumo_rlc_init()
4197 			dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);  in sumo_rlc_init()
4202 		dst_ptr = rdev->rlc.sr_ptr;  in sumo_rlc_init()
4203 		if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4205 			for (i = 0; i < rdev->rlc.reg_list_size; i++)  in sumo_rlc_init()
4214 			for (i = 0; i < dws; i++) {  in sumo_rlc_init()
4219 				j = (((i - 1) * 3) / 2);  in sumo_rlc_init()
4225 		radeon_bo_kunmap(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4226 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4231 		if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4232 			rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);  in sumo_rlc_init()
4233 		} else if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4234 			rdev->rlc.clear_state_size = si_get_csb_size(rdev);  in sumo_rlc_init()
4235 			dws = rdev->rlc.clear_state_size + (256 / 4);  in sumo_rlc_init()
4237 			reg_list_num = 0;  in sumo_rlc_init()
4238 			dws = 0;  in sumo_rlc_init()
4239 			for (i = 0; cs_data[i].section != NULL; i++) {  in sumo_rlc_init()
4240 				for (j = 0; cs_data[i].section[j].extent != NULL; j++) {  in sumo_rlc_init()
4247 			rdev->rlc.clear_state_size = dws;  in sumo_rlc_init()
4250 		if (rdev->rlc.clear_state_obj == NULL) {  in sumo_rlc_init()
4252 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4253 					     NULL, &rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4255 				dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);  in sumo_rlc_init()
4260 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_init()
4261 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4265 		r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4266 				  &rdev->rlc.clear_state_gpu_addr);  in sumo_rlc_init()
4268 			radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4269 			dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);  in sumo_rlc_init()
4274 		r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);  in sumo_rlc_init()
4276 			dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);  in sumo_rlc_init()
4281 		dst_ptr = rdev->rlc.cs_ptr;  in sumo_rlc_init()
4282 		if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4284 		} else if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4285 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;  in sumo_rlc_init()
4286 			dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));  in sumo_rlc_init()
4288 			dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);  in sumo_rlc_init()
4291 			reg_list_hdr_blk_index = 0;  in sumo_rlc_init()
4292 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);  in sumo_rlc_init()
4296 			for (i = 0; cs_data[i].section != NULL; i++) {  in sumo_rlc_init()
4297 				for (j = 0; cs_data[i].section[j].extent != NULL; j++) {  in sumo_rlc_init()
4299 					data = reg_list_mc_addr & 0xffffffff;  in sumo_rlc_init()
4303 					data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;  in sumo_rlc_init()
4307 					data = 0x08000000 | (reg_num * 4);  in sumo_rlc_init()
4311 					for (k = 0; k < reg_num; k++) {  in sumo_rlc_init()
4321 		radeon_bo_kunmap(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4322 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4325 	if (rdev->rlc.cp_table_size) {  in sumo_rlc_init()
4326 		if (rdev->rlc.cp_table_obj == NULL) {  in sumo_rlc_init()
4327 			r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,  in sumo_rlc_init()
4329 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4330 					     NULL, &rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4332 				dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);  in sumo_rlc_init()
4338 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_init()
4339 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4340 			dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);  in sumo_rlc_init()
4344 		r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4345 				  &rdev->rlc.cp_table_gpu_addr);  in sumo_rlc_init()
4347 			radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4348 			dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);  in sumo_rlc_init()
4352 		r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);  in sumo_rlc_init()
4354 			dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);  in sumo_rlc_init()
4361 		radeon_bo_kunmap(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4362 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4366 	return 0;  in sumo_rlc_init()
4373 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_rlc_start()
4385 	if (!rdev->rlc_fw)  in evergreen_rlc_resume()
4386 		return -EINVAL;  in evergreen_rlc_resume()
4390 	WREG32(RLC_HB_CNTL, 0);  in evergreen_rlc_resume()
4392 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_rlc_resume()
4393 		if (rdev->family == CHIP_ARUBA) {  in evergreen_rlc_resume()
4395 				3 | (3 << (16 * rdev->config.cayman.max_shader_engines));  in evergreen_rlc_resume()
4397 			u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in evergreen_rlc_resume()
4398 			tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;  in evergreen_rlc_resume()
4400 			if (tmp == rdev->config.cayman.max_simds_per_se) {  in evergreen_rlc_resume()
4402 				WREG32(TN_RLC_LB_PARAMS, 0x00601004);  in evergreen_rlc_resume()
4403 				WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff);  in evergreen_rlc_resume()
4404 				WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000);  in evergreen_rlc_resume()
4405 				WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000);  in evergreen_rlc_resume()
4408 			WREG32(RLC_HB_WPTR_LSB_ADDR, 0);  in evergreen_rlc_resume()
4409 			WREG32(RLC_HB_WPTR_MSB_ADDR, 0);  in evergreen_rlc_resume()
4411 		WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);  in evergreen_rlc_resume()
4412 		WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);  in evergreen_rlc_resume()
4414 		WREG32(RLC_HB_BASE, 0);  in evergreen_rlc_resume()
4415 		WREG32(RLC_HB_RPTR, 0);  in evergreen_rlc_resume()
4416 		WREG32(RLC_HB_WPTR, 0);  in evergreen_rlc_resume()
4417 		WREG32(RLC_HB_WPTR_LSB_ADDR, 0);  in evergreen_rlc_resume()
4418 		WREG32(RLC_HB_WPTR_MSB_ADDR, 0);  in evergreen_rlc_resume()
4420 	WREG32(RLC_MC_CNTL, 0);  in evergreen_rlc_resume()
4421 	WREG32(RLC_UCODE_CNTL, 0);  in evergreen_rlc_resume()
4423 	fw_data = (const __be32 *)rdev->rlc_fw->data;  in evergreen_rlc_resume()
4424 	if (rdev->family >= CHIP_ARUBA) {  in evergreen_rlc_resume()
4425 		for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4429 	} else if (rdev->family >= CHIP_CAYMAN) {  in evergreen_rlc_resume()
4430 		for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4435 		for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4440 	WREG32(RLC_UCODE_ADDR, 0);  in evergreen_rlc_resume()
4444 	return 0;  in evergreen_rlc_resume()
4451 	if (crtc >= rdev->num_crtc)  in evergreen_get_vblank_counter()
4452 		return 0;  in evergreen_get_vblank_counter()
4462 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_disable_interrupt_state()
4463 		cayman_cp_int_cntl_setup(rdev, 0,  in evergreen_disable_interrupt_state()
4465 		cayman_cp_int_cntl_setup(rdev, 1, 0);  in evergreen_disable_interrupt_state()
4466 		cayman_cp_int_cntl_setup(rdev, 2, 0);  in evergreen_disable_interrupt_state()
4473 	WREG32(GRBM_INT_CNTL, 0);  in evergreen_disable_interrupt_state()
4474 	WREG32(SRBM_INT_CNTL, 0);  in evergreen_disable_interrupt_state()
4475 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_disable_interrupt_state()
4476 		WREG32(INT_MASK + crtc_offsets[i], 0);  in evergreen_disable_interrupt_state()
4477 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_disable_interrupt_state()
4478 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);  in evergreen_disable_interrupt_state()
4482 		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);  in evergreen_disable_interrupt_state()
4483 	WREG32(DACB_AUTODETECT_INT_CONTROL, 0);  in evergreen_disable_interrupt_state()
4485 	for (i = 0; i < 6; i++)  in evergreen_disable_interrupt_state()
4494 	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;  in evergreen_irq_set()
4495 	u32 grbm_int_cntl = 0;  in evergreen_irq_set()
4496 	u32 dma_cntl, dma_cntl1 = 0;  in evergreen_irq_set()
4497 	u32 thermal_int = 0;  in evergreen_irq_set()
4499 	if (!rdev->irq.installed) {  in evergreen_irq_set()
4501 		return -EINVAL;  in evergreen_irq_set()
4504 	if (!rdev->ih.enabled) {  in evergreen_irq_set()
4508 		return 0;  in evergreen_irq_set()
4511 	if (rdev->family == CHIP_ARUBA)  in evergreen_irq_set()
4520 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4522 		if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {  in evergreen_irq_set()
4526 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {  in evergreen_irq_set()
4530 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {  in evergreen_irq_set()
4535 		if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {  in evergreen_irq_set()
4542 	if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {  in evergreen_irq_set()
4547 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4549 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {  in evergreen_irq_set()
4555 	if (rdev->irq.dpm_thermal) {  in evergreen_irq_set()
4560 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4561 		cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);  in evergreen_irq_set()
4569 	if (rdev->family >= CHIP_CAYMAN)  in evergreen_irq_set()
4574 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_irq_set()
4578 		    rdev->irq.crtc_vblank_int[i] ||  in evergreen_irq_set()
4579 		    atomic_read(&rdev->irq.pflip[i]), "vblank", i);  in evergreen_irq_set()
4582 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_irq_set()
4585 	for (i = 0; i < 6; i++) {  in evergreen_irq_set()
4589 		    rdev->irq.hpd[i], "HPD", i);  in evergreen_irq_set()
4592 	if (rdev->family == CHIP_ARUBA)  in evergreen_irq_set()
4597 	for (i = 0; i < 6; i++) {  in evergreen_irq_set()
4601 		    rdev->irq.afmt[i], "HDMI", i);  in evergreen_irq_set()
4607 	return 0;  in evergreen_irq_set()
4614 	u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;  in evergreen_irq_ack()
4615 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;  in evergreen_irq_ack()
4616 	u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;  in evergreen_irq_ack()
4618 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4621 		if (i < rdev->num_crtc)  in evergreen_irq_ack()
4626 	for (i = 0; i < rdev->num_crtc; i += 2) {  in evergreen_irq_ack()
4643 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4648 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4653 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4679 	if (rdev->wb.enabled)  in evergreen_get_ih_wptr()
4680 		wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);  in evergreen_get_ih_wptr()
4690 		dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in evergreen_get_ih_wptr()
4691 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);  in evergreen_get_ih_wptr()
4692 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;  in evergreen_get_ih_wptr()
4697 	return (wptr & rdev->ih.ptr_mask);  in evergreen_get_ih_wptr()
4702 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;  in evergreen_irq_process()
4703 	u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;  in evergreen_irq_process()
4717 	if (!rdev->ih.enabled || rdev->shutdown)  in evergreen_irq_process()
4724 	if (atomic_xchg(&rdev->ih.lock, 1))  in evergreen_irq_process()
4727 	rptr = rdev->ih.rptr;  in evergreen_irq_process()
4739 		src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;  in evergreen_irq_process()
4740 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;  in evergreen_irq_process()
4749 			crtc_idx = src_id - 1;  in evergreen_irq_process()
4751 			if (src_data == 0) { /* vblank */  in evergreen_irq_process()
4755 				if (rdev->irq.crtc_vblank_int[crtc_idx]) {  in evergreen_irq_process()
4757 					rdev->pm.vblank_sync = true;  in evergreen_irq_process()
4758 					wake_up(&rdev->irq.vblank_queue);  in evergreen_irq_process()
4760 				if (atomic_read(&rdev->irq.pflip[crtc_idx])) {  in evergreen_irq_process()
4775 				DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n",  in evergreen_irq_process()
4789 			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);  in evergreen_irq_process()
4790 			if (radeon_use_pflipirq > 0)  in evergreen_irq_process()
4791 				radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);  in evergreen_irq_process()
4801 				hpd_idx = src_data - 6;  in evergreen_irq_process()
4835 			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));  in evergreen_irq_process()
4836 			WREG32(SRBM_INT_ACK, 0x1);  in evergreen_irq_process()
4839 			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);  in evergreen_irq_process()
4848 			if (addr == 0x0 && status == 0x0)  in evergreen_irq_process()
4850 			dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);  in evergreen_irq_process()
4851 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",  in evergreen_irq_process()
4853 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",  in evergreen_irq_process()
4860 			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);  in evergreen_irq_process()
4865 			if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_process()
4867 				case 0:  in evergreen_irq_process()
4886 			rdev->pm.dpm.thermal.high_to_low = false;  in evergreen_irq_process()
4891 			rdev->pm.dpm.thermal.high_to_low = true;  in evergreen_irq_process()
4898 			if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_process()
4910 		rptr &= rdev->ih.ptr_mask;  in evergreen_irq_process()
4914 		schedule_work(&rdev->dp_work);  in evergreen_irq_process()
4916 		schedule_delayed_work(&rdev->hotplug_work, 0);  in evergreen_irq_process()
4918 		schedule_work(&rdev->audio_work);  in evergreen_irq_process()
4919 	if (queue_thermal && rdev->pm.dpm_enabled)  in evergreen_irq_process()
4920 		schedule_work(&rdev->pm.dpm.thermal.work);  in evergreen_irq_process()
4921 	rdev->ih.rptr = rptr;  in evergreen_irq_process()
4922 	atomic_set(&rdev->ih.lock, 0);  in evergreen_irq_process()
4936 	if (!rdev->has_uvd)  in evergreen_uvd_init()
4941 		dev_err(rdev->dev, "failed UVD (%d) init.\n", r);  in evergreen_uvd_init()
4943 		 * At this point rdev->uvd.vcpu_bo is NULL which trickles down  in evergreen_uvd_init()
4948 		rdev->has_uvd = false;  in evergreen_uvd_init()
4951 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;  in evergreen_uvd_init()
4952 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);  in evergreen_uvd_init()
4959 	if (!rdev->has_uvd)  in evergreen_uvd_start()
4964 		dev_err(rdev->dev, "failed UVD resume (%d).\n", r);  in evergreen_uvd_start()
4969 		dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);  in evergreen_uvd_start()
4975 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;  in evergreen_uvd_start()
4983 	if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)  in evergreen_uvd_resume()
4986 	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in evergreen_uvd_resume()
4987 	r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));  in evergreen_uvd_resume()
4989 		dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);  in evergreen_uvd_resume()
4994 		dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);  in evergreen_uvd_resume()
5016 	if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {  in evergreen_startup()
5024 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_startup()
5034 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_startup()
5035 		rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;  in evergreen_startup()
5036 		rdev->rlc.reg_list_size =  in evergreen_startup()
5038 		rdev->rlc.cs_data = evergreen_cs_data;  in evergreen_startup()
5053 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in evergreen_startup()
5059 		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);  in evergreen_startup()
5066 	if (!rdev->irq.installed) {  in evergreen_startup()
5080 	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_startup()
5081 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,  in evergreen_startup()
5086 	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];  in evergreen_startup()
5087 	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,  in evergreen_startup()
5088 			     DMA_PACKET(DMA_PACKET_NOP, 0, 0));  in evergreen_startup()
5106 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in evergreen_startup()
5116 	return 0;  in evergreen_startup()
5127 		dev_warn(rdev->dev, "GPU reset failed !\n");  in evergreen_resume()
5133 	atom_asic_init(rdev->mode_info.atom_context);  in evergreen_resume()
5138 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in evergreen_resume()
5141 	rdev->accel_working = true;  in evergreen_resume()
5145 		rdev->accel_working = false;  in evergreen_resume()
5157 	if (rdev->has_uvd) {  in evergreen_suspend()
5167 	return 0;  in evergreen_suspend()
5183 			return -EINVAL;  in evergreen_init()
5186 	if (!rdev->is_atom_bios) {  in evergreen_init()
5187 		dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");  in evergreen_init()
5188 		return -EINVAL;  in evergreen_init()
5197 		dev_warn(rdev->dev, "GPU reset failed !\n");  in evergreen_init()
5200 		if (!rdev->bios) {  in evergreen_init()
5201 			dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");  in evergreen_init()
5202 			return -EINVAL;  in evergreen_init()
5205 		atom_asic_init(rdev->mode_info.atom_context);  in evergreen_init()
5218 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_init()
5233 		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {  in evergreen_init()
5241 		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {  in evergreen_init()
5253 	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;  in evergreen_init()
5254 	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);  in evergreen_init()
5256 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;  in evergreen_init()
5257 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);  in evergreen_init()
5261 	rdev->ih.ring_obj = NULL;  in evergreen_init()
5268 	rdev->accel_working = true;  in evergreen_init()
5271 		dev_err(rdev->dev, "disabling GPU acceleration\n");  in evergreen_init()
5275 		if (rdev->flags & RADEON_IS_IGP)  in evergreen_init()
5281 		rdev->accel_working = false;  in evergreen_init()
5289 		if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {  in evergreen_init()
5291 			return -EINVAL;  in evergreen_init()
5295 	return 0;  in evergreen_init()
5305 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_fini()
5319 	kfree(rdev->bios);  in evergreen_fini()
5320 	rdev->bios = NULL;  in evergreen_fini()
5327 	if (radeon_pcie_gen2 == 0)  in evergreen_pcie_gen2_enable()
5330 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_pcie_gen2_enable()
5333 	if (!(rdev->flags & RADEON_IS_PCIE))  in evergreen_pcie_gen2_enable()
5340 	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&  in evergreen_pcie_gen2_enable()
5341 		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))  in evergreen_pcie_gen2_enable()
5350 	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");  in evergreen_pcie_gen2_enable()
5377 		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */  in evergreen_pcie_gen2_enable()
5398 	if (radeon_aspm == 0)  in evergreen_program_aspm()
5401 	if (!(rdev->flags & RADEON_IS_PCIE))  in evergreen_program_aspm()
5404 	switch (rdev->family) {  in evergreen_program_aspm()
5421 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_program_aspm()
5443 		if (rdev->family >= CHIP_BARTS)  in evergreen_program_aspm()
5450 		if (rdev->family >= CHIP_BARTS)  in evergreen_program_aspm()
5480 			if (rdev->family >= CHIP_BARTS) {  in evergreen_program_aspm()
5512 			if (rdev->family >= CHIP_BARTS) {  in evergreen_program_aspm()
5529 	if (rdev->family < CHIP_BARTS)  in evergreen_program_aspm()