Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x07ffffff
52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
70 0x98fc,
71 0x98f0,
72 0x9834,
73 0x9838,
74 0x9870,
75 0x9874,
76 0x8a14,
77 0x8b24,
78 0x8bcc,
79 0x8b10,
80 0x8c30,
81 0x8d00,
82 0x8d04,
83 0x8c00,
84 0x8c04,
85 0x8c10,
86 0x8c14,
87 0x8d8c,
88 0x8cf0,
89 0x8e38,
90 0x9508,
91 0x9688,
92 0x9608,
93 0x960c,
94 0x9610,
95 0x9614,
96 0x88c4,
97 0x8978,
98 0x88d4,
99 0x900c,
100 0x9100,
101 0x913c,
102 0x90e8,
103 0x9354,
104 0xa008,
105 0x98f8,
106 0x9148,
107 0x914c,
108 0x3f94,
109 0x98f4,
110 0x9b7c,
111 0x3f8c,
112 0x8950,
113 0x8954,
114 0x8a18,
115 0x8b28,
116 0x9144,
117 0x3f90,
118 0x915c,
119 0x9160,
120 0x9178,
121 0x917c,
122 0x9180,
123 0x918c,
124 0x9190,
125 0x9194,
126 0x9198,
127 0x919c,
128 0x91a8,
129 0x91ac,
130 0x91b0,
131 0x91b4,
132 0x91b8,
133 0x91c4,
134 0x91c8,
135 0x91cc,
136 0x91d0,
137 0x91d4,
138 0x91e0,
139 0x91e4,
140 0x91ec,
141 0x91f0,
142 0x91f4,
143 0x9200,
144 0x9204,
145 0x929c,
146 0x8030,
147 0x9150,
148 0x9a60,
149 0x920c,
150 0x9210,
151 0x9228,
152 0x922c,
153 0x9244,
154 0x9248,
155 0x91e8,
156 0x9294,
157 0x9208,
158 0x9224,
159 0x9240,
160 0x9220,
161 0x923c,
162 0x9258,
163 0x9744,
164 0xa200,
165 0xa204,
166 0xa208,
167 0xa20c,
168 0x8d58,
169 0x9030,
170 0x9034,
171 0x9038,
172 0x903c,
173 0x9040,
174 0x9654,
175 0x897c,
176 0xa210,
177 0xa214,
178 0x9868,
179 0xa02c,
180 0x9664,
181 0x9698,
182 0x949c,
183 0x8e10,
184 0x8e18,
185 0x8c50,
186 0x8c58,
187 0x8c60,
188 0x8c68,
189 0x89b4,
190 0x9830,
191 0x802c,
219 0x3e5c, 0xffffffff, 0x00000000,
220 0x3e48, 0xffffffff, 0x00000000,
221 0x3e4c, 0xffffffff, 0x00000000,
222 0x3e64, 0xffffffff, 0x00000000,
223 0x3e50, 0xffffffff, 0x00000000,
224 0x3e60, 0xffffffff, 0x00000000
228 0x5eb4, 0xffffffff, 0x00000002,
229 0x5e78, 0x8f311ff1, 0x001000f0,
230 0x3f90, 0xffff0000, 0xff000000,
231 0x9148, 0xffff0000, 0xff000000,
232 0x3f94, 0xffff0000, 0xff000000,
233 0x914c, 0xffff0000, 0xff000000,
234 0xc78, 0x00000080, 0x00000080,
235 0xbd4, 0x70073777, 0x00011003,
236 0xd02c, 0xbfffff1f, 0x08421000,
237 0xd0b8, 0x73773777, 0x02011003,
238 0x5bc0, 0x00200000, 0x50100000,
239 0x98f8, 0x33773777, 0x02011003,
240 0x98fc, 0xffffffff, 0x76541032,
241 0x7030, 0x31000311, 0x00000011,
242 0x2f48, 0x33773777, 0x42010001,
243 0x6b28, 0x00000010, 0x00000012,
244 0x7728, 0x00000010, 0x00000012,
245 0x10328, 0x00000010, 0x00000012,
246 0x10f28, 0x00000010, 0x00000012,
247 0x11b28, 0x00000010, 0x00000012,
248 0x12728, 0x00000010, 0x00000012,
249 0x240c, 0x000007ff, 0x00000000,
250 0x8a14, 0xf000001f, 0x00000007,
251 0x8b24, 0x3fff3fff, 0x00ff0fff,
252 0x8b10, 0x0000ff0f, 0x00000000,
253 0x28a4c, 0x07ffffff, 0x06000000,
254 0x10c, 0x00000001, 0x00010003,
255 0xa02c, 0xffffffff, 0x0000009b,
256 0x913c, 0x0000010f, 0x01000100,
257 0x8c04, 0xf8ff00ff, 0x40600060,
258 0x28350, 0x00000f01, 0x00000000,
259 0x9508, 0x3700001f, 0x00000002,
260 0x960c, 0xffffffff, 0x54763210,
261 0x88c4, 0x001f3ae3, 0x00000082,
262 0x88d0, 0xffffffff, 0x0f40df40,
263 0x88d4, 0x0000001f, 0x00000010,
264 0x8974, 0xffffffff, 0x00000000
268 0x8f8, 0xffffffff, 0,
269 0x8fc, 0x00380000, 0,
270 0x8f8, 0xffffffff, 1,
271 0x8fc, 0x0e000000, 0
275 0x690, 0x3fff3fff, 0x20c00033,
276 0x918c, 0x0fff0fff, 0x00010006,
277 0x91a8, 0x0fff0fff, 0x00010006,
278 0x9150, 0xffffdfff, 0x6e944040,
279 0x917c, 0x0fff0fff, 0x00030002,
280 0x9198, 0x0fff0fff, 0x00030002,
281 0x915c, 0x0fff0fff, 0x00010000,
282 0x3f90, 0xffff0001, 0xff000000,
283 0x9178, 0x0fff0fff, 0x00070000,
284 0x9194, 0x0fff0fff, 0x00070000,
285 0x9148, 0xffff0001, 0xff000000,
286 0x9190, 0x0fff0fff, 0x00090008,
287 0x91ac, 0x0fff0fff, 0x00090008,
288 0x3f94, 0xffff0000, 0xff000000,
289 0x914c, 0xffff0000, 0xff000000,
290 0x929c, 0x00000fff, 0x00000001,
291 0x55e4, 0xff607fff, 0xfc000100,
292 0x8a18, 0xff000fff, 0x00000100,
293 0x8b28, 0xff000fff, 0x00000100,
294 0x9144, 0xfffc0fff, 0x00000100,
295 0x6ed8, 0x00010101, 0x00010000,
296 0x9830, 0xffffffff, 0x00000000,
297 0x9834, 0xf00fffff, 0x00000400,
298 0x9838, 0xfffffffe, 0x00000000,
299 0xd0c0, 0xff000fff, 0x00000100,
300 0xd02c, 0xbfffff1f, 0x08421000,
301 0xd0b8, 0x73773777, 0x12010001,
302 0x5bb0, 0x000000f0, 0x00000070,
303 0x98f8, 0x73773777, 0x12010001,
304 0x98fc, 0xffffffff, 0x00000010,
305 0x9b7c, 0x00ff0000, 0x00fc0000,
306 0x8030, 0x00001f0f, 0x0000100a,
307 0x2f48, 0x73773777, 0x12010001,
308 0x2408, 0x00030000, 0x000c007f,
309 0x8a14, 0xf000003f, 0x00000007,
310 0x8b24, 0x3fff3fff, 0x00ff0fff,
311 0x8b10, 0x0000ff0f, 0x00000000,
312 0x28a4c, 0x07ffffff, 0x06000000,
313 0x4d8, 0x00000fff, 0x00000100,
314 0xa008, 0xffffffff, 0x00010000,
315 0x913c, 0xffff03ff, 0x01000100,
316 0x8c00, 0x000000ff, 0x00000003,
317 0x8c04, 0xf8ff00ff, 0x40600060,
318 0x8cf0, 0x1fff1fff, 0x08e00410,
319 0x28350, 0x00000f01, 0x00000000,
320 0x9508, 0xf700071f, 0x00000002,
321 0x960c, 0xffffffff, 0x54763210,
322 0x20ef8, 0x01ff01ff, 0x00000002,
323 0x20e98, 0xfffffbff, 0x00200000,
324 0x2015c, 0xffffffff, 0x00000f40,
325 0x88c4, 0x001f3ae3, 0x00000082,
326 0x8978, 0x3fffffff, 0x04050140,
327 0x88d4, 0x0000001f, 0x00000010,
328 0x8974, 0xffffffff, 0x00000000
332 0x690, 0x3fff3fff, 0x20c00033,
333 0x918c, 0x0fff0fff, 0x00010006,
334 0x918c, 0x0fff0fff, 0x00010006,
335 0x91a8, 0x0fff0fff, 0x00010006,
336 0x91a8, 0x0fff0fff, 0x00010006,
337 0x9150, 0xffffdfff, 0x6e944040,
338 0x9150, 0xffffdfff, 0x6e944040,
339 0x917c, 0x0fff0fff, 0x00030002,
340 0x917c, 0x0fff0fff, 0x00030002,
341 0x9198, 0x0fff0fff, 0x00030002,
342 0x9198, 0x0fff0fff, 0x00030002,
343 0x915c, 0x0fff0fff, 0x00010000,
344 0x915c, 0x0fff0fff, 0x00010000,
345 0x3f90, 0xffff0001, 0xff000000,
346 0x3f90, 0xffff0001, 0xff000000,
347 0x9178, 0x0fff0fff, 0x00070000,
348 0x9178, 0x0fff0fff, 0x00070000,
349 0x9194, 0x0fff0fff, 0x00070000,
350 0x9194, 0x0fff0fff, 0x00070000,
351 0x9148, 0xffff0001, 0xff000000,
352 0x9148, 0xffff0001, 0xff000000,
353 0x9190, 0x0fff0fff, 0x00090008,
354 0x9190, 0x0fff0fff, 0x00090008,
355 0x91ac, 0x0fff0fff, 0x00090008,
356 0x91ac, 0x0fff0fff, 0x00090008,
357 0x3f94, 0xffff0000, 0xff000000,
358 0x3f94, 0xffff0000, 0xff000000,
359 0x914c, 0xffff0000, 0xff000000,
360 0x914c, 0xffff0000, 0xff000000,
361 0x929c, 0x00000fff, 0x00000001,
362 0x929c, 0x00000fff, 0x00000001,
363 0x55e4, 0xff607fff, 0xfc000100,
364 0x8a18, 0xff000fff, 0x00000100,
365 0x8a18, 0xff000fff, 0x00000100,
366 0x8b28, 0xff000fff, 0x00000100,
367 0x8b28, 0xff000fff, 0x00000100,
368 0x9144, 0xfffc0fff, 0x00000100,
369 0x9144, 0xfffc0fff, 0x00000100,
370 0x6ed8, 0x00010101, 0x00010000,
371 0x9830, 0xffffffff, 0x00000000,
372 0x9830, 0xffffffff, 0x00000000,
373 0x9834, 0xf00fffff, 0x00000400,
374 0x9834, 0xf00fffff, 0x00000400,
375 0x9838, 0xfffffffe, 0x00000000,
376 0x9838, 0xfffffffe, 0x00000000,
377 0xd0c0, 0xff000fff, 0x00000100,
378 0xd02c, 0xbfffff1f, 0x08421000,
379 0xd02c, 0xbfffff1f, 0x08421000,
380 0xd0b8, 0x73773777, 0x12010001,
381 0xd0b8, 0x73773777, 0x12010001,
382 0x5bb0, 0x000000f0, 0x00000070,
383 0x98f8, 0x73773777, 0x12010001,
384 0x98f8, 0x73773777, 0x12010001,
385 0x98fc, 0xffffffff, 0x00000010,
386 0x98fc, 0xffffffff, 0x00000010,
387 0x9b7c, 0x00ff0000, 0x00fc0000,
388 0x9b7c, 0x00ff0000, 0x00fc0000,
389 0x8030, 0x00001f0f, 0x0000100a,
390 0x8030, 0x00001f0f, 0x0000100a,
391 0x2f48, 0x73773777, 0x12010001,
392 0x2f48, 0x73773777, 0x12010001,
393 0x2408, 0x00030000, 0x000c007f,
394 0x8a14, 0xf000003f, 0x00000007,
395 0x8a14, 0xf000003f, 0x00000007,
396 0x8b24, 0x3fff3fff, 0x00ff0fff,
397 0x8b24, 0x3fff3fff, 0x00ff0fff,
398 0x8b10, 0x0000ff0f, 0x00000000,
399 0x8b10, 0x0000ff0f, 0x00000000,
400 0x28a4c, 0x07ffffff, 0x06000000,
401 0x28a4c, 0x07ffffff, 0x06000000,
402 0x4d8, 0x00000fff, 0x00000100,
403 0x4d8, 0x00000fff, 0x00000100,
404 0xa008, 0xffffffff, 0x00010000,
405 0xa008, 0xffffffff, 0x00010000,
406 0x913c, 0xffff03ff, 0x01000100,
407 0x913c, 0xffff03ff, 0x01000100,
408 0x90e8, 0x001fffff, 0x010400c0,
409 0x8c00, 0x000000ff, 0x00000003,
410 0x8c00, 0x000000ff, 0x00000003,
411 0x8c04, 0xf8ff00ff, 0x40600060,
412 0x8c04, 0xf8ff00ff, 0x40600060,
413 0x8c30, 0x0000000f, 0x00040005,
414 0x8cf0, 0x1fff1fff, 0x08e00410,
415 0x8cf0, 0x1fff1fff, 0x08e00410,
416 0x900c, 0x00ffffff, 0x0017071f,
417 0x28350, 0x00000f01, 0x00000000,
418 0x28350, 0x00000f01, 0x00000000,
419 0x9508, 0xf700071f, 0x00000002,
420 0x9508, 0xf700071f, 0x00000002,
421 0x9688, 0x00300000, 0x0017000f,
422 0x960c, 0xffffffff, 0x54763210,
423 0x960c, 0xffffffff, 0x54763210,
424 0x20ef8, 0x01ff01ff, 0x00000002,
425 0x20e98, 0xfffffbff, 0x00200000,
426 0x2015c, 0xffffffff, 0x00000f40,
427 0x88c4, 0x001f3ae3, 0x00000082,
428 0x88c4, 0x001f3ae3, 0x00000082,
429 0x8978, 0x3fffffff, 0x04050140,
430 0x8978, 0x3fffffff, 0x04050140,
431 0x88d4, 0x0000001f, 0x00000010,
432 0x88d4, 0x0000001f, 0x00000010,
433 0x8974, 0xffffffff, 0x00000000,
434 0x8974, 0xffffffff, 0x00000000
439 switch (rdev->family) { in ni_init_golden_registers()
449 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
450 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
451 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
452 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
453 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
454 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
455 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
456 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
457 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
458 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
459 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
460 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
461 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
462 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
463 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
464 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
465 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
466 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
467 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
491 {0x00000077, 0xff010100},
492 {0x00000078, 0x00000000},
493 {0x00000079, 0x00001434},
494 {0x0000007a, 0xcc08ec08},
495 {0x0000007b, 0x00040000},
496 {0x0000007c, 0x000080c0},
497 {0x0000007d, 0x09000000},
498 {0x0000007e, 0x00210404},
499 {0x00000081, 0x08a8e800},
500 {0x00000082, 0x00030444},
501 {0x00000083, 0x00000000},
502 {0x00000085, 0x00000001},
503 {0x00000086, 0x00000002},
504 {0x00000087, 0x48490000},
505 {0x00000088, 0x20244647},
506 {0x00000089, 0x00000005},
507 {0x0000008b, 0x66030000},
508 {0x0000008c, 0x00006603},
509 {0x0000008d, 0x00000100},
510 {0x0000008f, 0x00001c0a},
511 {0x00000090, 0xff000001},
512 {0x00000094, 0x00101101},
513 {0x00000095, 0x00000fff},
514 {0x00000096, 0x00116fff},
515 {0x00000097, 0x60010000},
516 {0x00000098, 0x10010000},
517 {0x00000099, 0x00006000},
518 {0x0000009a, 0x00001000},
519 {0x0000009f, 0x00946a00}
523 {0x00000077, 0xff010100},
524 {0x00000078, 0x00000000},
525 {0x00000079, 0x00001434},
526 {0x0000007a, 0xcc08ec08},
527 {0x0000007b, 0x00040000},
528 {0x0000007c, 0x000080c0},
529 {0x0000007d, 0x09000000},
530 {0x0000007e, 0x00210404},
531 {0x00000081, 0x08a8e800},
532 {0x00000082, 0x00030444},
533 {0x00000083, 0x00000000},
534 {0x00000085, 0x00000001},
535 {0x00000086, 0x00000002},
536 {0x00000087, 0x48490000},
537 {0x00000088, 0x20244647},
538 {0x00000089, 0x00000005},
539 {0x0000008b, 0x66030000},
540 {0x0000008c, 0x00006603},
541 {0x0000008d, 0x00000100},
542 {0x0000008f, 0x00001c0a},
543 {0x00000090, 0xff000001},
544 {0x00000094, 0x00101101},
545 {0x00000095, 0x00000fff},
546 {0x00000096, 0x00116fff},
547 {0x00000097, 0x60010000},
548 {0x00000098, 0x10010000},
549 {0x00000099, 0x00006000},
550 {0x0000009a, 0x00001000},
551 {0x0000009f, 0x00936a00}
555 {0x00000077, 0xff010100},
556 {0x00000078, 0x00000000},
557 {0x00000079, 0x00001434},
558 {0x0000007a, 0xcc08ec08},
559 {0x0000007b, 0x00040000},
560 {0x0000007c, 0x000080c0},
561 {0x0000007d, 0x09000000},
562 {0x0000007e, 0x00210404},
563 {0x00000081, 0x08a8e800},
564 {0x00000082, 0x00030444},
565 {0x00000083, 0x00000000},
566 {0x00000085, 0x00000001},
567 {0x00000086, 0x00000002},
568 {0x00000087, 0x48490000},
569 {0x00000088, 0x20244647},
570 {0x00000089, 0x00000005},
571 {0x0000008b, 0x66030000},
572 {0x0000008c, 0x00006603},
573 {0x0000008d, 0x00000100},
574 {0x0000008f, 0x00001c0a},
575 {0x00000090, 0xff000001},
576 {0x00000094, 0x00101101},
577 {0x00000095, 0x00000fff},
578 {0x00000096, 0x00116fff},
579 {0x00000097, 0x60010000},
580 {0x00000098, 0x10010000},
581 {0x00000099, 0x00006000},
582 {0x0000009a, 0x00001000},
583 {0x0000009f, 0x00916a00}
587 {0x00000077, 0xff010100},
588 {0x00000078, 0x00000000},
589 {0x00000079, 0x00001434},
590 {0x0000007a, 0xcc08ec08},
591 {0x0000007b, 0x00040000},
592 {0x0000007c, 0x000080c0},
593 {0x0000007d, 0x09000000},
594 {0x0000007e, 0x00210404},
595 {0x00000081, 0x08a8e800},
596 {0x00000082, 0x00030444},
597 {0x00000083, 0x00000000},
598 {0x00000085, 0x00000001},
599 {0x00000086, 0x00000002},
600 {0x00000087, 0x48490000},
601 {0x00000088, 0x20244647},
602 {0x00000089, 0x00000005},
603 {0x0000008b, 0x66030000},
604 {0x0000008c, 0x00006603},
605 {0x0000008d, 0x00000100},
606 {0x0000008f, 0x00001c0a},
607 {0x00000090, 0xff000001},
608 {0x00000094, 0x00101101},
609 {0x00000095, 0x00000fff},
610 {0x00000096, 0x00116fff},
611 {0x00000097, 0x60010000},
612 {0x00000098, 0x10010000},
613 {0x00000099, 0x00006000},
614 {0x0000009a, 0x00001000},
615 {0x0000009f, 0x00976b00}
625 if (!rdev->mc_fw) in ni_mc_load_microcode()
626 return -EINVAL; in ni_mc_load_microcode()
628 switch (rdev->family) { in ni_mc_load_microcode()
655 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { in ni_mc_load_microcode()
657 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
658 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
661 for (i = 0; i < regs_size; i++) { in ni_mc_load_microcode()
666 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
667 for (i = 0; i < ucode_size; i++) in ni_mc_load_microcode()
671 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
672 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ni_mc_load_microcode()
673 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ni_mc_load_microcode()
676 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
683 return 0; in ni_mc_load_microcode()
691 size_t smc_req_size = 0; in ni_init_microcode()
697 switch (rdev->family) { in ni_init_microcode()
741 mc_req_size = 0; in ni_init_microcode()
750 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
753 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
755 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
756 err = -EINVAL; in ni_init_microcode()
761 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
764 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
766 rdev->me_fw->size, fw_name); in ni_init_microcode()
767 err = -EINVAL; in ni_init_microcode()
771 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
774 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
776 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
777 err = -EINVAL; in ni_init_microcode()
781 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
786 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
788 rdev->mc_fw->size, fw_name); in ni_init_microcode()
789 err = -EINVAL; in ni_init_microcode()
793 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
795 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
798 release_firmware(rdev->smc_fw); in ni_init_microcode()
799 rdev->smc_fw = NULL; in ni_init_microcode()
800 err = 0; in ni_init_microcode()
801 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
803 rdev->smc_fw->size, fw_name); in ni_init_microcode()
804 err = -EINVAL; in ni_init_microcode()
810 if (err != -EINVAL) in ni_init_microcode()
813 release_firmware(rdev->pfp_fw); in ni_init_microcode()
814 rdev->pfp_fw = NULL; in ni_init_microcode()
815 release_firmware(rdev->me_fw); in ni_init_microcode()
816 rdev->me_fw = NULL; in ni_init_microcode()
817 release_firmware(rdev->rlc_fw); in ni_init_microcode()
818 rdev->rlc_fw = NULL; in ni_init_microcode()
819 release_firmware(rdev->mc_fw); in ni_init_microcode()
820 rdev->mc_fw = NULL; in ni_init_microcode()
826 * cayman_get_allowed_info_register - fetch the register for the info ioctl
832 * Returns 0 for success or -EINVAL for an invalid register
848 return 0; in cayman_get_allowed_info_register()
850 return -EINVAL; in cayman_get_allowed_info_register()
856 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
857 int actual_temp = (temp / 8) - 49; in tn_get_temp()
867 u32 gb_addr_config = 0; in cayman_gpu_init()
878 switch (rdev->family) { in cayman_gpu_init()
880 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
881 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
882 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
883 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
884 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
885 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
886 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
887 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
888 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
889 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
890 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
891 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
892 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
893 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
894 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
895 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
897 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
898 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
899 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
904 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
905 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
906 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
907 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
908 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
909 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
910 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
911 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
912 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
913 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
914 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
915 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
916 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
917 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
918 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
919 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
920 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
921 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
922 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
923 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
924 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
925 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
926 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
927 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
928 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
929 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
930 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
931 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
932 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
933 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
934 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
935 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
936 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
937 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
938 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
939 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
940 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
941 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
944 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
945 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
946 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
947 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
948 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
949 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
950 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
951 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
952 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
953 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
954 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
956 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
957 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
958 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
959 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
960 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
961 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
963 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
964 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
965 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
966 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
967 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
968 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
969 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
971 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
972 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
973 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
979 for (i = 0, j = 0; i < 32; i++, j += 0x18) { in cayman_gpu_init()
980 WREG32((0x2c14 + j), 0x00000000); in cayman_gpu_init()
981 WREG32((0x2c18 + j), 0x00000000); in cayman_gpu_init()
982 WREG32((0x2c1c + j), 0x00000000); in cayman_gpu_init()
983 WREG32((0x2c20 + j), 0x00000000); in cayman_gpu_init()
984 WREG32((0x2c24 + j), 0x00000000); in cayman_gpu_init()
987 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cayman_gpu_init()
988 WREG32(SRBM_INT_CNTL, 0x1); in cayman_gpu_init()
989 WREG32(SRBM_INT_ACK, 0x1); in cayman_gpu_init()
997 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
998 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
999 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1001 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1002 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1003 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1006 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1008 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1010 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1012 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1014 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1016 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1021 * bits 3:0 num_pipes in cayman_gpu_init()
1026 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1027 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1030 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1033 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1036 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1039 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1043 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ in cayman_gpu_init()
1044 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1045 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1048 case 0: /* four banks */ in cayman_gpu_init()
1049 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1052 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1056 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1060 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1062 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1065 tmp = 0; in cayman_gpu_init()
1066 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1071 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in cayman_gpu_init()
1077 tmp = 0; in cayman_gpu_init()
1078 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1082 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1086 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1091 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in cayman_gpu_init()
1092 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1096 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1112 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1113 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1116 tmp = 0x00000000; in cayman_gpu_init()
1119 tmp = 0x11111111; in cayman_gpu_init()
1124 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1125 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1128 rdev->config.cayman.backend_map = tmp; in cayman_gpu_init()
1131 cgts_tcc_disable = 0xffff0000; in cayman_gpu_init()
1132 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1141 for (i = 0; i < 16; i++) in cayman_gpu_init()
1146 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cayman_gpu_init()
1153 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); in cayman_gpu_init()
1154 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1159 /* need to be explicitly zero-ed */ in cayman_gpu_init()
1160 WREG32(VGT_OFFCHIP_LDS_BASE, 0); in cayman_gpu_init()
1161 WREG32(SQ_LSTMP_RING_BASE, 0); in cayman_gpu_init()
1162 WREG32(SQ_HSTMP_RING_BASE, 0); in cayman_gpu_init()
1163 WREG32(SQ_ESTMP_RING_BASE, 0); in cayman_gpu_init()
1164 WREG32(SQ_GSTMP_RING_BASE, 0); in cayman_gpu_init()
1165 WREG32(SQ_VSTMP_RING_BASE, 0); in cayman_gpu_init()
1166 WREG32(SQ_PSTMP_RING_BASE, 0); in cayman_gpu_init()
1170 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1171 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1172 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1174 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1175 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1176 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1181 WREG32(CP_PERFMON_CNTL, 0); in cayman_gpu_init()
1183 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1184 FETCH_FIFO_HIWATER(0x4) | in cayman_gpu_init()
1185 DONE_FIFO_HIWATER(0xe0) | in cayman_gpu_init()
1186 ALU_UPDATE_FIFO_HIWATER(0x8))); in cayman_gpu_init()
1191 GFX_PRIO(0) | in cayman_gpu_init()
1192 CS1_PRIO(0) | in cayman_gpu_init()
1203 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cayman_gpu_init()
1205 WREG32(CB_PERF_CTR0_SEL_0, 0); in cayman_gpu_init()
1206 WREG32(CB_PERF_CTR0_SEL_1, 0); in cayman_gpu_init()
1207 WREG32(CB_PERF_CTR1_SEL_0, 0); in cayman_gpu_init()
1208 WREG32(CB_PERF_CTR1_SEL_1, 0); in cayman_gpu_init()
1209 WREG32(CB_PERF_CTR2_SEL_0, 0); in cayman_gpu_init()
1210 WREG32(CB_PERF_CTR2_SEL_1, 0); in cayman_gpu_init()
1211 WREG32(CB_PERF_CTR3_SEL_0, 0); in cayman_gpu_init()
1212 WREG32(CB_PERF_CTR3_SEL_1, 0); in cayman_gpu_init()
1226 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1228 tmp &= ~0x00380000; in cayman_gpu_init()
1231 tmp &= ~0x0e000000; in cayman_gpu_init()
1242 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in cayman_pcie_gart_tlb_flush()
1244 /* bits 0-7 are the VM contexts0-7 */ in cayman_pcie_gart_tlb_flush()
1252 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1253 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1254 return -EINVAL; in cayman_pcie_gart_enable()
1261 (0xA << 7) | in cayman_pcie_gart_enable()
1279 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1283 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1284 WREG32(VM_CONTEXT0_CNTL2, 0); in cayman_pcie_gart_enable()
1285 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1288 WREG32(0x15D4, 0); in cayman_pcie_gart_enable()
1289 WREG32(0x15D8, 0); in cayman_pcie_gart_enable()
1290 WREG32(0x15DC, 0); in cayman_pcie_gart_enable()
1292 /* empty context1-7 */ in cayman_pcie_gart_enable()
1298 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); in cayman_pcie_gart_enable()
1300 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1302 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1305 /* enable context1-7 */ in cayman_pcie_gart_enable()
1307 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1310 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | in cayman_pcie_gart_enable()
1325 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in cayman_pcie_gart_enable()
1326 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1327 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1328 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1329 return 0; in cayman_pcie_gart_enable()
1337 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1342 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
1343 WREG32(VM_CONTEXT1_CNTL, 0); in cayman_pcie_gart_disable()
1353 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
1379 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit()
1380 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1387 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1388 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1390 /* EVENT_WRITE_EOP - flush caches, send int */ in cayman_fence_ring_emit()
1394 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1395 radeon_ring_write(ring, fence->seq); in cayman_fence_ring_emit()
1396 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1401 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute()
1402 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cayman_ring_ib_execute()
1407 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1410 if (ring->rptr_save_reg) { in cayman_ring_ib_execute()
1411 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; in cayman_ring_ib_execute()
1413 radeon_ring_write(ring, ((ring->rptr_save_reg - in cayman_ring_ib_execute()
1421 (2 << 0) | in cayman_ring_ib_execute()
1423 (ib->gpu_addr & 0xFFFFFFFC)); in cayman_ring_ib_execute()
1424 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1425 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in cayman_ring_ib_execute()
1430 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_ring_ib_execute()
1431 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1440 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1441 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1443 WREG32(SCRATCH_UMSK, 0); in cayman_cp_enable()
1444 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1453 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1454 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1456 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_rptr()
1458 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_rptr()
1472 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_wptr()
1474 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_wptr()
1485 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cayman_gfx_set_wptr()
1486 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1488 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { in cayman_gfx_set_wptr()
1489 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1492 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1502 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1503 return -EINVAL; in cayman_cp_load_microcode()
1507 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1508 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1509 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) in cayman_cp_load_microcode()
1511 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1513 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1514 WREG32(CP_ME_RAM_WADDR, 0); in cayman_cp_load_microcode()
1515 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) in cayman_cp_load_microcode()
1518 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1519 WREG32(CP_ME_RAM_WADDR, 0); in cayman_cp_load_microcode()
1520 WREG32(CP_ME_RAM_RADDR, 0); in cayman_cp_load_microcode()
1521 return 0; in cayman_cp_load_microcode()
1526 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1535 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1536 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1537 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1539 radeon_ring_write(ring, 0); in cayman_cp_start()
1540 radeon_ring_write(ring, 0); in cayman_cp_start()
1552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1555 for (i = 0; i < cayman_default_size; i++) in cayman_cp_start()
1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1562 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
1563 radeon_ring_write(ring, 0); in cayman_cp_start()
1566 radeon_ring_write(ring, 0xc0026f00); in cayman_cp_start()
1567 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1568 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1569 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1572 radeon_ring_write(ring, 0xc0036f00); in cayman_cp_start()
1573 radeon_ring_write(ring, 0x00000bc4); in cayman_cp_start()
1574 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1575 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1576 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1578 radeon_ring_write(ring, 0xc0026900); in cayman_cp_start()
1579 radeon_ring_write(ring, 0x00000316); in cayman_cp_start()
1580 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cayman_cp_start()
1581 radeon_ring_write(ring, 0x00000010); /* */ in cayman_cp_start()
1587 return 0; in cayman_cp_start()
1592 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1595 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1647 WREG32(GRBM_SOFT_RESET, 0); in cayman_cp_resume()
1650 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cayman_cp_resume()
1651 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cayman_cp_resume()
1654 WREG32(CP_RB_WPTR_DELAY, 0); in cayman_cp_resume()
1659 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1660 WREG32(SCRATCH_UMSK, 0xff); in cayman_cp_resume()
1662 for (i = 0; i < 3; ++i) { in cayman_cp_resume()
1667 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1668 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1676 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1677 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); in cayman_cp_resume()
1678 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); in cayman_cp_resume()
1682 for (i = 0; i < 3; ++i) { in cayman_cp_resume()
1683 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1684 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1687 for (i = 0; i < 3; ++i) { in cayman_cp_resume()
1689 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1692 ring->wptr = 0; in cayman_cp_resume()
1693 WREG32(cp_rb_rptr[i], 0); in cayman_cp_resume()
1694 WREG32(cp_rb_wptr[i], ring->wptr); in cayman_cp_resume()
1697 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); in cayman_cp_resume()
1702 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1703 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1704 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1706 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1708 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1709 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1710 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1714 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1715 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1717 return 0; in cayman_cp_resume()
1722 u32 reset_mask = 0; in cayman_gpu_check_soft_reset()
1742 /* DMA_STATUS_REG 0 */ in cayman_gpu_check_soft_reset()
1791 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in cayman_gpu_check_soft_reset()
1801 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in cayman_gpu_soft_reset()
1804 if (reset_mask == 0) in cayman_gpu_soft_reset()
1807 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1810 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1811 RREG32(0x14F8)); in cayman_gpu_soft_reset()
1812 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1813 RREG32(0x14D8)); in cayman_gpu_soft_reset()
1814 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1815 RREG32(0x14FC)); in cayman_gpu_soft_reset()
1816 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1817 RREG32(0x14DC)); in cayman_gpu_soft_reset()
1840 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1888 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1896 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1910 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1936 return 0; in cayman_asic_reset()
1953 return 0; in cayman_asic_reset()
1957 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1982 if (!rdev->has_uvd) in cayman_uvd_init()
1987 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in cayman_uvd_init()
1989 * At this point rdev->uvd.vcpu_bo is NULL which trickles down in cayman_uvd_init()
1994 rdev->has_uvd = false; in cayman_uvd_init()
1997 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in cayman_uvd_init()
1998 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in cayman_uvd_init()
2005 if (!rdev->has_uvd) in cayman_uvd_start()
2010 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in cayman_uvd_start()
2015 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in cayman_uvd_start()
2021 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2029 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2032 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_uvd_resume()
2033 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2035 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in cayman_uvd_resume()
2040 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in cayman_uvd_resume()
2050 if (!rdev->has_vce) in cayman_vce_init()
2055 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in cayman_vce_init()
2057 * At this point rdev->vce.vcpu_bo is NULL which trickles down in cayman_vce_init()
2062 rdev->has_vce = false; in cayman_vce_init()
2065 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in cayman_vce_init()
2066 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in cayman_vce_init()
2067 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in cayman_vce_init()
2068 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in cayman_vce_init()
2075 if (!rdev->has_vce) in cayman_vce_start()
2080 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2085 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2090 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in cayman_vce_start()
2095 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in cayman_vce_start()
2101 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2102 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2110 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2113 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_vce_resume()
2114 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2116 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2119 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_vce_resume()
2120 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2122 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2127 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in cayman_vce_resume()
2134 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup()
2149 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2163 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2164 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2165 rdev->rlc.reg_list_size = in cayman_startup()
2167 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2182 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2191 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2197 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2203 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2209 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2214 if (!rdev->irq.installed) { in cayman_startup()
2228 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2233 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2234 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2235 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); in cayman_startup()
2239 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2240 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2241 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); in cayman_startup()
2261 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2267 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2275 return 0; in cayman_startup()
2287 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2292 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2295 rdev->accel_working = true; in cayman_resume()
2299 rdev->accel_working = false; in cayman_resume()
2312 if (rdev->has_uvd) { in cayman_suspend()
2319 return 0; in cayman_suspend()
2330 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init()
2336 return -EINVAL; in cayman_init()
2339 if (!rdev->is_atom_bios) { in cayman_init()
2340 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2341 return -EINVAL; in cayman_init()
2349 if (!rdev->bios) { in cayman_init()
2350 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2351 return -EINVAL; in cayman_init()
2354 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2375 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2376 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2384 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2396 ring->ring_obj = NULL; in cayman_init()
2399 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2400 ring->ring_obj = NULL; in cayman_init()
2403 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2404 ring->ring_obj = NULL; in cayman_init()
2410 rdev->ih.ring_obj = NULL; in cayman_init()
2417 rdev->accel_working = true; in cayman_init()
2420 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2424 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2431 rdev->accel_working = false; in cayman_init()
2441 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2443 return -EINVAL; in cayman_init()
2446 return 0; in cayman_init()
2455 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2463 if (rdev->has_vce) in cayman_fini()
2471 kfree(rdev->bios); in cayman_fini()
2472 rdev->bios = NULL; in cayman_fini()
2481 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2483 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2486 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2488 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2489 return 0; in cayman_vm_init()
2497 * cayman_vm_decode_fault - print human readable fault info
2651 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", in cayman_vm_decode_fault()
2658 * cayman_vm_flush - vm flush using the CP
2661 * using the CP (cayman-si).
2666 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
2670 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2671 radeon_ring_write(ring, 0x1); in cayman_vm_flush()
2673 /* bits 0-7 are the VM contexts0-7 */ in cayman_vm_flush()
2674 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
2679 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in cayman_vm_flush()
2680 WAIT_REG_MEM_ENGINE(0))); /* me */ in cayman_vm_flush()
2682 radeon_ring_write(ring, 0); in cayman_vm_flush()
2683 radeon_ring_write(ring, 0); /* ref */ in cayman_vm_flush()
2684 radeon_ring_write(ring, 0); /* mask */ in cayman_vm_flush()
2685 radeon_ring_write(ring, 0x20); /* poll interval */ in cayman_vm_flush()
2688 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cayman_vm_flush()
2689 radeon_ring_write(ring, 0x0); in cayman_vm_flush()
2702 for (i = 0; i < 100; i++) { in tn_set_vce_clocks()
2708 return -ETIMEDOUT; in tn_set_vce_clocks()
2712 for (i = 0; i < 100; i++) { in tn_set_vce_clocks()
2718 return -ETIMEDOUT; in tn_set_vce_clocks()
2720 return 0; in tn_set_vce_clocks()