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Searched refs:spread (Results 1 – 25 of 71) sorted by relevance

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/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf134 (RO) Presents SSC (spread spectrum clock) information for EMI
140 [7:0] Sets clock spectrum spread percentage:
142 1 LSB = 0.1% increase in spread (for
144 1 LSB = 0.2% increase in spread (for
146 [8] When set to 1, enables spread
155 to spread waveform
/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt40 regulator-coupled-max-spread = <170000 550000>;
50 regulator-coupled-max-spread = <170000 550000>;
60 regulator-coupled-max-spread = <550000 550000>;
/linux/Documentation/misc-devices/
H A Dics932s401.rst25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
/linux/lib/zstd/common/
H A Dfse_decompress.c76 BYTE* spread = (BYTE*)(symbolNext + maxSymbolValue + 1); in FSE_buildDTable_internal() local
122 MEM_write64(spread + pos, sv); in FSE_buildDTable_internal()
124 MEM_write64(spread + pos + i, sv); in FSE_buildDTable_internal()
144 tableDecode[uPosition].symbol = spread[s + u]; in FSE_buildDTable_internal()
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst241 Set the FIVR spread spectrum clocking percentage
244 Enable/disable of the FIVR spread spectrum clocking feature
309 Sets DLVR spread spectrum percent value.
312 Specifies how frequencies are spread using spread spectrum.
313 0: Down spread,
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi57 regulator-coupled-max-spread = <300000>;
134 regulator-coupled-max-spread = <300000>;
H A Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi70 regulator-coupled-max-spread = <300000>;
83 regulator-coupled-max-spread = <300000>;
H A Dtegra20-ventana.dts407 regulator-coupled-max-spread = <170000 550000>;
419 regulator-coupled-max-spread = <550000 550000>;
447 regulator-coupled-max-spread = <170000 550000>;
H A Dtegra20-paz00.dts362 regulator-coupled-max-spread = <170000 550000>;
373 regulator-coupled-max-spread = <550000 550000>;
400 regulator-coupled-max-spread = <170000 550000>;
/linux/lib/zstd/compress/
H A Dfse_compress.c119 …BYTE* const spread = tableSymbol + tableSize; /* size = tableSize + 8 (may write beyond tableSize)… in FSE_buildCTable_wksp() local
127 MEM_write64(spread + pos, sv); in FSE_buildCTable_wksp()
129 MEM_write64(spread + pos + i, sv); in FSE_buildCTable_wksp()
147 tableSymbol[uPosition] = spread[s + u]; in FSE_buildCTable_wksp()
/linux/drivers/clk/
H A Dclk-eyeq.c166 u32 spread; in eqc_pll_parse_registers() local
207 spread = FIELD_GET(PCSR1_SPREAD, r1); in eqc_pll_parse_registers()
208 *acc = spread * 500000; in eqc_pll_parse_registers()
215 *mult *= 2000 - spread; in eqc_pll_parse_registers()
/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,berlin.txt7 Clock related registers are spread among the chip control registers. Berlin
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-evb.dts146 regulator-coupled-max-spread = <100000>;
154 regulator-coupled-max-spread = <100000>;
/linux/Documentation/driver-api/media/drivers/
H A Drkisp1.rst22 reached much market spread.
/linux/Documentation/admin-guide/device-mapper/
H A Dswitch.rst22 is created it is spread across multiple members. The details of the
44 spread with an address region size on the order of 10s of MBs, which
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-dms-ba16.dts114 fsl,no-spread-spectrum;
H A Dimx6q-cubox-i-som-v15.dts58 fsl,no-spread-spectrum;
H A Dimx6q-cubox-i.dts58 fsl,no-spread-spectrum;
H A Dimx6q-cubox-i-emmc-som-v15.dts59 fsl,no-spread-spectrum;
H A Dimx6q-hummingboard2-emmc-som-v15.dts62 fsl,no-spread-spectrum;
H A Dimx6q-hummingboard2.dts60 fsl,no-spread-spectrum;
H A Dimx6q-hummingboard2-som-v15.dts61 fsl,no-spread-spectrum;
/linux/Documentation/devicetree/bindings/arm/
H A Dsyna.txt52 CPU boot address. Unfortunately, the individual registers are spread among the
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c356 bool spread; member
564 if (tc->link.spread) in tc_srcctrl()
861 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
881 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
1108 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1194 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()

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