xref: /linux/Documentation/arch/mips/ingenic-tcu.rst (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1*ec62a746SCosta Shulyupin.. SPDX-License-Identifier: GPL-2.0
2*ec62a746SCosta Shulyupin
3*ec62a746SCosta Shulyupin===============================================
4*ec62a746SCosta ShulyupinIngenic JZ47xx SoCs Timer/Counter Unit hardware
5*ec62a746SCosta Shulyupin===============================================
6*ec62a746SCosta Shulyupin
7*ec62a746SCosta ShulyupinThe Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
8*ec62a746SCosta Shulyupinhardware block. It features up to eight channels, that can be used as
9*ec62a746SCosta Shulyupincounters, timers, or PWM.
10*ec62a746SCosta Shulyupin
11*ec62a746SCosta Shulyupin- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
12*ec62a746SCosta Shulyupin  have eight channels.
13*ec62a746SCosta Shulyupin
14*ec62a746SCosta Shulyupin- JZ4725B introduced a separate channel, called Operating System Timer
15*ec62a746SCosta Shulyupin  (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16*ec62a746SCosta Shulyupin  64-bit.
17*ec62a746SCosta Shulyupin
18*ec62a746SCosta Shulyupin- Each one of the TCU channels has its own clock, which can be reparented to three
19*ec62a746SCosta Shulyupin  different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
20*ec62a746SCosta Shulyupin
21*ec62a746SCosta Shulyupin    - The watchdog and OST hardware blocks also feature a TCSR register with the same
22*ec62a746SCosta Shulyupin      format in their register space.
23*ec62a746SCosta Shulyupin    - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
24*ec62a746SCosta Shulyupin      OST clocks.
25*ec62a746SCosta Shulyupin
26*ec62a746SCosta Shulyupin- Each TCU channel works in one of two modes:
27*ec62a746SCosta Shulyupin
28*ec62a746SCosta Shulyupin    - mode TCU1: channels cannot work in sleep mode, but are easier to
29*ec62a746SCosta Shulyupin      operate.
30*ec62a746SCosta Shulyupin    - mode TCU2: channels can work in sleep mode, but the operation is a bit
31*ec62a746SCosta Shulyupin      more complicated than with TCU1 channels.
32*ec62a746SCosta Shulyupin
33*ec62a746SCosta Shulyupin- The mode of each TCU channel depends on the SoC used:
34*ec62a746SCosta Shulyupin
35*ec62a746SCosta Shulyupin    - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
36*ec62a746SCosta Shulyupin      TCU1 mode.
37*ec62a746SCosta Shulyupin    - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
38*ec62a746SCosta Shulyupin    - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
39*ec62a746SCosta Shulyupin      others operate as TCU1.
40*ec62a746SCosta Shulyupin
41*ec62a746SCosta Shulyupin- Each channel can generate an interrupt. Some channels share an interrupt
42*ec62a746SCosta Shulyupin  line, some don't, and this changes between SoC versions:
43*ec62a746SCosta Shulyupin
44*ec62a746SCosta Shulyupin    - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
45*ec62a746SCosta Shulyupin      own interrupt line; channels 2-7 share the last interrupt line.
46*ec62a746SCosta Shulyupin    - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
47*ec62a746SCosta Shulyupin      interrupt line; the OST uses the last interrupt line.
48*ec62a746SCosta Shulyupin    - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
49*ec62a746SCosta Shulyupin      channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
50*ec62a746SCosta Shulyupin      the OST uses the last interrupt line.
51*ec62a746SCosta Shulyupin
52*ec62a746SCosta ShulyupinImplementation
53*ec62a746SCosta Shulyupin==============
54*ec62a746SCosta Shulyupin
55*ec62a746SCosta ShulyupinThe functionalities of the TCU hardware are spread across multiple drivers:
56*ec62a746SCosta Shulyupin
57*ec62a746SCosta Shulyupin===========  =====
58*ec62a746SCosta Shulyupinclocks       drivers/clk/ingenic/tcu.c
59*ec62a746SCosta Shulyupininterrupts   drivers/irqchip/irq-ingenic-tcu.c
60*ec62a746SCosta Shulyupintimers       drivers/clocksource/ingenic-timer.c
61*ec62a746SCosta ShulyupinOST          drivers/clocksource/ingenic-ost.c
62*ec62a746SCosta ShulyupinPWM          drivers/pwm/pwm-jz4740.c
63*ec62a746SCosta Shulyupinwatchdog     drivers/watchdog/jz4740_wdt.c
64*ec62a746SCosta Shulyupin===========  =====
65*ec62a746SCosta Shulyupin
66*ec62a746SCosta ShulyupinBecause various functionalities of the TCU that belong to different drivers
67*ec62a746SCosta Shulyupinand frameworks can be controlled from the same registers, all of these
68*ec62a746SCosta Shulyupindrivers access their registers through the same regmap.
69*ec62a746SCosta Shulyupin
70*ec62a746SCosta ShulyupinFor more information regarding the devicetree bindings of the TCU drivers,
71*ec62a746SCosta Shulyupinhave a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.
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