| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 793 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
828 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1091 for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1126 for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1139 for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1144 for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1151 for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1175 for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1298 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1306 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 832 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
867 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1147 for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1182 for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1195 for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1200 for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1207 for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1231 for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1357 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1365 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1186 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1538 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1572 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1585 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1590 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1597 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1620 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1636 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1670 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1694 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 1530 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn42b_resource_destruct()
1559 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) { in dcn42b_resource_destruct()
1564 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn42b_resource_destruct()
1575 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn42b_resource_destruct()
1580 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn42b_resource_destruct()
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn42b_resource_destruct()
1610 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn42b_resource_destruct()
1626 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn42b_resource_destruct()
1714 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn42b_dwbc_create()
1750 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn42b_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1251 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1603 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1636 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1649 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1654 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1661 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1684 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1700 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1737 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1761 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1180 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1594 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
1624 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
1637 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
1642 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1649 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1672 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1688 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1746 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1784 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1194 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1543 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1577 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1590 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1595 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1602 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1625 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1641 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1678 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1702 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1193 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1607 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1637 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1650 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1655 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1662 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1685 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1701 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1759 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1797 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1193 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1545 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1579 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1592 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1597 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1604 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1627 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1643 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1680 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1704 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1173 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1617 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1630 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1635 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1642 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1665 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1681 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1739 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1777 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 379 static const struct resource_caps res_cap = { variable
856 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
931 pool->base.res_cap = &res_cap; in dce60_construct()
939 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
940 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1057 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1131 pool->base.res_cap = &res_cap_61; in dce61_construct()
1257 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1331 pool->base.res_cap in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 1542 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn42_resource_destruct()
1571 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn42_resource_destruct()
1584 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn42_resource_destruct()
1589 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn42_resource_destruct()
1596 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn42_resource_destruct()
1619 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn42_resource_destruct()
1635 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn42_resource_destruct()
1725 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn42_dwbc_create()
1761 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn42_mmhubbub_create()
1886 if ((unsigned int)(eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn42_link_enc_create_minimal()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1532 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1561 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1574 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1579 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1586 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1609 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1625 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1652 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1680 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1837 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1239 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1275 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1288 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1293 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1300 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1323 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1379 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1403 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1604 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1634 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1562 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
1592 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
1605 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
1610 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1617 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1640 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn401_resource_destruct()
1656 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1683 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1713 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
2046 pool->base.res_cap = &res_cap_dcn4_01; in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 1677 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn60_resource_destruct()
1707 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) { in dcn60_resource_destruct()
1712 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn60_resource_destruct()
1723 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn60_resource_destruct()
1728 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn60_resource_destruct()
1747 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn60_resource_destruct()
1763 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn60_resource_destruct()
1988 pool->base.res_cap = &res_cap_dcn6_0; in dcn60_resource_construct()
1991 num_pipes = pool->base.res_cap->num_timing_generator; in dcn60_resource_construct()
1994 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn60_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 379 static const struct resource_caps res_cap = { variable
807 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
1050 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1125 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1126 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1183 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1557 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1600 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1605 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1612 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1635 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1651 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1678 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1706 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1796 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 603 ASSERT(dc->res_pool->res_cap->num_dwb >= 0); in dcn30_program_all_writeback_pipes_in_tree()
604 ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
634 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 575 for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { in dcn60_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 344 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
345 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
391 num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in destroy_link_encoders()
392 num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in destroy_link_encoders()
1594 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator; in dc_create()
1996 if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) { in dc_validate_boot_timing()
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| H A D | dc_resource.c | 463 const struct resource_caps *caps = pool->res_cap; in resource_construct()
4375 return dc->res_pool->res_cap->num_dsc > 0; in dc_resource_is_dsc_encoding_supported()
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