| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1145 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1209 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1153 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1080 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1158 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1138 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1151 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1076 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1097 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
| H A D | dpcs_3_1_4_offset.h | 6256 #define regDC_PINSTRAPS … macro
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| H A D | dpcs_4_2_3_offset.h | 629 #define regDC_PINSTRAPS … macro
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| H A D | dpcs_4_2_2_offset.h | 593 #define regDC_PINSTRAPS … macro
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| H A D | dpcs_4_2_0_offset.h | 596 #define regDC_PINSTRAPS … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
| H A D | dcn_3_2_0_offset.h | 10949 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_1_5_offset.h | 11550 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_5_1_offset.h | 9776 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_5_0_offset.h | 9797 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_1_4_offset.h | 10908 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_1_2_offset.h | 11805 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_2_1_offset.h | 10958 #define regDC_PINSTRAPS … macro
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| H A D | dcn_3_1_6_offset.h | 12041 #define regDC_PINSTRAPS … macro
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| H A D | dcn_4_1_0_offset.h | 11209 #define regDC_PINSTRAPS … macro
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