| /linux/drivers/irqchip/ |
| H A D | irq-pruss-intc.c | 122 struct pruss_intc *intc; member
126 static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) in pruss_intc_read_reg() argument
128 return readl_relaxed(intc->base + reg); in pruss_intc_read_reg()
131 static inline void pruss_intc_write_reg(struct pruss_intc *intc, in pruss_intc_write_reg() argument
134 writel_relaxed(val, intc->base + reg); in pruss_intc_write_reg()
137 static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt, in pruss_intc_update_cmr() argument
145 val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); in pruss_intc_update_cmr()
148 pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); in pruss_intc_update_cmr()
150 dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch, in pruss_intc_update_cmr()
151 idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); in pruss_intc_update_cmr()
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| H A D | irq-bcm7038-l1.c | 79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
127 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
[all …]
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| H A D | irq-bcm6345-l1.c | 84 struct bcm6345_l1_chip *intc; member
90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() argument
94 return (1 * intc->n_words - word - 1) * sizeof(u32); in reg_enable()
96 return (0 * intc->n_words + word) * sizeof(u32); in reg_enable()
100 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, in reg_status() argument
104 return (2 * intc->n_words - word - 1) * sizeof(u32); in reg_status()
106 return (1 * intc->n_words + word) * sizeof(u32); in reg_status()
110 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, in cpu_for_irq() argument
113 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); in cpu_for_irq()
119 struct bcm6345_l1_chip *intc = cpu->intc; in bcm6345_l1_irq_handle() local
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| H A D | irq-ingenic.c | 36 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
37 struct irq_domain *domain = intc->domain; in intc_cascade()
42 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
63 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
70 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
71 if (!intc) { in ingenic_intc_of_init()
82 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
86 intc->num_chips = num_chips; in ingenic_intc_of_init()
87 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
88 if (!intc->base) { in ingenic_intc_of_init()
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| H A D | irq-bcm2836.c | 23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
66 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); in bcm2836_arm_irqchip_mask_pmu_irq()
71 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); in bcm2836_arm_irqchip_unmask_pmu_irq()
145 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); in bcm2836_arm_irqchip_handle_irq()
149 generic_handle_domain_irq(intc.domain, hwirq); in bcm2836_arm_irqchip_handle_irq()
164 mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu); in bcm2836_arm_irqchip_handle_ipi()
178 intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu); in bcm2836_arm_irqchip_ipi_ack()
185 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; in bcm2836_arm_irqchip_ipi_send_mask()
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| H A D | irq-bcm2835.c | 87 static struct armctrl_ic intc __read_mostly;
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
147 intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), in armctrl_of_init()
149 if (!intc.domain) in armctrl_of_init()
153 intc.pending[b] = base + reg_pending[b]; in armctrl_of_init()
154 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
155 intc.disable[b] = base + reg_disable[b]; in armctrl_of_init()
158 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i)); in armctrl_of_init()
165 reg = readl_relaxed(intc.enable[b]); in armctrl_of_init()
[all …]
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
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| H A D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
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| H A D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
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| /linux/arch/m68k/coldfire/ |
| H A D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o
27 obj-$(CONFIG_M528x) += m528x.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o intc.o reset.o
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
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| H A D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| H A D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
37 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
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| H A D | ti,omap2-intc.txt | 9 "ti,omap2-intc"
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
20 intc: interrupt-controller@1 {
21 compatible = "ti,omap2-intc";
24 ti,intc-size = <96>;
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| H A D | ti,cp-intc.txt | 10 "ti,cp-intc"
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
21 intc: interrupt-controller@1 {
22 compatible = "ti,cp-intc";
25 ti,intc-size = <101>;
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| /linux/arch/mips/boot/dts/ingenic/ |
| H A D | jz4770.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4770-intc";
92 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
155 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
185 interrupt-parent = <&intc>;
200 interrupt-parent = <&intc>;
215 interrupt-parent = <&intc>;
230 interrupt-parent = <&intc>;
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| H A D | jz4780.dtsi | 41 intc: interrupt-controller@10001000 { label
42 compatible = "ingenic,jz4780-intc";
113 interrupt-parent = <&intc>;
153 interrupt-parent = <&intc>;
180 interrupt-parent = <&intc>;
195 interrupt-parent = <&intc>;
210 interrupt-parent = <&intc>;
225 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
255 interrupt-parent = <&intc>;
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| H A D | x1000.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
121 interrupt-parent = <&intc>;
149 interrupt-parent = <&intc>;
173 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
203 interrupt-parent = <&intc>;
218 interrupt-parent = <&intc>;
227 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
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| H A D | x1830.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
114 interrupt-parent = <&intc>;
144 interrupt-parent = <&intc>;
168 interrupt-parent = <&intc>;
183 interrupt-parent = <&intc>;
198 interrupt-parent = <&intc>;
213 interrupt-parent = <&intc>;
222 interrupt-parent = <&intc>;
235 interrupt-parent = <&intc>;
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| H A D | jz4740.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
111 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
181 interrupt-parent = <&intc>;
192 interrupt-parent = <&intc>;
219 interrupt-parent = <&intc>;
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| H A D | jz4725b.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
120 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
190 interrupt-parent = <&intc>;
204 interrupt-parent = <&intc>;
228 interrupt-parent = <&intc>;
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| /linux/arch/arm/boot/dts/xilinx/ |
| H A D | zynq-7000.dtsi | 48 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
106 interrupt-parent = <&intc>;
117 interrupt-parent = <&intc>;
129 interrupt-parent = <&intc>;
141 interrupt-parent = <&intc>;
150 interrupt-parent = <&intc>;
162 interrupt-parent = <&intc>;
170 intc: interrupt-controller@f8f01000 { label
215 interrupt-parent = <&intc>;
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | mmp3.dtsi | 49 compatible = "marvell,mmp3-intc";
54 mrvl,intc-nr-irqs = <64>;
58 compatible = "mrvl,mmp2-mux-intc";
64 mrvl,intc-nr-irqs = <4>;
68 compatible = "mrvl,mmp2-mux-intc";
74 mrvl,intc-nr-irqs = <2>;
78 compatible = "mrvl,mmp2-mux-intc";
84 mrvl,intc-nr-irqs = <3>;
88 compatible = "mrvl,mmp2-mux-intc";
94 mrvl,intc-nr-irqs = <3>;
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| /linux/arch/mips/boot/dts/ralink/ |
| H A D | rt3050.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
|