87 static struct armctrl_ic intc __read_mostly;
94 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);  in armctrl_mask_irq()
99 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);  in armctrl_unmask_irq()
147 	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),  in armctrl_of_init()
149 	if (!intc.domain)  in armctrl_of_init()
153 		intc.pending[b] = base + reg_pending[b];  in armctrl_of_init()
154 		intc.enable[b] = base + reg_enable[b];  in armctrl_of_init()
155 		intc.disable[b] = base + reg_disable[b];  in armctrl_of_init()
158 			irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));  in armctrl_of_init()
165 		reg = readl_relaxed(intc.enable[b]);  in armctrl_of_init()
167 			writel_relaxed(reg, intc.disable[b]);  in armctrl_of_init()
215 	u32 stat = readl_relaxed(intc.pending[bank]);  in armctrl_translate_bank()
227 	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;  in get_next_armctrl_hwirq()
251 		generic_handle_domain_irq(intc.domain, hwirq);  in bcm2835_handle_irq()
259 		generic_handle_domain_irq(intc.domain, hwirq);  in bcm2836_chained_handle_irq()