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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c55 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
56 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
57 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
66 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
67 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
68 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
69 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
70 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
78 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
87 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
[all …]
H A Dgfx_v11_0.c41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
274 /* gfx queue registers */
375 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
440 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
509 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
686 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
687 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
688 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
689 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
691 kfree(adev->gfx in gfx_v11_0_free_microcode()
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H A Dgfx_v12_0.c39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
208 /* gfx queue registers */
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
427 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
558 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
559 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
560 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
561 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
563 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
601 err = amdgpu_ucode_request(adev, &adev->gfx in gfx_v12_0_init_microcode()
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H A Dgfx_v12_1.c278 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_1_kiq_unmap_queues()
349 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_set_kiq_pm4_funcs()
351 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; in gfx_v12_1_set_kiq_pm4_funcs()
491 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_1_free_microcode()
492 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_1_free_microcode()
494 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_1_free_microcode()
535 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_1_init_microcode()
539 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_1_init_microcode()
544 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v12_1_init_microcode()
552 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v12_1_init_microcode()
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H A Dgfx_v9_4_3.c181 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
341 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
343 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
512 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
516 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
523 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
524 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
525 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
526 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_4_3_free_microcode()
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H A Dgfx_v9_0.c934 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_0_kiq_set_resources()
1093 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1283 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1284 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1285 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1286 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1287 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1288 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1290 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1295 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
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H A Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
985 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
994 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
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H A Dgfx_v10_0.c3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx10_kiq_set_resources()
3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
4131 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
4132 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
4134 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
4137 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4142 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
[all …]
H A Damdgpu_dev_coredump.c98 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
100 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
102 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
104 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
107 adev->gfx.rlc_srlc_feature_version, in amdgpu_devcoredump_fw_info()
108 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
110 adev->gfx.rlc_srlg_feature_version, in amdgpu_devcoredump_fw_info()
111 adev->gfx.rlc_srlg_fw_version); in amdgpu_devcoredump_fw_info()
113 adev->gfx.rlc_srls_feature_version, in amdgpu_devcoredump_fw_info()
114 adev->gfx.rlc_srls_fw_version); in amdgpu_devcoredump_fw_info()
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H A Dimu_v11_0.c60 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
63 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
68 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
74 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
79 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
83 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
90 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
102 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
105 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
108 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
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H A Damdgpu_amdkfd_gfx_v12.c46 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
47 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
62 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v12()
63 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v12()
406 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
407 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
484 bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap, in kgd_gfx_v12_get_cu_occupancy()
486 max_queue_cnt = adev->gfx.mec.num_pipe_per_mec * in kgd_gfx_v12_get_cu_occupancy()
487 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v12_get_cu_occupancy()
488 se_cnt = adev->gfx.config.max_shader_engines; in kgd_gfx_v12_get_cu_occupancy()
[all …]
H A Damdgpu_discovery.c923 adev->gfx.xcc_mask &= ~BIT(inst); in amdgpu_discovery_read_from_harvest_table()
1213 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1760 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1860 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
2018 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
2019 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
2021 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
2022 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
2023 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
2024 adev->gfx in amdgpu_discovery_get_gfx_info()
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H A Damdgpu_amdkfd_gfx_v12_1.c46 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
47 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
62 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v12_1()
63 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v12_1()
409 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
410 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
487 bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap, in kgd_gfx_v12_1_get_cu_occupancy()
489 max_queue_cnt = adev->gfx.mec.num_pipe_per_mec * in kgd_gfx_v12_1_get_cu_occupancy()
490 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v12_1_get_cu_occupancy()
491 se_cnt = adev->gfx.config.max_shader_engines; in kgd_gfx_v12_1_get_cu_occupancy()
[all …]
H A Damdgpu_amdkfd_gfx_v11.c58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
111 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v11()
112 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v11()
183 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v11()
184 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v11()
266 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v11()
275 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v11()
276 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v11()
[all …]
H A Damdgpu_debugfs.c151 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
152 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
280 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
281 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
451 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_gprwave_read()
452 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
456 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gprwave_read()
457 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data); in amdgpu_debugfs_gprwave_read()
459 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gprwave_read()
460 adev->gfx in amdgpu_debugfs_gprwave_read()
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H A Damdgpu_mes.c108 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_mes_init()
109 u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, in amdgpu_mes_init()
110 adev->gfx.me.num_queue_per_pipe, in amdgpu_mes_init()
111 adev->gfx.disable_kq ? 0 : adev->gfx.num_gfx_rings); in amdgpu_mes_init()
112 u32 compute_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.mec.num_pipe_per_mec, in amdgpu_mes_init()
113 adev->gfx.mec.num_queue_per_pipe, in amdgpu_mes_init()
114 adev->gfx.disable_kq ? 0 : adev->gfx.num_compute_rings); in amdgpu_mes_init()
132 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
144 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; in amdgpu_mes_init()
156 if (i >= adev->gfx.mec.num_pipe_per_mec) in amdgpu_mes_init()
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H A Damdgpu_amdkfd.c184 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
185 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
198 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
205 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
206 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
477 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
480 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
483 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
486 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
489 return adev->gfx in amdgpu_amdkfd_get_fw_version()
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H A Damdgpu_amdkfd_gfx_v10_3.c60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
115 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
116 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
197 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
198 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3()
289 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
290 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
[all …]
H A Damdgpu_amdkfd_gfx_v9.c66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_acquire_queue()
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_acquire_queue()
75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
166 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
167 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
305 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load()
314 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
315 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
320 spin_lock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
347 spin_unlock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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H A Damdgpu_ring_mux.c319 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_rptr_gfx()
328 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_wptr_gfx()
337 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_set_wptr_gfx()
396 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_begin()
399 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) { in amdgpu_sw_ring_ib_begin()
411 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_end()
414 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) in amdgpu_sw_ring_ib_end()
422 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_mark_offset()
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c118 static struct rpmhpd gfx = { variable
241 [RPMHPD_GFX] = &gfx,
260 [RPMHPD_GFX] = &gfx,
299 [SA8775P_GFX] = &gfx,
322 [RPMHPD_GFX] = &gfx,
346 [RPMHPD_GFX] = &gfx,
369 [SDM670_GFX] = &gfx,
387 [SDM845_GFX] = &gfx,
460 [SM6350_GFX] = &gfx,
476 [RPMHPD_GFX] = &gfx,
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_crat.c1450 if (adev->gfx.config.gc_tcp_l1_size) { in kfd_fill_gpu_cache_info_from_gfx_config()
1451 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1456 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1457 pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1463 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1465 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
1470 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1471 pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1477 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1478 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/
H A Damdgpu_dm_plane_test.c538 adev->gfx.config.gb_addr_config_fields.num_pipes = 2; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
539 adev->gfx.config.gb_addr_config_fields.num_banks = 4; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
540 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
541 adev->gfx.config.gb_addr_config_fields.num_se = 1; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
542 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
543 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
588 adev->gfx.config.gb_addr_config_fields.num_pipes = 2; in dm_test_fill_gfx9_plane_attributes_from_modifiers()
589 adev->gfx.config.gb_addr_config_fields.num_banks = 4; in dm_test_fill_gfx9_plane_attributes_from_modifiers()
590 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256; in dm_test_fill_gfx9_plane_attributes_from_modifiers()
591 adev->gfx.config.gb_addr_config_fields.num_se = 1; in dm_test_fill_gfx9_plane_attributes_from_modifiers()
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()

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