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Searched refs:gfx (Results 1 – 25 of 121) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c353 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
418 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
486 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
663 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
664 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
665 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
666 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
668 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
700 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
701 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
[all …]
H A Dgfx_v12_0.c358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
557 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
558 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
559 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
560 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
562 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v12_0_init_microcode()
608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v12_0_init_microcode()
618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_0_init_microcode()
[all …]
H A Dgfx_v7_0.c892 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
895 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
896 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
897 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
939 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v7_0_init_microcode()
945 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v7_0_init_microcode()
951 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v7_0_init_microcode()
[all …]
H A Dgfx_v6_0.c353 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
362 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v6_0_init_microcode()
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
368 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
369 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
371 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v6_0_init_microcode()
376 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
[all …]
H A Damdgpu_dev_coredump.c88 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
90 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
92 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
94 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
97 adev->gfx.rlc_srlc_feature_version, in amdgpu_devcoredump_fw_info()
98 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
100 adev->gfx.rlc_srlg_feature_version, in amdgpu_devcoredump_fw_info()
101 adev->gfx.rlc_srlg_fw_version); in amdgpu_devcoredump_fw_info()
103 adev->gfx.rlc_srls_feature_version, in amdgpu_devcoredump_fw_info()
104 adev->gfx.rlc_srls_fw_version); in amdgpu_devcoredump_fw_info()
[all …]
H A Damdgpu_kms.c234 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
235 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
238 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
239 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
242 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
243 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
246 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
247 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
250 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
251 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
H A Dimu_v11_0.c56 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
59 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
64 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
70 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
75 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
79 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
86 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
98 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
101 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
104 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
[all …]
H A Dimu_v12_0.c52 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
55 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
60 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_init_microcode()
61 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v12_0_init_microcode()
66 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
71 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
81 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v12_0_init_microcode()
93 if (!adev->gfx.imu_fw) in imu_v12_0_load_microcode()
96 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_load_microcode()
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v12_0_load_microcode()
[all …]
H A Damdgpu_ucode.c754 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
755 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
756 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
757 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
758 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
759 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
760 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
761 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
762 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
763 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
[all …]
H A Damdgpu_discovery.c793 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1085 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1390 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1488 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1644 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1645 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1647 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1648 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1649 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1650 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
[all …]
H A Damdgpu_amdkfd.c180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
194 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
201 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
202 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
446 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
449 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
452 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
455 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
458 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
H A Daqua_vanjaram.c89 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_calc_xcp_mode()
90 if (adev->gfx.funcs->get_xccs_per_xcp) in __aqua_vanjaram_calc_xcp_mode()
91 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); in __aqua_vanjaram_calc_xcp_mode()
144 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()
179 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; in __aqua_vanjaram_get_xcp_ip_info()
180 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; in __aqua_vanjaram_get_xcp_ip_info()
258 *num_xcp = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_get_px_mode_info()
284 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_get_xcp_res_info()
319 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()
353 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()
[all …]
H A Damdgpu_ring_mux.c319 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_rptr_gfx()
328 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_wptr_gfx()
337 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_set_wptr_gfx()
396 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_begin()
399 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) { in amdgpu_sw_ring_ib_begin()
411 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_end()
414 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) in amdgpu_sw_ring_ib_end()
422 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_mark_offset()
H A Damdgpu_mes.c109 adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xFFFE : 0xFF00; in amdgpu_mes_init()
111 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
127 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE; in amdgpu_mes_init()
134 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2; in amdgpu_mes_init()
137 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; in amdgpu_mes_init()
145 adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC; in amdgpu_mes_init()
743 if (adev->enable_mes && adev->gfx.enable_cleaner_shader) { in amdgpu_mes_update_enforce_isolation()
H A Damdgpu_amdkfd_gfx_v8.c60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
118 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
119 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
172 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hqd_load()
173 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hqd_load()
H A Dmes_v11_0.c405 mutex_lock(&adev->gfx.reset_sem_mutex); in mes_v11_0_reset_queue_mmio()
417 mutex_unlock(&adev->gfx.reset_sem_mutex); in mes_v11_0_reset_queue_mmio()
1281 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v11_0_kiq_enable_queue()
1282 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_enable_queue()
1306 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_queue_init()
1361 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v11_0_kiq_ring_init()
1363 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_ring_init()
1389 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_mqd_sw_init()
1496 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, in mes_v11_0_sw_fini()
1497 &adev->gfx.kiq[0].ring.mqd_gpu_addr, in mes_v11_0_sw_fini()
[all …]
H A Damdgpu_virt.c568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
572 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
573 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
574 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
575 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
576 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
1204 adev->gfx.is_poweron = false; in amdgpu_virt_post_reset()
[all …]
H A Dsoc15_common.h41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
46 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
H A Dmes_v12_0.c430 mutex_lock(&adev->gfx.reset_sem_mutex); in mes_v12_0_reset_queue_mmio()
442 mutex_unlock(&adev->gfx.reset_sem_mutex); in mes_v12_0_reset_queue_mmio()
1445 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v12_0_kiq_enable_queue()
1446 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v12_0_kiq_enable_queue()
1475 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_queue_init()
1550 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v12_0_kiq_ring_init()
1552 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_kiq_ring_init()
1578 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_mqd_sw_init()
1679 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, in mes_v12_0_sw_fini()
1680 &adev->gfx.kiq[0].ring.mqd_gpu_addr, in mes_v12_0_sw_fini()
[all …]
H A Damdgpu_amdkfd_gfx_v7.c66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
123 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
124 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()
/linux/drivers/gpu/drm/ci/xfails/
H A Di915-apl-flakes.txt2 # Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/61f62c86-3e82-4eff-bd3c-8123fa0ca332@collabora.com/…
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c219 adev->gfx.config.gb_addr_config_fields.num_pipes; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
221 adev->gfx.config.gb_addr_config_fields.num_banks; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
223 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
225 adev->gfx.config.gb_addr_config_fields.num_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
227 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
229 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
232 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
407 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_add_gfx10_1_modifiers()
454 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_add_gfx9_modifiers()
456 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in amdgpu_dm_plane_add_gfx9_modifiers()
[all …]
/linux/drivers/video/
H A Dvgastate.c29 __u8 *gfx; member
251 saved->gfx[i] = vga_rgfx(state->vgabase, i); in save_vga_mode()
291 vga_wgfx(state->vgabase, i, saved->gfx[i]); in restore_vga_mode()
390 saved->gfx = saved->crtc + state->num_crtc; in save_vga()
391 saved->seq = saved->gfx + state->num_gfx; in save_vga()

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