| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx.c | 55 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
56 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
57 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
66 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
67 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
68 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
69 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
70 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
78 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
87 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
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| H A D | gfx_v11_0.c | 375 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
440 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
509 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
686 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
687 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
688 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
689 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
691 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
723 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
724 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
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| H A D | gfx_v12_0.c | 358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
427 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
558 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
559 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
560 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
561 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
563 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
601 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v12_0_init_microcode()
607 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( in gfx_v12_0_init_microcode()
609 adev->gfx.pfp_fw->data, 2, 0); in gfx_v12_0_init_microcode()
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| H A D | gfx_v12_1.c | 278 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_1_kiq_unmap_queues()
349 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_set_kiq_pm4_funcs()
351 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; in gfx_v12_1_set_kiq_pm4_funcs()
491 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_1_free_microcode()
492 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_1_free_microcode()
494 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_1_free_microcode()
535 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_1_init_microcode()
539 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v12_1_init_microcode()
544 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v12_1_init_microcode()
552 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v12_1_init_microcode()
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| H A D | gfx_v9_4_3.c | 181 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
341 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
343 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
512 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
516 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
523 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
524 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
525 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
526 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_4_3_free_microcode()
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| H A D | gfx_v9_0.c | 934 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_0_kiq_set_resources()
1093 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1283 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1284 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1285 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1286 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1287 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1288 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1290 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1295 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
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| H A D | gfx_v8_0.c | 927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
985 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
994 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
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| H A D | gfx_v10_0.c | 3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx10_kiq_set_resources()
3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
4131 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
4132 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
4134 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
4137 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4142 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
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| H A D | amdgpu_dev_coredump.c | 98 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
100 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
102 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
104 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
107 adev->gfx.rlc_srlc_feature_version, in amdgpu_devcoredump_fw_info()
108 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
110 adev->gfx.rlc_srlg_feature_version, in amdgpu_devcoredump_fw_info()
111 adev->gfx.rlc_srlg_fw_version); in amdgpu_devcoredump_fw_info()
113 adev->gfx.rlc_srls_feature_version, in amdgpu_devcoredump_fw_info()
114 adev->gfx.rlc_srls_fw_version); in amdgpu_devcoredump_fw_info()
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| H A D | imu_v11_0.c | 60 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
63 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
68 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
74 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
79 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
83 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
90 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
102 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
105 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
108 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
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| H A D | amdgpu_amdkfd.c | 184 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
185 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
198 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
205 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
206 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
477 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
480 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
483 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
486 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
489 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
115 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
116 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
197 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
198 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3()
289 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
290 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_acquire_queue()
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_acquire_queue()
75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
166 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
167 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
305 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load()
314 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
315 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
320 spin_lock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
347 spin_unlock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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| H A D | amdgpu_ring_mux.c | 319 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_rptr_gfx()
328 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_get_wptr_gfx()
337 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_set_wptr_gfx()
396 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_begin()
399 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) { in amdgpu_sw_ring_ib_begin()
411 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_end()
414 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) in amdgpu_sw_ring_ib_end()
422 struct amdgpu_ring_mux *mux = &adev->gfx.muxer; in amdgpu_sw_ring_ib_mark_offset()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
118 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
119 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
172 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hqd_load()
173 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hqd_load()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
146 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
147 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in kgd_hiq_mqd_load()
303 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hiq_mqd_load()
304 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hiq_mqd_load()
309 spin_lock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
336 spin_unlock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
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| H A D | mes_v12_1.c | 1436 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in mes_v12_1_kiq_enable_queue()
1437 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; in mes_v12_1_kiq_enable_queue()
1467 ring = &adev->gfx.kiq[xcc_id].ring; in mes_v12_1_queue_init()
1540 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); in mes_v12_1_kiq_ring_init()
1542 ring = &adev->gfx.kiq[xcc_id].ring; in mes_v12_1_kiq_ring_init()
1577 ring = &adev->gfx.kiq[xcc_id].ring; in mes_v12_1_mqd_sw_init()
1607 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_init()
1654 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_fini()
1684 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, in mes_v12_1_sw_fini()
1685 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, in mes_v12_1_sw_fini()
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| H A D | mes_v11_0.c | 479 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { in mes_v11_0_clear_hqds_on_mec_pipe()
497 if (adev->gfx.rs64_enable) { in mes_v11_0_reset_compute_pipe_mmio()
645 mutex_lock(&adev->gfx.reset_sem_mutex); in mes_v11_0_reset_queue_mmio()
657 mutex_unlock(&adev->gfx.reset_sem_mutex); in mes_v11_0_reset_queue_mmio()
1583 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v11_0_kiq_enable_queue()
1584 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_enable_queue()
1608 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_queue_init()
1665 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v11_0_kiq_ring_init()
1667 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_ring_init()
1693 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_mqd_sw_init()
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intel-i915-hwmon | 4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_crat.c | 1450 if (adev->gfx.config.gc_tcp_l1_size) { in kfd_fill_gpu_cache_info_from_gfx_config()
1451 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1456 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1457 pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1463 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1465 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
1470 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; in kfd_fill_gpu_cache_info_from_gfx_config()
1471 pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size; in kfd_fill_gpu_cache_info_from_gfx_config()
1477 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) { in kfd_fill_gpu_cache_info_from_gfx_config()
1478 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; in kfd_fill_gpu_cache_info_from_gfx_config()
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_gfxpll.c | 177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()
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| H A D | lsdc_pixpll.c | 476 const struct loongson_gfx_desc *gfx = to_loongson_gfx(descp); in lsdc_pixpll_init() local
480 this->reg_base = gfx->conf_reg_base + gfx->pixpll[index].reg_offset; in lsdc_pixpll_init()
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| /linux/drivers/gpu/drm/ci/xfails/ |
| H A D | i915-apl-flakes.txt | 2 # Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/61f62c86-3e82-4eff-bd3c-8123fa0ca332@collabora.com/…
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 255 adev->gfx.config.gb_addr_config_fields.num_pipes; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
257 adev->gfx.config.gb_addr_config_fields.num_banks; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
259 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
261 adev->gfx.config.gb_addr_config_fields.num_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
263 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
265 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
268 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
449 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_add_gfx10_1_modifiers()
558 adev->gfx.config.mem_row_size_in_kb * 1024); in amdgpu_dm_plane_calc_gfx7_tile_split()
614 gb_tile_mode = adev->gfx.config.tile_mode_array[tile_idx]; in amdgpu_dm_plane_calc_gfx6_mod()
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| /linux/drivers/video/ |
| H A D | vgastate.c | 29 __u8 *gfx; member
251 saved->gfx[i] = vga_rgfx(state->vgabase, i); in save_vga_mode()
291 vga_wgfx(state->vgabase, i, saved->gfx[i]); in restore_vga_mode()
390 saved->gfx = saved->crtc + state->num_crtc; in save_vga()
391 saved->seq = saved->gfx + state->num_gfx; in save_vga()
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