1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #include <linux/list.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27
28 #include <linux/firmware.h>
29 #include <drm/amdgpu_drm.h>
30 #include "amdgpu.h"
31 #include "atom.h"
32 #include "amdgpu_ucode.h"
33
34 struct amdgpu_cgs_device {
35 struct cgs_device base;
36 struct amdgpu_device *adev;
37 };
38
39 #define CGS_FUNC_ADEV \
40 struct amdgpu_device *adev = \
41 ((struct amdgpu_cgs_device *)cgs_device)->adev
42
43
amdgpu_cgs_read_register(struct cgs_device * cgs_device,unsigned int offset)44 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned int offset)
45 {
46 CGS_FUNC_ADEV;
47 return RREG32(offset);
48 }
49
amdgpu_cgs_write_register(struct cgs_device * cgs_device,unsigned int offset,uint32_t value)50 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned int offset,
51 uint32_t value)
52 {
53 CGS_FUNC_ADEV;
54 WREG32(offset, value);
55 }
56
amdgpu_cgs_read_ind_register(struct cgs_device * cgs_device,enum cgs_ind_reg space,unsigned int index)57 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
58 enum cgs_ind_reg space,
59 unsigned int index)
60 {
61 CGS_FUNC_ADEV;
62 switch (space) {
63 case CGS_IND_REG__PCIE:
64 return RREG32_PCIE(index);
65 case CGS_IND_REG__SMC:
66 return RREG32_SMC(index);
67 case CGS_IND_REG__UVD_CTX:
68 return RREG32_UVD_CTX(index);
69 case CGS_IND_REG__DIDT:
70 return RREG32_DIDT(index);
71 case CGS_IND_REG_GC_CAC:
72 return RREG32_GC_CAC(index);
73 case CGS_IND_REG_SE_CAC:
74 return RREG32_SE_CAC(index);
75 case CGS_IND_REG__AUDIO_ENDPT:
76 DRM_ERROR("audio endpt register access not implemented.\n");
77 return 0;
78 default:
79 BUG();
80 }
81 WARN(1, "Invalid indirect register space");
82 return 0;
83 }
84
amdgpu_cgs_write_ind_register(struct cgs_device * cgs_device,enum cgs_ind_reg space,unsigned int index,uint32_t value)85 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
86 enum cgs_ind_reg space,
87 unsigned int index, uint32_t value)
88 {
89 CGS_FUNC_ADEV;
90 switch (space) {
91 case CGS_IND_REG__PCIE:
92 return WREG32_PCIE(index, value);
93 case CGS_IND_REG__SMC:
94 return WREG32_SMC(index, value);
95 case CGS_IND_REG__UVD_CTX:
96 return WREG32_UVD_CTX(index, value);
97 case CGS_IND_REG__DIDT:
98 return WREG32_DIDT(index, value);
99 case CGS_IND_REG_GC_CAC:
100 return WREG32_GC_CAC(index, value);
101 case CGS_IND_REG_SE_CAC:
102 return WREG32_SE_CAC(index, value);
103 case CGS_IND_REG__AUDIO_ENDPT:
104 DRM_ERROR("audio endpt register access not implemented.\n");
105 return;
106 default:
107 BUG();
108 }
109 WARN(1, "Invalid indirect register space");
110 }
111
fw_type_convert(struct cgs_device * cgs_device,uint32_t fw_type)112 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
113 {
114 CGS_FUNC_ADEV;
115 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
116
117 switch (fw_type) {
118 case CGS_UCODE_ID_SDMA0:
119 result = AMDGPU_UCODE_ID_SDMA0;
120 break;
121 case CGS_UCODE_ID_SDMA1:
122 result = AMDGPU_UCODE_ID_SDMA1;
123 break;
124 case CGS_UCODE_ID_CP_CE:
125 result = AMDGPU_UCODE_ID_CP_CE;
126 break;
127 case CGS_UCODE_ID_CP_PFP:
128 result = AMDGPU_UCODE_ID_CP_PFP;
129 break;
130 case CGS_UCODE_ID_CP_ME:
131 result = AMDGPU_UCODE_ID_CP_ME;
132 break;
133 case CGS_UCODE_ID_CP_MEC:
134 case CGS_UCODE_ID_CP_MEC_JT1:
135 result = AMDGPU_UCODE_ID_CP_MEC1;
136 break;
137 case CGS_UCODE_ID_CP_MEC_JT2:
138 /* for VI. JT2 should be the same as JT1, because:
139 1, MEC2 and MEC1 use exactly same FW.
140 2, JT2 is not pached but JT1 is.
141 */
142 if (adev->asic_type >= CHIP_TOPAZ)
143 result = AMDGPU_UCODE_ID_CP_MEC1;
144 else
145 result = AMDGPU_UCODE_ID_CP_MEC2;
146 break;
147 case CGS_UCODE_ID_RLC_G:
148 result = AMDGPU_UCODE_ID_RLC_G;
149 break;
150 case CGS_UCODE_ID_STORAGE:
151 result = AMDGPU_UCODE_ID_STORAGE;
152 break;
153 default:
154 DRM_ERROR("Firmware type not supported\n");
155 }
156 return result;
157 }
158
amdgpu_get_firmware_version(struct cgs_device * cgs_device,enum cgs_ucode_id type)159 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
160 enum cgs_ucode_id type)
161 {
162 CGS_FUNC_ADEV;
163 uint16_t fw_version = 0;
164
165 switch (type) {
166 case CGS_UCODE_ID_SDMA0:
167 fw_version = adev->sdma.instance[0].fw_version;
168 break;
169 case CGS_UCODE_ID_SDMA1:
170 fw_version = adev->sdma.instance[1].fw_version;
171 break;
172 case CGS_UCODE_ID_CP_CE:
173 fw_version = adev->gfx.ce_fw_version;
174 break;
175 case CGS_UCODE_ID_CP_PFP:
176 fw_version = adev->gfx.pfp_fw_version;
177 break;
178 case CGS_UCODE_ID_CP_ME:
179 fw_version = adev->gfx.me_fw_version;
180 break;
181 case CGS_UCODE_ID_CP_MEC:
182 fw_version = adev->gfx.mec_fw_version;
183 break;
184 case CGS_UCODE_ID_CP_MEC_JT1:
185 fw_version = adev->gfx.mec_fw_version;
186 break;
187 case CGS_UCODE_ID_CP_MEC_JT2:
188 fw_version = adev->gfx.mec_fw_version;
189 break;
190 case CGS_UCODE_ID_RLC_G:
191 fw_version = adev->gfx.rlc_fw_version;
192 break;
193 case CGS_UCODE_ID_STORAGE:
194 break;
195 default:
196 DRM_ERROR("firmware type %d do not have version\n", type);
197 break;
198 }
199 return fw_version;
200 }
201
amdgpu_cgs_get_firmware_info(struct cgs_device * cgs_device,enum cgs_ucode_id type,struct cgs_firmware_info * info)202 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
203 enum cgs_ucode_id type,
204 struct cgs_firmware_info *info)
205 {
206 CGS_FUNC_ADEV;
207
208 if (type != CGS_UCODE_ID_SMU && type != CGS_UCODE_ID_SMU_SK) {
209 uint64_t gpu_addr;
210 uint32_t data_size;
211 const struct gfx_firmware_header_v1_0 *header;
212 enum AMDGPU_UCODE_ID id;
213 struct amdgpu_firmware_info *ucode;
214
215 id = fw_type_convert(cgs_device, type);
216 if (id >= AMDGPU_UCODE_ID_MAXIMUM)
217 return -EINVAL;
218
219 ucode = &adev->firmware.ucode[id];
220 if (ucode->fw == NULL)
221 return -EINVAL;
222
223 gpu_addr = ucode->mc_addr;
224 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
225 data_size = le32_to_cpu(header->header.ucode_size_bytes);
226
227 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
228 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
229 gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
230 data_size = le32_to_cpu(header->jt_size) << 2;
231 }
232
233 info->kptr = ucode->kaddr;
234 info->image_size = data_size;
235 info->mc_addr = gpu_addr;
236 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
237
238 if (type == CGS_UCODE_ID_CP_MEC)
239 info->image_size = le32_to_cpu(header->jt_offset) << 2;
240
241 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
242 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
243 } else {
244 char fw_name[30] = {0};
245 int err = 0;
246 uint32_t ucode_size;
247 uint32_t ucode_start_address;
248 const uint8_t *src;
249 const struct smc_firmware_header_v1_0 *hdr;
250 const struct common_firmware_header *header;
251 struct amdgpu_firmware_info *ucode = NULL;
252
253 if (!adev->pm.fw) {
254 switch (adev->asic_type) {
255 case CHIP_TAHITI:
256 strcpy(fw_name, "radeon/tahiti_smc.bin");
257 break;
258 case CHIP_PITCAIRN:
259 if ((adev->pdev->revision == 0x81) &&
260 ((adev->pdev->device == 0x6810) ||
261 (adev->pdev->device == 0x6811))) {
262 info->is_kicker = true;
263 strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
264 } else {
265 strcpy(fw_name, "radeon/pitcairn_smc.bin");
266 }
267 break;
268 case CHIP_VERDE:
269 if (((adev->pdev->device == 0x6820) &&
270 ((adev->pdev->revision == 0x81) ||
271 (adev->pdev->revision == 0x83))) ||
272 ((adev->pdev->device == 0x6821) &&
273 ((adev->pdev->revision == 0x83) ||
274 (adev->pdev->revision == 0x87))) ||
275 ((adev->pdev->revision == 0x87) &&
276 ((adev->pdev->device == 0x6823) ||
277 (adev->pdev->device == 0x682b)))) {
278 info->is_kicker = true;
279 strcpy(fw_name, "radeon/verde_k_smc.bin");
280 } else {
281 strcpy(fw_name, "radeon/verde_smc.bin");
282 }
283 break;
284 case CHIP_OLAND:
285 if (((adev->pdev->revision == 0x81) &&
286 ((adev->pdev->device == 0x6600) ||
287 (adev->pdev->device == 0x6604) ||
288 (adev->pdev->device == 0x6605) ||
289 (adev->pdev->device == 0x6610))) ||
290 ((adev->pdev->revision == 0x83) &&
291 (adev->pdev->device == 0x6610))) {
292 info->is_kicker = true;
293 strcpy(fw_name, "radeon/oland_k_smc.bin");
294 } else {
295 strcpy(fw_name, "radeon/oland_smc.bin");
296 }
297 break;
298 case CHIP_HAINAN:
299 if (((adev->pdev->revision == 0x81) &&
300 (adev->pdev->device == 0x6660)) ||
301 ((adev->pdev->revision == 0x83) &&
302 ((adev->pdev->device == 0x6660) ||
303 (adev->pdev->device == 0x6663) ||
304 (adev->pdev->device == 0x6665) ||
305 (adev->pdev->device == 0x6667)))) {
306 info->is_kicker = true;
307 strcpy(fw_name, "radeon/hainan_k_smc.bin");
308 } else if ((adev->pdev->revision == 0xc3) &&
309 (adev->pdev->device == 0x6665)) {
310 info->is_kicker = true;
311 strcpy(fw_name, "radeon/banks_k_2_smc.bin");
312 } else {
313 strcpy(fw_name, "radeon/hainan_smc.bin");
314 }
315 break;
316 case CHIP_BONAIRE:
317 if ((adev->pdev->revision == 0x80) ||
318 (adev->pdev->revision == 0x81) ||
319 (adev->pdev->device == 0x665f)) {
320 info->is_kicker = true;
321 strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
322 } else {
323 strcpy(fw_name, "amdgpu/bonaire_smc.bin");
324 }
325 break;
326 case CHIP_HAWAII:
327 if (adev->pdev->revision == 0x80) {
328 info->is_kicker = true;
329 strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
330 } else {
331 strcpy(fw_name, "amdgpu/hawaii_smc.bin");
332 }
333 break;
334 case CHIP_TOPAZ:
335 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
336 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
337 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
338 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
339 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
340 info->is_kicker = true;
341 strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
342 } else
343 strcpy(fw_name, "amdgpu/topaz_smc.bin");
344 break;
345 case CHIP_TONGA:
346 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
347 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
348 info->is_kicker = true;
349 strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
350 } else
351 strcpy(fw_name, "amdgpu/tonga_smc.bin");
352 break;
353 case CHIP_FIJI:
354 strcpy(fw_name, "amdgpu/fiji_smc.bin");
355 break;
356 case CHIP_POLARIS11:
357 if (type == CGS_UCODE_ID_SMU) {
358 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
359 info->is_kicker = true;
360 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
361 } else if (ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
362 info->is_kicker = true;
363 strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
364 } else {
365 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
366 }
367 } else if (type == CGS_UCODE_ID_SMU_SK) {
368 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
369 }
370 break;
371 case CHIP_POLARIS10:
372 if (type == CGS_UCODE_ID_SMU) {
373 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
374 info->is_kicker = true;
375 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
376 } else if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
377 info->is_kicker = true;
378 strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
379 } else {
380 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
381 }
382 } else if (type == CGS_UCODE_ID_SMU_SK) {
383 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
384 }
385 break;
386 case CHIP_POLARIS12:
387 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
388 info->is_kicker = true;
389 strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
390 } else {
391 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
392 }
393 break;
394 case CHIP_VEGAM:
395 strcpy(fw_name, "amdgpu/vegam_smc.bin");
396 break;
397 case CHIP_VEGA10:
398 if ((adev->pdev->device == 0x687f) &&
399 ((adev->pdev->revision == 0xc0) ||
400 (adev->pdev->revision == 0xc1) ||
401 (adev->pdev->revision == 0xc3)))
402 strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
403 else
404 strcpy(fw_name, "amdgpu/vega10_smc.bin");
405 break;
406 case CHIP_VEGA12:
407 strcpy(fw_name, "amdgpu/vega12_smc.bin");
408 break;
409 case CHIP_VEGA20:
410 strcpy(fw_name, "amdgpu/vega20_smc.bin");
411 break;
412 default:
413 DRM_ERROR("SMC firmware not supported\n");
414 return -EINVAL;
415 }
416
417 err = amdgpu_ucode_request(adev, &adev->pm.fw, "%s", fw_name);
418 if (err) {
419 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
420 amdgpu_ucode_release(&adev->pm.fw);
421 return err;
422 }
423
424 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
425 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
426 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
427 ucode->fw = adev->pm.fw;
428 header = (const struct common_firmware_header *)ucode->fw->data;
429 adev->firmware.fw_size +=
430 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
431 }
432 }
433
434 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
435 amdgpu_ucode_print_smc_hdr(&hdr->header);
436 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
437 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
438 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
439 src = (const uint8_t *)(adev->pm.fw->data +
440 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
441
442 info->version = adev->pm.fw_version;
443 info->image_size = ucode_size;
444 info->ucode_start_address = ucode_start_address;
445 info->kptr = (void *)src;
446 }
447 return 0;
448 }
449
450 static const struct cgs_ops amdgpu_cgs_ops = {
451 .read_register = amdgpu_cgs_read_register,
452 .write_register = amdgpu_cgs_write_register,
453 .read_ind_register = amdgpu_cgs_read_ind_register,
454 .write_ind_register = amdgpu_cgs_write_ind_register,
455 .get_firmware_info = amdgpu_cgs_get_firmware_info,
456 };
457
amdgpu_cgs_create_device(struct amdgpu_device * adev)458 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
459 {
460 struct amdgpu_cgs_device *cgs_device =
461 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
462
463 if (!cgs_device) {
464 DRM_ERROR("Couldn't allocate CGS device structure\n");
465 return NULL;
466 }
467
468 cgs_device->base.ops = &amdgpu_cgs_ops;
469 cgs_device->adev = adev;
470
471 return (struct cgs_device *)cgs_device;
472 }
473
amdgpu_cgs_destroy_device(struct cgs_device * cgs_device)474 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
475 {
476 kfree(cgs_device);
477 }
478