130 		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||  in amdgpu_debugfs_process_reg_op()
131 		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {  in amdgpu_debugfs_process_reg_op()
254 		if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||  in amdgpu_debugfs_regs2_op()
255 		    (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {  in amdgpu_debugfs_regs2_op()
429 		if (adev->gfx.funcs->read_wave_data)  in amdgpu_debugfs_gprwave_read()
430 			adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x);  in amdgpu_debugfs_gprwave_read()
434 			if (adev->gfx.funcs->read_wave_vgprs)  in amdgpu_debugfs_gprwave_read()
435 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,…  in amdgpu_debugfs_gprwave_read()
437 			if (adev->gfx.funcs->read_wave_sgprs)  in amdgpu_debugfs_gprwave_read()
438 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat…  in amdgpu_debugfs_gprwave_read()
884 	config[no_regs++] = adev->gfx.config.max_shader_engines;  in amdgpu_debugfs_gca_config_read()
885 	config[no_regs++] = adev->gfx.config.max_tile_pipes;  in amdgpu_debugfs_gca_config_read()
886 	config[no_regs++] = adev->gfx.config.max_cu_per_sh;  in amdgpu_debugfs_gca_config_read()
887 	config[no_regs++] = adev->gfx.config.max_sh_per_se;  in amdgpu_debugfs_gca_config_read()
888 	config[no_regs++] = adev->gfx.config.max_backends_per_se;  in amdgpu_debugfs_gca_config_read()
889 	config[no_regs++] = adev->gfx.config.max_texture_channel_caches;  in amdgpu_debugfs_gca_config_read()
890 	config[no_regs++] = adev->gfx.config.max_gprs;  in amdgpu_debugfs_gca_config_read()
891 	config[no_regs++] = adev->gfx.config.max_gs_threads;  in amdgpu_debugfs_gca_config_read()
892 	config[no_regs++] = adev->gfx.config.max_hw_contexts;  in amdgpu_debugfs_gca_config_read()
893 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;  in amdgpu_debugfs_gca_config_read()
894 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;  in amdgpu_debugfs_gca_config_read()
895 	config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
896 	config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
897 	config[no_regs++] = adev->gfx.config.num_tile_pipes;  in amdgpu_debugfs_gca_config_read()
898 	config[no_regs++] = adev->gfx.config.backend_enable_mask;  in amdgpu_debugfs_gca_config_read()
899 	config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;  in amdgpu_debugfs_gca_config_read()
900 	config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;  in amdgpu_debugfs_gca_config_read()
901 	config[no_regs++] = adev->gfx.config.shader_engine_tile_size;  in amdgpu_debugfs_gca_config_read()
902 	config[no_regs++] = adev->gfx.config.num_gpus;  in amdgpu_debugfs_gca_config_read()
903 	config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;  in amdgpu_debugfs_gca_config_read()
904 	config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;  in amdgpu_debugfs_gca_config_read()
905 	config[no_regs++] = adev->gfx.config.gb_addr_config;  in amdgpu_debugfs_gca_config_read()
906 	config[no_regs++] = adev->gfx.config.num_rbs;  in amdgpu_debugfs_gca_config_read()
1079 	if (adev->gfx.funcs->read_wave_data)  in amdgpu_debugfs_wave_read()
1080 		adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x);  in amdgpu_debugfs_wave_read()
1172 		if (adev->gfx.funcs->read_wave_vgprs)  in amdgpu_debugfs_gpr_read()
1173 			adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data);  in amdgpu_debugfs_gpr_read()
1175 		if (adev->gfx.funcs->read_wave_sgprs)  in amdgpu_debugfs_gpr_read()
1176 			adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data);  in amdgpu_debugfs_gpr_read()
1431 		u32 value = adev->gfx.gfx_off_state;  in amdgpu_debugfs_gfxoff_read()