| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 522 #define dpp_regs(id)\ macro
525 static const struct dcn3_dpp_registers dpp_regs[] = { variable
526 dpp_regs(0),
527 dpp_regs(1),
528 dpp_regs(2),
529 dpp_regs(3),
530 dpp_regs(4)
548 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 403 #define dpp_regs(id)\ macro
408 static const struct dcn3_dpp_registers dpp_regs[] = { variable
409 dpp_regs(0),
410 dpp_regs(1),
411 dpp_regs(2),
412 dpp_regs(3),
726 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 470 #define dpp_regs(id)\ macro
475 static const struct dcn3_dpp_registers dpp_regs[] = { variable
476 dpp_regs(0),
477 dpp_regs(1),
478 dpp_regs(2),
479 dpp_regs(3)
920 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 414 #define dpp_regs(id)\ macro
419 static const struct dcn3_dpp_registers dpp_regs[] = { variable
420 dpp_regs(0),
421 dpp_regs(1),
422 dpp_regs(2),
423 dpp_regs(3),
424 dpp_regs(4),
425 dpp_regs(5),
762 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn30_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 482 #define dpp_regs(id)\ macro
487 static const struct dcn3_dpp_registers dpp_regs[] = { variable
488 dpp_regs(0),
489 dpp_regs(1),
490 dpp_regs(2),
491 dpp_regs(3)
964 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 503 #define dpp_regs(id)\ macro
506 static const struct dcn3_dpp_registers dpp_regs[] = { variable
507 dpp_regs(0),
508 dpp_regs(1)
526 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 479 #define dpp_regs(id)\ macro
484 static const struct dcn3_dpp_registers dpp_regs[] = { variable
485 dpp_regs(0),
486 dpp_regs(1),
487 dpp_regs(2),
488 dpp_regs(3)
927 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 476 #define dpp_regs(id)\ macro
481 static const struct dcn3_dpp_registers dpp_regs[] = { variable
482 dpp_regs(0),
483 dpp_regs(1),
484 dpp_regs(2),
485 dpp_regs(3)
928 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 369 static struct dcn3_dpp_registers dpp_regs[4]; variable
807 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
813 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 388 static struct dcn3_dpp_registers dpp_regs[4]; variable
820 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
826 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 368 static struct dcn3_dpp_registers dpp_regs[4]; variable
800 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
806 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 368 static struct dcn3_dpp_registers dpp_regs[4]; variable
927 #define REG_STRUCT dpp_regs in dcn321_dpp_create()
934 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn321_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 350 static struct dcn401_dpp_registers dpp_regs[4]; variable
959 #define REG_STRUCT dpp_regs in dcn401_dpp_create()
966 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn401_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 369 static struct dcn3_dpp_registers dpp_regs[4]; variable
933 #define REG_STRUCT dpp_regs in dcn32_dpp_create()
940 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn32_dpp_create()
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