| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 640 #define dpp_regs(id)\ macro
643 static const struct dcn3_dpp_registers dpp_regs[] = { variable
644 dpp_regs(0),
645 dpp_regs(1),
646 dpp_regs(2),
647 dpp_regs(3),
648 dpp_regs(4)
666 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 513 #define dpp_regs(id)\ macro
518 static const struct dcn3_dpp_registers dpp_regs[] = { variable
519 dpp_regs(0),
520 dpp_regs(1),
521 dpp_regs(2),
522 dpp_regs(3)
981 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 457 #define dpp_regs(id)\ macro
462 static const struct dcn3_dpp_registers dpp_regs[] = { variable
463 dpp_regs(0),
464 dpp_regs(1),
465 dpp_regs(2),
466 dpp_regs(3),
467 dpp_regs(4),
468 dpp_regs(5),
807 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn30_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 525 #define dpp_regs(id)\ macro
530 static const struct dcn3_dpp_registers dpp_regs[] = { variable
531 dpp_regs(0),
532 dpp_regs(1),
533 dpp_regs(2),
534 dpp_regs(3)
1024 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 621 #define dpp_regs(id)\ macro
624 static const struct dcn3_dpp_registers dpp_regs[] = { variable
625 dpp_regs(0),
626 dpp_regs(1)
644 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 519 #define dpp_regs(id)\ macro
524 static const struct dcn3_dpp_registers dpp_regs[] = { variable
525 dpp_regs(0),
526 dpp_regs(1),
527 dpp_regs(2),
528 dpp_regs(3)
989 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 522 #define dpp_regs(id)\ macro
527 static const struct dcn3_dpp_registers dpp_regs[] = { variable
528 dpp_regs(0),
529 dpp_regs(1),
530 dpp_regs(2),
531 dpp_regs(3)
988 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 406 static struct dcn3_dpp_registers dpp_regs[4]; variable
858 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
864 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 425 static struct dcn3_dpp_registers dpp_regs[4]; variable
871 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
877 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 405 static struct dcn3_dpp_registers dpp_regs[4]; variable
851 #define REG_STRUCT dpp_regs in dcn35_dpp_create()
857 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 405 static struct dcn3_dpp_registers dpp_regs[4]; variable
995 #define REG_STRUCT dpp_regs in dcn321_dpp_create()
1002 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn321_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 402 static struct dcn60_dpp_registers dpp_regs[4]; variable
1176 #define REG_STRUCT dpp_regs in dcn60_dpp_create()
1183 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn60_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 412 static struct dcn42_dpp_registers dpp_regs[4]; variable
1092 #define REG_STRUCT dpp_regs in dcn42b_dpp_create()
1099 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn42b_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 360 static struct dcn42_dpp_registers dpp_regs[4]; variable
1033 #define REG_STRUCT dpp_regs in dcn42_dpp_create()
1040 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn42_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 389 static struct dcn401_dpp_registers dpp_regs[4]; variable
1012 #define REG_STRUCT dpp_regs in dcn401_dpp_create()
1019 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn401_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 412 static struct dcn3_dpp_registers dpp_regs[4]; variable
1007 #define REG_STRUCT dpp_regs in dcn32_dpp_create()
1014 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn32_dpp_create()
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