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Searched refs:dpcd (Results 1 – 25 of 41) sorted by relevance

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/linux/include/drm/display/
H A Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
134 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
135 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
140 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
142 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
146 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
148 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
[all …]
/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c285 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
301 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
327 rd_interval = dpcd[offset]; in __read_delay()
340 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
343 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
347 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
350 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
375 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
377 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
381 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c42 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
78 !drm_dp_read_dpcd_caps(aux, dpcd) && in nouveau_dp_probe_dpcd()
79 !drm_dp_read_lttpr_common_caps(aux, dpcd, outp->dp.lttpr.caps)) { in nouveau_dp_probe_dpcd()
99 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
103 outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_probe_dpcd()
114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && dpcd[DP_DPCD_REV] >= 0x13) { in nouveau_dp_probe_dpcd()
134 outp->dp.rate[j].dpcd = i; in nouveau_dp_probe_dpcd()
143 u32 max_rate = dpcd[DP_MAX_LINK_RATE] * 27000; in nouveau_dp_probe_dpcd()
156 outp->dp.rate[outp->dp.rate_nr].dpcd = -1; in nouveau_dp_probe_dpcd()
[all …]
H A Dnouveau_encoder.h84 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
99 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
150 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { in anx6345_dp_link_training()
151 err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]); in anx6345_dp_link_training()
158 dpcd[0] &= ~DP_SET_POWER_MASK; in anx6345_dp_link_training()
159 dpcd[0] |= DP_SET_POWER_D0; in anx6345_dp_link_training()
161 err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]); in anx6345_dp_link_training()
182 if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx6345_dp_link_training()
201 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) in anx6345_dp_link_training()
[all …]
H A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { in anx78xx_dp_link_training()
664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); in anx78xx_dp_link_training()
671 dpcd[0] &= ~DP_SET_POWER_MASK; in anx78xx_dp_link_training()
672 dpcd[0] |= DP_SET_POWER_D0; in anx78xx_dp_link_training()
674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]); in anx78xx_dp_link_training()
695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx78xx_dp_link_training()
714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c302 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
308 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
309 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
370 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
393 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
394 dig_connector->dpcd); in radeon_dp_getdpcd()
401 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
458 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
485 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c35 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in msm_dp_panel_read_psr_cap()
53 u8 *dpcd, major, minor; in msm_dp_panel_read_dpcd() local
56 dpcd = msm_dp_panel->dpcd; in msm_dp_panel_read_dpcd()
57 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
61 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
63 link_info->revision = dpcd[DP_DPCD_REV]; in msm_dp_panel_read_dpcd()
67 link_info->rate = drm_dp_max_link_rate(dpcd); in msm_dp_panel_read_dpcd()
68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd()
82 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_panel_read_dpcd()
143 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { in msm_dp_panel_read_sink_caps()
[all …]
H A Ddp_ctrl.c140 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl() local
149 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
161 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
1141 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_link_train_1()
1219 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_clear_training_pattern()
1235 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1238 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1253 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_link_train_2()
1278 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train() local
1293 if (drm_dp_max_downspread(dpcd)) in msm_dp_ctrl_link_train()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
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H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
H A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/linux/drivers/gpu/drm/tegra/
H A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c75 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
80 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
91 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
95 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, in intel_dp_read_lttpr_common_caps()
145 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr_phys()
149 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr_phys()
206 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr()
211 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); in intel_dp_init_lttpr()
214 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); in intel_dp_init_lttpr()
221 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_dprx_caps()
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H A Dintel_dp.c170 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
178 return drm_dp_max_lane_count(intel_dp->dpcd); in max_dprx_lane_count()
224 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { in intel_dp_set_dpcd_sink_rates()
1075 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1092 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
1130 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
3111 drm_dp_enhanced_frame_cap(intel_dp->dpcd); in intel_dp_compute_config()
3228 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3229 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
3465 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
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H A Dintel_alpm.c28 u8 dpcd; in intel_alpm_init_dpcd() local
30 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) in intel_alpm_init_dpcd()
33 intel_dp->alpm_dpcd = dpcd; in intel_alpm_init_dpcd()
H A Dintel_dp_link_training.h16 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c263 uint8_t dpcd[4]; member
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
342 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1673 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dite-it6505.c428 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
629 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num) in it6505_get_dpcd() argument
634 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num); in it6505_get_dpcd()
640 num, dpcd); in it6505_get_dpcd()
1451 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01; in it6505_use_step_train_check()
1462 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
1469 link->revision = it6505->dpcd[0]; in it6505_parse_link_capabilities()
1470 link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]); in it6505_parse_link_capabilities()
1471 link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK; in it6505_parse_link_capabilities()
1473 if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP) in it6505_parse_link_capabilities()
[all …]
/linux/drivers/gpu/drm/nouveau/nvif/
H A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train()
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); in nvif_outp_dp_train()
148 args.rate[i].dpcd = rate->dpcd; in nvif_outp_dp_rates()
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1401 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1409 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1414 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1416 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1420 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1426 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1442 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
1448 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1449 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1450 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.h103 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member

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