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Searched refs:dpcd (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
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H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
H A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c73 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in msm_dp_panel_read_psr_cap()
92 u8 *dpcd, major, minor; in msm_dp_panel_read_dpcd() local
95 dpcd = msm_dp_panel->dpcd; in msm_dp_panel_read_dpcd()
96 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
100 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
102 link_info->revision = dpcd[DP_DPCD_REV]; in msm_dp_panel_read_dpcd()
110 link_info->rate = drm_dp_max_link_rate(dpcd); in msm_dp_panel_read_dpcd()
111 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd()
135 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_panel_read_dpcd()
193 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { in msm_dp_panel_read_sink_caps()
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H A Ddp_ctrl.c386 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl() local
395 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
407 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
1422 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1525 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1540 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1546 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1549 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1612 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train() local
1625 if (drm_dp_max_downspread(dpcd)) in msm_dp_ctrl_link_train()
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H A Ddp_panel.h32 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
H A Ddp_display.c372 dp->panel->dpcd, in msm_dp_display_send_hpd_notification()
385 static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd) in msm_dp_display_lttpr_init() argument
389 if (drm_dp_read_lttpr_common_caps(dp->aux, dpcd, dp->link->lttpr_common_caps)) in msm_dp_display_lttpr_init()
407 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in msm_dp_display_process_hpd_high() local
409 rc = drm_dp_read_dpcd_caps(dp->aux, dpcd); in msm_dp_display_process_hpd_high()
413 dp->link->lttpr_count = msm_dp_display_lttpr_init(dp, dpcd); in msm_dp_display_process_hpd_high()
424 dp->panel->dpcd, in msm_dp_display_process_hpd_high()
531 if (drm_dp_is_branch(dp->panel->dpcd) && dp->link->sink_count == 0) { in msm_dp_display_handle_port_status_changed()
/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c213 drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_cr()
266 drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_channel_eq()
330 dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE]; in hibmc_dp_update_caps()
334 dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in hibmc_dp_update_caps()
344 ret = drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); in hibmc_dp_link_training()
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c406 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
787 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_cr()
835 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
836 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
852 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
950 drm_dp_enhanced_frame_cap(dp->dpcd), in zynqmp_dp_train()
951 dp->dpcd[DP_MAX_DOWNSPREAD] & in zynqmp_dp_train()
1700 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in __zynqmp_dp_bridge_detect()
1701 sizeof(dp->dpcd)); in __zynqmp_dp_bridge_detect()
1708 drm_dp_max_link_rate(dp->dpcd), in __zynqmp_dp_bridge_detect()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1331 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1339 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1344 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1346 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1350 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1356 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1372 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
1378 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1379 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1380 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c359 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
843 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
848 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
849 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
850 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
886 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
1194 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1245 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1519 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c543 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], in dm_helpers_dp_mst_start_top_mgr()
544 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); in dm_helpers_dp_mst_start_top_mgr()
H A Damdgpu_dm.c2761 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { in resume_mst_branch_status()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_mode.h470 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h1762 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
H A Dintel_psr.c909 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddisp.c1611 bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP; in nv50_sor_dp_watermark_sst()