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Searched refs:dpcd (Results 1 – 25 of 26) sorted by relevance

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/linux/include/drm/display/
H A Ddrm_dp_helper.h48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
137 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
138 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
143 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
145 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
149 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
151 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
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/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c296 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
312 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
338 rd_interval = dpcd[offset]; in __read_delay()
351 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
354 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
358 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
361 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
386 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
388 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
392 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
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H A Ddrm_dp_mst_topology.c3618 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_mst_cap()
3622 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12) in drm_dp_read_mst_cap()
3661 ret = drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd); in drm_dp_mst_topology_mgr_set_mst()
3811 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { in drm_dp_mst_topology_mgr_resume()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
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H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
H A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c75 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in msm_dp_panel_read_psr_cap()
94 u8 *dpcd, major, minor; in msm_dp_panel_read_dpcd() local
97 dpcd = msm_dp_panel->dpcd; in msm_dp_panel_read_dpcd()
98 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
102 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
104 link_info->revision = dpcd[DP_DPCD_REV]; in msm_dp_panel_read_dpcd()
116 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in msm_dp_panel_read_dpcd()
179 link_info->rate = drm_dp_max_link_rate(dpcd); in msm_dp_panel_read_dpcd()
190 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd()
206 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_panel_read_dpcd()
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H A Ddp_display.c248 static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd) in msm_dp_display_lttpr_init() argument
252 if (drm_dp_read_lttpr_common_caps(dp->aux, dpcd, dp->link->lttpr_common_caps)) in msm_dp_display_lttpr_init()
270 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in msm_dp_display_process_hpd_high() local
273 rc = drm_dp_read_dpcd_caps(dp->aux, dpcd); in msm_dp_display_process_hpd_high()
277 dp->link->lttpr_count = msm_dp_display_lttpr_init(dp, dpcd); in msm_dp_display_process_hpd_high()
298 dp->panel->dpcd, in msm_dp_display_process_hpd_high()
480 dp->panel->dpcd, in msm_dp_hpd_unplug_handle()
896 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in msm_dp_bridge_detect() local
924 ret = drm_dp_read_dpcd_caps(priv->aux, dpcd); in msm_dp_bridge_detect()
931 ret = drm_dp_read_desc(priv->aux, &desc, drm_dp_is_branch(dpcd)); in msm_dp_bridge_detect()
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H A Ddp_ctrl.c424 const u8 *dpcd = panel->dpcd; in msm_dp_ctrl_config_ctrl_link() local
430 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in msm_dp_ctrl_config_ctrl_link()
437 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_ctrl_config_ctrl_link()
1457 panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1568 panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1584 panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1590 if (drm_dp_tps4_supported(panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1593 } else if (drm_dp_tps3_supported(panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1658 const u8 *dpcd = panel->dpcd; in msm_dp_ctrl_link_train() local
1672 if (drm_dp_max_downspread(dpcd)) in msm_dp_ctrl_link_train()
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H A Ddp_panel.h32 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c476 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
481 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
492 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
496 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, in intel_dp_read_lttpr_common_caps()
543 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr_phys()
548 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr_phys()
593 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr()
598 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); in intel_dp_init_lttpr()
601 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); in intel_dp_init_lttpr()
608 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_dprx_caps()
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H A Dintel_dp.c166 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
185 return drm_dp_max_lane_count(intel_dp->dpcd); in max_dprx_lane_count()
199 return drm_dp_128b132b_supported(intel_dp->dpcd); in dprx_supports_128b132b()
1006 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1023 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
1061 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
3112 if (drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_needs_as_sdp()
3602 drm_dp_enhanced_frame_cap(intel_dp->dpcd); in intel_dp_compute_config()
3729 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3730 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
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H A Dintel_psr.c496 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { in _psr_compute_su_granularity()
534 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; in compute_pr_dsc_support()
571 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & in _panel_replay_compute_su_granularity()
582 …w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPL… in _panel_replay_compute_su_granularity()
583 …y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ?… in _panel_replay_compute_su_granularity()
607 &connector->dp.panel_replay_caps.dpcd, in _panel_replay_init_dpcd()
608 sizeof(connector->dp.panel_replay_caps.dpcd)); in _panel_replay_init_dpcd()
612 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
623 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
634 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
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H A Dintel_dp_mst.c536 drm_dp_128b132b_supported(connector->mst.dp->dpcd); in hblank_expansion_quirk_needs_dsc()
1775 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in detect_dsc_hblank_expansion_quirk() local
1790 if (drm_dp_read_dpcd_caps(aux, dpcd) < 0) in detect_dsc_hblank_expansion_quirk()
1793 if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0) in detect_dsc_hblank_expansion_quirk()
1806 if (!drm_dp_128b132b_supported(dpcd) && in detect_dsc_hblank_expansion_quirk()
1807 !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) in detect_dsc_hblank_expansion_quirk()
2222 drm_dp_enhanced_frame_cap(intel_dp->dpcd), false); in intel_dp_mst_prepare_probe()
H A Dintel_display_types.h577 u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE]; member
589 u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; member
1832 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
H A Dintel_vrr.c69 if (drm_dp_is_branch(intel_dp->dpcd)) in intel_vrr_is_capable()
72 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) in intel_vrr_is_capable()
H A Dintel_lt_phy.c1341 return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); in intel_lt_phy_pll_is_ssc_enabled()
H A Dintel_cx0_phy.c1994 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); in intel_cx0pll_update_ssc()
/linux/drivers/gpu/drm/nouveau/nvif/
H A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train()
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); in nvif_outp_dp_train()
148 args.rate[i].dpcd = rate->dpcd; in nvif_outp_dp_rates()
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Ddisp.c975 if (outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) in r535_dp_train_target()
979 (outp->dp.dpcd[DPCD_RC02] & 0x20) && in r535_dp_train_target()
980 !(outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)) in r535_dp_train_target()
1049 ctrl->linkRateTbl[outp->dp.rate[i].dpcd] = outp->dp.rate[i].rate * 10 / 200; in r535_dp_set_indexed_link_rates()
1060 !outp->dp.rates || outp->dp.rate[0].dpcd < 0) in r535_dp_rates()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/
H A Ddisp.c155 ctrl->linkRateTbl[outp->dp.rate[i].dpcd] = outp->dp.rate[i].rate * 10 / 200; in r570_dp_set_indexed_link_rates()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c630 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], in dm_helpers_dp_mst_start_top_mgr()
631 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); in dm_helpers_dp_mst_start_top_mgr()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_connectors.c1491 amdgpu_dig_connector->dpcd, in amdgpu_connector_dp_detect()

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