178 	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);  in max_dprx_rate()
186 	return drm_dp_max_lane_count(intel_dp->dpcd);  in max_dprx_lane_count()
232 	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {  in intel_dp_set_dpcd_sink_rates()
1096 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_rgb()
1113 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_ycbcr444()
1151 		    (!drm_dp_is_branch(intel_dp->dpcd) ||  in intel_dp_output_format()
3146 			drm_dp_enhanced_frame_cap(intel_dp->dpcd);  in intel_dp_compute_config()
3264 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&  in downstream_hpd_needs_d0()
3265 		drm_dp_is_branch(intel_dp->dpcd) &&  in downstream_hpd_needs_d0()
3502 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_set_power()
3561 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {  in intel_dp_sync_state()
3775 	if (drm_dp_is_branch(intel_dp->dpcd) &&  in intel_dp_is_hdmi_2_1_sink()
3942 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)  in intel_dp_configure_protocol_converter()
3945 	if (!drm_dp_is_branch(intel_dp->dpcd))  in intel_dp_configure_protocol_converter()
4076 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],  in intel_dp_detect_dsc_caps()
4149 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {  in intel_edp_mso_init()
4157 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,  in intel_edp_mso_init()
4215 	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);  in intel_edp_init_dpcd()
4217 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)  in intel_edp_init_dpcd()
4221 			 drm_dp_is_branch(intel_dp->dpcd));  in intel_edp_init_dpcd()
4274 					  intel_dp->dpcd,  in intel_dp_has_sink_count()
4299 				 drm_dp_is_branch(intel_dp->dpcd));  in intel_dp_get_dpcd()
4332 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,  in intel_dp_get_dpcd()
4359 	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))  in intel_dp_mst_mode_choose()
4373 	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_mst_detect()
5269 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_device_service_irq()
5294 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_link_service_irq()
5373 	u8 *dpcd = intel_dp->dpcd;  in intel_dp_detect_dpcd()  local
5387 	if (!drm_dp_is_branch(dpcd))  in intel_dp_detect_dpcd()
5405 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in intel_dp_detect_dpcd()
5411 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in intel_dp_detect_dpcd()
5518 		drm_dp_downstream_max_bpc(intel_dp->dpcd,  in intel_dp_update_dfp()
5522 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,  in intel_dp_update_dfp()
5526 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5530 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5535 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,  in intel_dp_update_dfp()
5554 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))  in intel_dp_can_ycbcr420()
5575 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,  in intel_dp_update_420()
5580 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5583 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5653 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_detect_sdp_caps()
5787 						 intel_dp->dpcd,  in intel_dp_detect()
5836 					      intel_dp->dpcd,  in intel_dp_get_modes()
6149 	u8 dpcd[DP_RECEIVER_CAP_SIZE];  in intel_dp_hpd_pulse()  local
6183 		intel_dp_read_dprx_caps(intel_dp, dpcd);  in intel_dp_hpd_pulse()
6404 		if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&  in intel_edp_init_connector()
6405 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==  in intel_edp_init_connector()