| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 545 static struct dccg_registers dccg_regs; variable
1976 #define REG_STRUCT dccg_regs in dcn36_resource_construct()
2146 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn36_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 558 static struct dccg_registers dccg_regs; variable
2006 #define REG_STRUCT dccg_regs in dcn35_resource_construct()
2176 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn35_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 538 static struct dccg_registers dccg_regs; variable
1979 #define REG_STRUCT dccg_regs in dcn351_resource_construct()
2148 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn351_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 544 static struct dccg_registers dccg_regs; variable
1831 #define REG_STRUCT dccg_regs in dcn321_resource_construct()
2022 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 1258 static const struct dccg_registers dccg_regs = { variable
1427 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 1314 static const struct dccg_registers dccg_regs = { variable
1495 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 514 static struct dccg_registers dccg_regs; variable
1983 #define REG_STRUCT dccg_regs in dcn60_resource_construct()
2173 pool->base.dccg = dccg60_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn60_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 532 static struct dccg_registers dccg_regs; variable
1968 #define REG_STRUCT dccg_regs in dcn42b_resource_construct()
2197 pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn42b_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 482 static struct dccg_registers dccg_regs; variable
1992 #define REG_STRUCT dccg_regs in dcn42_resource_construct()
2223 pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn42_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 527 static struct dccg_registers dccg_regs; variable
2041 #define REG_STRUCT dccg_regs in dcn401_resource_construct()
2248 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 554 static struct dccg_registers dccg_regs; variable
2336 #define REG_STRUCT dccg_regs in dcn32_resource_construct()
2529 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn32_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 696 static const struct dccg_registers dccg_regs = { variable
2043 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 709 static const struct dccg_registers dccg_regs = { variable
2140 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn314_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 702 static const struct dccg_registers dccg_regs = { variable
2219 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 701 static const struct dccg_registers dccg_regs = { variable
2172 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 657 static const struct dccg_registers dccg_regs = { variable
2602 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn30_resource_construct()
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