Searched refs:RREG32_PCIE (Results 1 – 16 of 16) sorted by relevance
71 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_correctable_error_count()86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_uncorrectable_error_count()133 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_14_err_cnt_init_per_channel()
192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()257 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()267 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()402 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
281 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()286 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()296 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()378 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()391 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()499 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
1227 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()1234 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()1243 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()1250 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()1259 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()1261 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()1268 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()1270 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
308 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel()
1058 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) macro
94 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()96 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()179 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()199 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()538 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()556 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()572 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info_show()[all …]
130 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
123 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
2223 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()2243 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega12_get_current_pcie_link_speed_level()
3314 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_get_current_pcie_link_width_level()3334 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega20_get_current_pcie_link_speed_level()
992 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v15_0_8_check_fw_status()
412 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_7_check_fw_status()