1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SWSMU_CODE_LAYER_L3
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v15_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "amdgpu_ras.h"
39 #include "smu_cmn.h"
40
41 #include "asic_reg/thm/thm_15_0_0_offset.h"
42 #include "asic_reg/thm/thm_15_0_0_sh_mask.h"
43 #include "asic_reg/mp/mp_15_0_0_offset.h"
44 #include "asic_reg/mp/mp_15_0_0_sh_mask.h"
45
46 #define regMP1_SMN_IH_SW_INT_mp1_15_0_0 0x0341
47 #define regMP1_SMN_IH_SW_INT_mp1_15_0_0_BASE_IDX 0
48 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0 0x0342
49 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0_BASE_IDX 0
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
62
smu_v15_0_init_microcode(struct smu_context * smu)63 int smu_v15_0_init_microcode(struct smu_context *smu)
64 {
65 struct amdgpu_device *adev = smu->adev;
66 char ucode_prefix[15];
67 int err = 0;
68 const struct smc_firmware_header_v1_0 *hdr;
69 const struct common_firmware_header *header;
70 struct amdgpu_firmware_info *ucode = NULL;
71
72 /* doesn't need to load smu firmware in IOV mode */
73 if (amdgpu_sriov_vf(adev))
74 return 0;
75
76 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
77 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
78 "amdgpu/%s.bin", ucode_prefix);
79 if (err)
80 goto out;
81
82 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
83 amdgpu_ucode_print_smc_hdr(&hdr->header);
84 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
85
86 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
87 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
88 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
89 ucode->fw = adev->pm.fw;
90 header = (const struct common_firmware_header *)ucode->fw->data;
91 adev->firmware.fw_size +=
92 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
93 }
94
95 out:
96 if (err)
97 amdgpu_ucode_release(&adev->pm.fw);
98 return err;
99 }
100
smu_v15_0_fini_microcode(struct smu_context * smu)101 void smu_v15_0_fini_microcode(struct smu_context *smu)
102 {
103 struct amdgpu_device *adev = smu->adev;
104
105 amdgpu_ucode_release(&adev->pm.fw);
106 adev->pm.fw_version = 0;
107 }
108
smu_v15_0_load_microcode(struct smu_context * smu)109 int smu_v15_0_load_microcode(struct smu_context *smu)
110 {
111 struct amdgpu_device *adev = smu->adev;
112 const uint32_t *src;
113 const struct smc_firmware_header_v1_0 *hdr;
114 uint32_t addr_start = MP1_SRAM;
115 uint32_t i;
116 uint32_t smc_fw_size;
117 uint32_t mp1_fw_flags;
118
119 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
120 src = (const uint32_t *)(adev->pm.fw->data +
121 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
122 smc_fw_size = hdr->header.ucode_size_bytes;
123
124 for (i = 1; i < smc_fw_size/4 - 1; i++) {
125 WREG32_PCIE(addr_start, src[i]);
126 addr_start += 4;
127 }
128
129
130 for (i = 0; i < adev->usec_timeout; i++) {
131 if (smu->is_apu)
132 mp1_fw_flags = RREG32_PCIE(MP1_Public |
133 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
134
135 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
136 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
137 break;
138 udelay(1);
139 }
140
141 if (i == adev->usec_timeout)
142 return -ETIME;
143
144 return 0;
145 }
146
smu_v15_0_init_pptable_microcode(struct smu_context * smu)147 int smu_v15_0_init_pptable_microcode(struct smu_context *smu)
148 {
149 struct amdgpu_device *adev = smu->adev;
150 struct amdgpu_firmware_info *ucode = NULL;
151 uint32_t size = 0, pptable_id = 0;
152 int ret = 0;
153 void *table;
154
155 /* doesn't need to load smu firmware in IOV mode */
156 if (amdgpu_sriov_vf(adev))
157 return 0;
158
159 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
160 return 0;
161
162 if (!adev->scpm_enabled)
163 return 0;
164
165 /* override pptable_id from driver parameter */
166 if (amdgpu_smu_pptable_id >= 0) {
167 pptable_id = amdgpu_smu_pptable_id;
168 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
169 } else {
170 pptable_id = smu->smu_table.boot_values.pp_table_id;
171 }
172
173 /* "pptable_id == 0" means vbios carries the pptable. */
174 if (!pptable_id)
175 return 0;
176
177 ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
178 if (ret)
179 return ret;
180
181 smu->pptable_firmware.data = table;
182 smu->pptable_firmware.size = size;
183
184 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
185 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
186 ucode->fw = &smu->pptable_firmware;
187 adev->firmware.fw_size +=
188 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
189
190 return 0;
191 }
192
smu_v15_0_check_fw_status(struct smu_context * smu)193 int smu_v15_0_check_fw_status(struct smu_context *smu)
194 {
195 struct amdgpu_device *adev = smu->adev;
196 uint32_t mp1_fw_flags = 0;
197
198 if (smu->is_apu)
199 mp1_fw_flags = RREG32_PCIE(MP1_Public |
200 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
201
202
203 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
204 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
205 return 0;
206
207 return -EIO;
208 }
209
smu_v15_0_check_fw_version(struct smu_context * smu)210 int smu_v15_0_check_fw_version(struct smu_context *smu)
211 {
212 struct amdgpu_device *adev = smu->adev;
213 uint32_t if_version = 0xff, smu_version = 0xff;
214 uint8_t smu_program, smu_major, smu_minor, smu_debug;
215 int ret = 0;
216
217 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
218 if (ret)
219 return ret;
220
221 smu_program = (smu_version >> 24) & 0xff;
222 smu_major = (smu_version >> 16) & 0xff;
223 smu_minor = (smu_version >> 8) & 0xff;
224 smu_debug = (smu_version >> 0) & 0xff;
225 if (smu->is_apu)
226 adev->pm.fw_version = smu_version;
227
228 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
229 case IP_VERSION(15, 0, 0):
230 smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0;
231 break;
232 default:
233 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
234 amdgpu_ip_version(adev, MP1_HWIP, 0));
235 smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_INV;
236 break;
237 }
238
239 if (adev->pm.fw)
240 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
241 smu_program, smu_version, smu_major, smu_minor, smu_debug);
242
243 /*
244 * 1. if_version mismatch is not critical as our fw is designed
245 * to be backward compatible.
246 * 2. New fw usually brings some optimizations. But that's visible
247 * only on the paired driver.
248 * Considering above, we just leave user a verbal message instead
249 * of halt driver loading.
250 */
251 if (if_version != smu->smc_driver_if_version) {
252 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
253 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
254 smu->smc_driver_if_version, if_version,
255 smu_program, smu_version, smu_major, smu_minor, smu_debug);
256 dev_info(adev->dev, "SMU driver if version not matched\n");
257 }
258
259 return ret;
260 }
261
smu_v15_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)262 static int smu_v15_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
263 {
264 struct amdgpu_device *adev = smu->adev;
265 uint32_t ppt_offset_bytes;
266 const struct smc_firmware_header_v2_0 *v2;
267
268 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
269
270 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
271 *size = le32_to_cpu(v2->ppt_size_bytes);
272 *table = (uint8_t *)v2 + ppt_offset_bytes;
273
274 return 0;
275 }
276
smu_v15_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)277 static int smu_v15_0_set_pptable_v2_1(struct smu_context *smu, void **table,
278 uint32_t *size, uint32_t pptable_id)
279 {
280 struct amdgpu_device *adev = smu->adev;
281 const struct smc_firmware_header_v2_1 *v2_1;
282 struct smc_soft_pptable_entry *entries;
283 uint32_t pptable_count = 0;
284 int i = 0;
285
286 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
287 entries = (struct smc_soft_pptable_entry *)
288 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
289 pptable_count = le32_to_cpu(v2_1->pptable_count);
290 for (i = 0; i < pptable_count; i++) {
291 if (le32_to_cpu(entries[i].id) == pptable_id) {
292 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
293 *size = le32_to_cpu(entries[i].ppt_size_bytes);
294 break;
295 }
296 }
297
298 if (i == pptable_count)
299 return -EINVAL;
300
301 return 0;
302 }
303
smu_v15_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)304 static int smu_v15_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
305 {
306 struct amdgpu_device *adev = smu->adev;
307 uint16_t atom_table_size;
308 uint8_t frev, crev;
309 int ret, index;
310
311 dev_info(adev->dev, "use vbios provided pptable\n");
312 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
313 powerplayinfo);
314
315 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
316 (uint8_t **)table);
317 if (ret)
318 return ret;
319
320 if (size)
321 *size = atom_table_size;
322
323 return 0;
324 }
325
smu_v15_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)326 int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu,
327 void **table,
328 uint32_t *size,
329 uint32_t pptable_id)
330 {
331 const struct smc_firmware_header_v1_0 *hdr;
332 struct amdgpu_device *adev = smu->adev;
333 uint16_t version_major, version_minor;
334 int ret;
335
336 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
337 if (!hdr)
338 return -EINVAL;
339
340 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
341
342 version_major = le16_to_cpu(hdr->header.header_version_major);
343 version_minor = le16_to_cpu(hdr->header.header_version_minor);
344 if (version_major != 2) {
345 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
346 version_major, version_minor);
347 return -EINVAL;
348 }
349
350 switch (version_minor) {
351 case 0:
352 ret = smu_v15_0_set_pptable_v2_0(smu, table, size);
353 break;
354 case 1:
355 ret = smu_v15_0_set_pptable_v2_1(smu, table, size, pptable_id);
356 break;
357 default:
358 ret = -EINVAL;
359 break;
360 }
361
362 return ret;
363 }
364
smu_v15_0_setup_pptable(struct smu_context * smu)365 int smu_v15_0_setup_pptable(struct smu_context *smu)
366 {
367 struct amdgpu_device *adev = smu->adev;
368 uint32_t size = 0, pptable_id = 0;
369 void *table;
370 int ret = 0;
371
372 /* override pptable_id from driver parameter */
373 if (amdgpu_smu_pptable_id >= 0) {
374 pptable_id = amdgpu_smu_pptable_id;
375 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
376 } else {
377 pptable_id = smu->smu_table.boot_values.pp_table_id;
378 }
379
380 /* force using vbios pptable in sriov mode */
381 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
382 ret = smu_v15_0_get_pptable_from_vbios(smu, &table, &size);
383 else
384 ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
385
386 if (ret)
387 return ret;
388
389 if (!smu->smu_table.power_play_table)
390 smu->smu_table.power_play_table = table;
391 if (!smu->smu_table.power_play_table_size)
392 smu->smu_table.power_play_table_size = size;
393
394 return 0;
395 }
396
smu_v15_0_init_smc_tables(struct smu_context * smu)397 int smu_v15_0_init_smc_tables(struct smu_context *smu)
398 {
399 struct smu_table_context *smu_table = &smu->smu_table;
400 struct smu_table *tables = smu_table->tables;
401 int ret = 0;
402
403 smu_table->driver_pptable =
404 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
405 if (!smu_table->driver_pptable) {
406 ret = -ENOMEM;
407 goto err0_out;
408 }
409
410 smu_table->max_sustainable_clocks =
411 kzalloc_obj(struct smu_15_0_max_sustainable_clocks);
412 if (!smu_table->max_sustainable_clocks) {
413 ret = -ENOMEM;
414 goto err1_out;
415 }
416
417 if (tables[SMU_TABLE_OVERDRIVE].size) {
418 smu_table->overdrive_table =
419 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
420 if (!smu_table->overdrive_table) {
421 ret = -ENOMEM;
422 goto err2_out;
423 }
424
425 smu_table->boot_overdrive_table =
426 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
427 if (!smu_table->boot_overdrive_table) {
428 ret = -ENOMEM;
429 goto err3_out;
430 }
431
432 smu_table->user_overdrive_table =
433 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
434 if (!smu_table->user_overdrive_table) {
435 ret = -ENOMEM;
436 goto err4_out;
437 }
438 }
439
440 smu_table->combo_pptable =
441 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
442 if (!smu_table->combo_pptable) {
443 ret = -ENOMEM;
444 goto err5_out;
445 }
446
447 return 0;
448
449 err5_out:
450 kfree(smu_table->user_overdrive_table);
451 err4_out:
452 kfree(smu_table->boot_overdrive_table);
453 err3_out:
454 kfree(smu_table->overdrive_table);
455 err2_out:
456 kfree(smu_table->max_sustainable_clocks);
457 err1_out:
458 kfree(smu_table->driver_pptable);
459 err0_out:
460 return ret;
461 }
462
smu_v15_0_fini_smc_tables(struct smu_context * smu)463 int smu_v15_0_fini_smc_tables(struct smu_context *smu)
464 {
465 struct smu_table_context *smu_table = &smu->smu_table;
466 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
467
468 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
469 kfree(smu_table->combo_pptable);
470 kfree(smu_table->boot_overdrive_table);
471 kfree(smu_table->overdrive_table);
472 kfree(smu_table->max_sustainable_clocks);
473 kfree(smu_table->driver_pptable);
474 smu_table->combo_pptable = NULL;
475 smu_table->boot_overdrive_table = NULL;
476 smu_table->overdrive_table = NULL;
477 smu_table->max_sustainable_clocks = NULL;
478 smu_table->driver_pptable = NULL;
479 kfree(smu_table->hardcode_pptable);
480 smu_table->hardcode_pptable = NULL;
481
482 kfree(smu_table->ecc_table);
483 kfree(smu_table->metrics_table);
484 kfree(smu_table->watermarks_table);
485 smu_table->ecc_table = NULL;
486 smu_table->metrics_table = NULL;
487 smu_table->watermarks_table = NULL;
488 smu_table->metrics_time = 0;
489
490 kfree(smu_dpm->dpm_context);
491 kfree(smu_dpm->golden_dpm_context);
492 kfree(smu_dpm->dpm_current_power_state);
493 kfree(smu_dpm->dpm_request_power_state);
494 smu_dpm->dpm_context = NULL;
495 smu_dpm->golden_dpm_context = NULL;
496 smu_dpm->dpm_context_size = 0;
497 smu_dpm->dpm_current_power_state = NULL;
498 smu_dpm->dpm_request_power_state = NULL;
499
500 return 0;
501 }
502
smu_v15_0_init_power(struct smu_context * smu)503 int smu_v15_0_init_power(struct smu_context *smu)
504 {
505 struct smu_power_context *smu_power = &smu->smu_power;
506
507 if (smu_power->power_context || smu_power->power_context_size != 0)
508 return -EINVAL;
509
510 smu_power->power_context = kzalloc_obj(struct smu_15_0_dpm_context);
511 if (!smu_power->power_context)
512 return -ENOMEM;
513 smu_power->power_context_size = sizeof(struct smu_15_0_dpm_context);
514
515 return 0;
516 }
517
smu_v15_0_fini_power(struct smu_context * smu)518 int smu_v15_0_fini_power(struct smu_context *smu)
519 {
520 struct smu_power_context *smu_power = &smu->smu_power;
521
522 if (!smu_power->power_context || smu_power->power_context_size == 0)
523 return -EINVAL;
524
525 kfree(smu_power->power_context);
526 smu_power->power_context = NULL;
527 smu_power->power_context_size = 0;
528
529 return 0;
530 }
531
smu_v15_0_get_vbios_bootup_values(struct smu_context * smu)532 int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu)
533 {
534 int ret, index;
535 uint16_t size;
536 uint8_t frev, crev;
537 struct atom_common_table_header *header;
538 struct atom_firmware_info_v3_4 *v_3_4;
539 struct atom_firmware_info_v3_3 *v_3_3;
540 struct atom_firmware_info_v3_1 *v_3_1;
541 struct atom_smu_info_v3_6 *smu_info_v3_6;
542 struct atom_smu_info_v4_0 *smu_info_v4_0;
543
544 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
545 firmwareinfo);
546
547 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
548 (uint8_t **)&header);
549 if (ret)
550 return ret;
551
552 if (header->format_revision != 3) {
553 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu15\n");
554 return -EINVAL;
555 }
556
557 switch (header->content_revision) {
558 case 0:
559 case 1:
560 case 2:
561 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
562 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
563 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
564 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
565 smu->smu_table.boot_values.socclk = 0;
566 smu->smu_table.boot_values.dcefclk = 0;
567 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
568 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
569 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
570 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
571 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
572 smu->smu_table.boot_values.pp_table_id = 0;
573 break;
574 case 3:
575 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
576 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
577 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
578 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
579 smu->smu_table.boot_values.socclk = 0;
580 smu->smu_table.boot_values.dcefclk = 0;
581 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
582 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
583 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
584 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
585 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
586 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
587 break;
588 case 4:
589 default:
590 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
591 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
592 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
593 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
594 smu->smu_table.boot_values.socclk = 0;
595 smu->smu_table.boot_values.dcefclk = 0;
596 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
597 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
598 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
599 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
600 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
601 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
602 break;
603 }
604
605 smu->smu_table.boot_values.format_revision = header->format_revision;
606 smu->smu_table.boot_values.content_revision = header->content_revision;
607
608 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
609 smu_info);
610 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
611 (uint8_t **)&header)) {
612
613 if ((frev == 3) && (crev == 6)) {
614 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
615
616 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
617 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
618 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
619 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
620 } else if ((frev == 3) && (crev == 1)) {
621 return 0;
622 } else if ((frev == 4) && (crev == 0)) {
623 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
624
625 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
626 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
627 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
628 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
629 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
630 } else {
631 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
632 (uint32_t)frev, (uint32_t)crev);
633 }
634 }
635
636 return 0;
637 }
638
639
smu_v15_0_notify_memory_pool_location(struct smu_context * smu)640 int smu_v15_0_notify_memory_pool_location(struct smu_context *smu)
641 {
642 struct smu_table_context *smu_table = &smu->smu_table;
643 struct smu_table *memory_pool = &smu_table->memory_pool;
644 int ret = 0;
645 uint64_t address;
646 uint32_t address_low, address_high;
647
648 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
649 return ret;
650
651 address = memory_pool->mc_address;
652 address_high = (uint32_t)upper_32_bits(address);
653 address_low = (uint32_t)lower_32_bits(address);
654
655 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
656 address_high, NULL);
657 if (ret)
658 return ret;
659 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
660 address_low, NULL);
661 if (ret)
662 return ret;
663 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
664 (uint32_t)memory_pool->size, NULL);
665 if (ret)
666 return ret;
667
668 return ret;
669 }
670
smu_v15_0_set_driver_table_location(struct smu_context * smu)671 int smu_v15_0_set_driver_table_location(struct smu_context *smu)
672 {
673 struct smu_table *driver_table = &smu->smu_table.driver_table;
674 int ret = 0;
675
676 if (driver_table->mc_address) {
677 ret = smu_cmn_send_smc_msg_with_param(smu,
678 SMU_MSG_SetDriverDramAddrHigh,
679 upper_32_bits(driver_table->mc_address),
680 NULL);
681 if (!ret)
682 ret = smu_cmn_send_smc_msg_with_param(smu,
683 SMU_MSG_SetDriverDramAddrLow,
684 lower_32_bits(driver_table->mc_address),
685 NULL);
686 }
687
688 return ret;
689 }
690
smu_v15_0_set_tool_table_location(struct smu_context * smu)691 int smu_v15_0_set_tool_table_location(struct smu_context *smu)
692 {
693 int ret = 0;
694 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
695
696 if (tool_table->mc_address) {
697 ret = smu_cmn_send_smc_msg_with_param(smu,
698 SMU_MSG_SetToolsDramAddrHigh,
699 upper_32_bits(tool_table->mc_address),
700 NULL);
701 if (!ret)
702 ret = smu_cmn_send_smc_msg_with_param(smu,
703 SMU_MSG_SetToolsDramAddrLow,
704 lower_32_bits(tool_table->mc_address),
705 NULL);
706 }
707
708 return ret;
709 }
710
smu_v15_0_set_allowed_mask(struct smu_context * smu)711 int smu_v15_0_set_allowed_mask(struct smu_context *smu)
712 {
713 struct smu_feature *feature = &smu->smu_feature;
714 int ret = 0;
715 uint32_t feature_mask[2];
716
717 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
718 feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
719 return -EINVAL;
720
721 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
722
723 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
724 feature_mask[1], NULL);
725 if (ret)
726 return ret;
727
728 return smu_cmn_send_smc_msg_with_param(smu,
729 SMU_MSG_SetAllowedFeaturesMaskLow,
730 feature_mask[0],
731 NULL);
732 }
733
smu_v15_0_gfx_off_control(struct smu_context * smu,bool enable)734 int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable)
735 {
736 int ret = 0;
737 struct amdgpu_device *adev = smu->adev;
738
739 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
740 case IP_VERSION(15, 0, 0):
741 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
742 return 0;
743 if (enable)
744 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
745 else
746 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
747 break;
748 default:
749 break;
750 }
751
752 return ret;
753 }
754
smu_v15_0_system_features_control(struct smu_context * smu,bool en)755 int smu_v15_0_system_features_control(struct smu_context *smu,
756 bool en)
757 {
758 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
759 SMU_MSG_DisableAllSmuFeatures), NULL);
760 }
761
smu_v15_0_notify_display_change(struct smu_context * smu)762 int smu_v15_0_notify_display_change(struct smu_context *smu)
763 {
764 int ret = 0;
765
766 if (!smu->pm_enabled)
767 return ret;
768
769 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
770 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
771 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
772
773 return ret;
774 }
775
smu_v15_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)776 int smu_v15_0_get_current_power_limit(struct smu_context *smu,
777 uint32_t *power_limit)
778 {
779 int power_src;
780 int ret = 0;
781
782 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
783 return -EINVAL;
784
785 power_src = smu_cmn_to_asic_specific_index(smu,
786 CMN2ASIC_MAPPING_PWR,
787 smu->adev->pm.ac_power ?
788 SMU_POWER_SOURCE_AC :
789 SMU_POWER_SOURCE_DC);
790 if (power_src < 0)
791 return -EINVAL;
792
793 ret = smu_cmn_send_smc_msg_with_param(smu,
794 SMU_MSG_GetPptLimit,
795 power_src << 16,
796 power_limit);
797 if (ret)
798 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
799
800 return ret;
801 }
802
smu_v15_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)803 int smu_v15_0_set_power_limit(struct smu_context *smu,
804 enum smu_ppt_limit_type limit_type,
805 uint32_t limit)
806 {
807 int ret = 0;
808
809 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
810 return -EINVAL;
811
812 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
813 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
814 return -EOPNOTSUPP;
815 }
816
817 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
818 if (ret) {
819 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
820 return ret;
821 }
822
823 smu->current_power_limit = limit;
824
825 return 0;
826 }
827
smu_v15_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)828 static int smu_v15_0_set_irq_state(struct amdgpu_device *adev,
829 struct amdgpu_irq_src *source,
830 unsigned tyep,
831 enum amdgpu_interrupt_state state)
832 {
833 struct smu_context *smu = adev->powerplay.pp_handle;
834 uint32_t val = 0;
835
836 switch (state) {
837 case AMDGPU_IRQ_STATE_DISABLE:
838
839 /* For MP1 SW irqs */
840 if (smu->is_apu) {
841 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0);
842 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
843 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val);
844 } else {
845 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
846 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
847 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
848 }
849
850 break;
851 case AMDGPU_IRQ_STATE_ENABLE:
852 /* For MP1 SW irqs */
853 if (smu->is_apu) {
854 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0);
855 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
856 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
857 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0, val);
858
859 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0);
860 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
861 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val);
862 } else {
863 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
864 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
865 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
866 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
867
868 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
869 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
870 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
871 }
872
873 break;
874 default:
875 break;
876 }
877
878 return 0;
879 }
880
881 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
882 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
883
smu_v15_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)884 static int smu_v15_0_irq_process(struct amdgpu_device *adev,
885 struct amdgpu_irq_src *source,
886 struct amdgpu_iv_entry *entry)
887 {
888 struct smu_context *smu = adev->powerplay.pp_handle;
889 uint32_t client_id = entry->client_id;
890 uint32_t src_id = entry->src_id;
891
892 if (client_id == SOC15_IH_CLIENTID_THM) {
893 switch (src_id) {
894 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
895 schedule_delayed_work(&smu->swctf_delayed_work,
896 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
897 break;
898 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
899 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
900 break;
901 default:
902 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
903 src_id);
904 break;
905 }
906 }
907
908 return 0;
909 }
910
911 static const struct amdgpu_irq_src_funcs smu_v15_0_irq_funcs = {
912 .set = smu_v15_0_set_irq_state,
913 .process = smu_v15_0_irq_process,
914 };
915
smu_v15_0_register_irq_handler(struct smu_context * smu)916 int smu_v15_0_register_irq_handler(struct smu_context *smu)
917 {
918 struct amdgpu_device *adev = smu->adev;
919 struct amdgpu_irq_src *irq_src = &smu->irq_source;
920 int ret = 0;
921
922 if (amdgpu_sriov_vf(adev))
923 return 0;
924
925 irq_src->num_types = 1;
926 irq_src->funcs = &smu_v15_0_irq_funcs;
927
928 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
929 THM_11_0__SRCID__THM_DIG_THERM_L2H,
930 irq_src);
931 if (ret)
932 return ret;
933
934 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
935 THM_11_0__SRCID__THM_DIG_THERM_H2L,
936 irq_src);
937 if (ret)
938 return ret;
939
940 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
941 SMU_IH_INTERRUPT_ID_TO_DRIVER,
942 irq_src);
943 if (ret)
944 return ret;
945
946 return ret;
947 }
948
smu_v15_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)949 static int smu_v15_0_wait_for_reset_complete(struct smu_context *smu,
950 uint64_t event_arg)
951 {
952 int ret = 0;
953
954 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
955 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
956
957 return ret;
958 }
959
smu_v15_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)960 int smu_v15_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
961 uint64_t event_arg)
962 {
963 int ret = -EINVAL;
964
965 switch (event) {
966 case SMU_EVENT_RESET_COMPLETE:
967 ret = smu_v15_0_wait_for_reset_complete(smu, event_arg);
968 break;
969 default:
970 break;
971 }
972
973 return ret;
974 }
975
smu_v15_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)976 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
977 uint32_t *min, uint32_t *max)
978 {
979 int ret = 0, clk_id = 0;
980 uint32_t param = 0;
981 uint32_t clock_limit;
982
983 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
984 switch (clk_type) {
985 case SMU_MCLK:
986 case SMU_UCLK:
987 clock_limit = smu->smu_table.boot_values.uclk;
988 break;
989 case SMU_GFXCLK:
990 case SMU_SCLK:
991 clock_limit = smu->smu_table.boot_values.gfxclk;
992 break;
993 case SMU_SOCCLK:
994 clock_limit = smu->smu_table.boot_values.socclk;
995 break;
996 default:
997 clock_limit = 0;
998 break;
999 }
1000
1001 /* clock in Mhz unit */
1002 if (min)
1003 *min = clock_limit / 100;
1004 if (max)
1005 *max = clock_limit / 100;
1006
1007 return 0;
1008 }
1009
1010 clk_id = smu_cmn_to_asic_specific_index(smu,
1011 CMN2ASIC_MAPPING_CLK,
1012 clk_type);
1013 if (clk_id < 0) {
1014 ret = -EINVAL;
1015 goto failed;
1016 }
1017 param = (clk_id & 0xffff) << 16;
1018
1019 if (max) {
1020 if (smu->adev->pm.ac_power)
1021 ret = smu_cmn_send_smc_msg_with_param(smu,
1022 SMU_MSG_GetMaxDpmFreq,
1023 param,
1024 max);
1025 else
1026 ret = smu_cmn_send_smc_msg_with_param(smu,
1027 SMU_MSG_GetDcModeMaxDpmFreq,
1028 param,
1029 max);
1030 if (ret)
1031 goto failed;
1032 }
1033
1034 if (min) {
1035 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1036 if (ret)
1037 goto failed;
1038 }
1039
1040 failed:
1041 return ret;
1042 }
1043
smu_v15_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1044 int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu,
1045 enum smu_clk_type clk_type,
1046 uint32_t min,
1047 uint32_t max,
1048 bool automatic)
1049 {
1050 int ret = 0, clk_id = 0;
1051 uint32_t param;
1052
1053 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1054 return 0;
1055
1056 clk_id = smu_cmn_to_asic_specific_index(smu,
1057 CMN2ASIC_MAPPING_CLK,
1058 clk_type);
1059 if (clk_id < 0)
1060 return clk_id;
1061
1062 if (max > 0) {
1063 if (automatic)
1064 param = (uint32_t)((clk_id << 16) | 0xffff);
1065 else
1066 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1067 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1068 param, NULL);
1069 if (ret)
1070 goto out;
1071 }
1072
1073 if (min > 0) {
1074 if (automatic)
1075 param = (uint32_t)((clk_id << 16) | 0);
1076 else
1077 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1078 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1079 param, NULL);
1080 if (ret)
1081 goto out;
1082 }
1083
1084 out:
1085 return ret;
1086 }
1087
smu_v15_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1088 int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu,
1089 enum smu_clk_type clk_type,
1090 uint32_t min,
1091 uint32_t max)
1092 {
1093 int ret = 0, clk_id = 0;
1094 uint32_t param;
1095
1096 if (min <= 0 && max <= 0)
1097 return -EINVAL;
1098
1099 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1100 return 0;
1101
1102 clk_id = smu_cmn_to_asic_specific_index(smu,
1103 CMN2ASIC_MAPPING_CLK,
1104 clk_type);
1105 if (clk_id < 0)
1106 return clk_id;
1107
1108 if (max > 0) {
1109 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1110 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1111 param, NULL);
1112 if (ret)
1113 return ret;
1114 }
1115
1116 if (min > 0) {
1117 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1118 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1119 param, NULL);
1120 if (ret)
1121 return ret;
1122 }
1123
1124 return ret;
1125 }
1126
smu_v15_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1127 int smu_v15_0_set_performance_level(struct smu_context *smu,
1128 enum amd_dpm_forced_level level)
1129 {
1130 struct smu_15_0_dpm_context *dpm_context =
1131 smu->smu_dpm.dpm_context;
1132 struct smu_15_0_dpm_table *gfx_table =
1133 &dpm_context->dpm_tables.gfx_table;
1134 struct smu_15_0_dpm_table *mem_table =
1135 &dpm_context->dpm_tables.uclk_table;
1136 struct smu_15_0_dpm_table *soc_table =
1137 &dpm_context->dpm_tables.soc_table;
1138 struct smu_15_0_dpm_table *vclk_table =
1139 &dpm_context->dpm_tables.vclk_table;
1140 struct smu_15_0_dpm_table *dclk_table =
1141 &dpm_context->dpm_tables.dclk_table;
1142 struct smu_15_0_dpm_table *fclk_table =
1143 &dpm_context->dpm_tables.fclk_table;
1144 struct smu_umd_pstate_table *pstate_table =
1145 &smu->pstate_table;
1146 struct amdgpu_device *adev = smu->adev;
1147 uint32_t sclk_min = 0, sclk_max = 0;
1148 uint32_t mclk_min = 0, mclk_max = 0;
1149 uint32_t socclk_min = 0, socclk_max = 0;
1150 uint32_t vclk_min = 0, vclk_max = 0;
1151 uint32_t dclk_min = 0, dclk_max = 0;
1152 uint32_t fclk_min = 0, fclk_max = 0;
1153 int ret = 0, i;
1154 bool auto_level = false;
1155
1156 switch (level) {
1157 case AMD_DPM_FORCED_LEVEL_HIGH:
1158 sclk_min = sclk_max = gfx_table->max;
1159 mclk_min = mclk_max = mem_table->max;
1160 socclk_min = socclk_max = soc_table->max;
1161 vclk_min = vclk_max = vclk_table->max;
1162 dclk_min = dclk_max = dclk_table->max;
1163 fclk_min = fclk_max = fclk_table->max;
1164 break;
1165 case AMD_DPM_FORCED_LEVEL_LOW:
1166 sclk_min = sclk_max = gfx_table->min;
1167 mclk_min = mclk_max = mem_table->min;
1168 socclk_min = socclk_max = soc_table->min;
1169 vclk_min = vclk_max = vclk_table->min;
1170 dclk_min = dclk_max = dclk_table->min;
1171 fclk_min = fclk_max = fclk_table->min;
1172 break;
1173 case AMD_DPM_FORCED_LEVEL_AUTO:
1174 sclk_min = gfx_table->min;
1175 sclk_max = gfx_table->max;
1176 mclk_min = mem_table->min;
1177 mclk_max = mem_table->max;
1178 socclk_min = soc_table->min;
1179 socclk_max = soc_table->max;
1180 vclk_min = vclk_table->min;
1181 vclk_max = vclk_table->max;
1182 dclk_min = dclk_table->min;
1183 dclk_max = dclk_table->max;
1184 fclk_min = fclk_table->min;
1185 fclk_max = fclk_table->max;
1186 auto_level = true;
1187 break;
1188 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1189 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1190 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1191 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1192 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1193 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1194 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1195 break;
1196 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1197 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1198 break;
1199 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1200 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1201 break;
1202 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1203 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1204 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1205 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1206 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1207 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1208 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1209 break;
1210 case AMD_DPM_FORCED_LEVEL_MANUAL:
1211 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1212 return 0;
1213 default:
1214 dev_err(adev->dev, "Invalid performance level %d\n", level);
1215 return -EINVAL;
1216 }
1217
1218 if (sclk_min && sclk_max) {
1219 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1220 SMU_GFXCLK,
1221 sclk_min,
1222 sclk_max,
1223 auto_level);
1224 if (ret)
1225 return ret;
1226
1227 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1228 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1229 }
1230
1231 if (mclk_min && mclk_max) {
1232 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1233 SMU_MCLK,
1234 mclk_min,
1235 mclk_max,
1236 auto_level);
1237 if (ret)
1238 return ret;
1239
1240 pstate_table->uclk_pstate.curr.min = mclk_min;
1241 pstate_table->uclk_pstate.curr.max = mclk_max;
1242 }
1243
1244 if (socclk_min && socclk_max) {
1245 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1246 SMU_SOCCLK,
1247 socclk_min,
1248 socclk_max,
1249 auto_level);
1250 if (ret)
1251 return ret;
1252
1253 pstate_table->socclk_pstate.curr.min = socclk_min;
1254 pstate_table->socclk_pstate.curr.max = socclk_max;
1255 }
1256
1257 if (vclk_min && vclk_max) {
1258 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1259 if (adev->vcn.harvest_config & (1 << i))
1260 continue;
1261 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1262 i ? SMU_VCLK1 : SMU_VCLK,
1263 vclk_min,
1264 vclk_max,
1265 auto_level);
1266 if (ret)
1267 return ret;
1268 }
1269 pstate_table->vclk_pstate.curr.min = vclk_min;
1270 pstate_table->vclk_pstate.curr.max = vclk_max;
1271 }
1272
1273 if (dclk_min && dclk_max) {
1274 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1275 if (adev->vcn.harvest_config & (1 << i))
1276 continue;
1277 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1278 i ? SMU_DCLK1 : SMU_DCLK,
1279 dclk_min,
1280 dclk_max,
1281 auto_level);
1282 if (ret)
1283 return ret;
1284 }
1285 pstate_table->dclk_pstate.curr.min = dclk_min;
1286 pstate_table->dclk_pstate.curr.max = dclk_max;
1287 }
1288
1289 if (fclk_min && fclk_max) {
1290 ret = smu_v15_0_set_soft_freq_limited_range(smu,
1291 SMU_FCLK,
1292 fclk_min,
1293 fclk_max,
1294 auto_level);
1295 if (ret)
1296 return ret;
1297
1298 pstate_table->fclk_pstate.curr.min = fclk_min;
1299 pstate_table->fclk_pstate.curr.max = fclk_max;
1300 }
1301
1302 return ret;
1303 }
1304
smu_v15_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1305 int smu_v15_0_set_power_source(struct smu_context *smu,
1306 enum smu_power_src_type power_src)
1307 {
1308 int pwr_source;
1309
1310 pwr_source = smu_cmn_to_asic_specific_index(smu,
1311 CMN2ASIC_MAPPING_PWR,
1312 (uint32_t)power_src);
1313 if (pwr_source < 0)
1314 return -EINVAL;
1315
1316 return smu_cmn_send_smc_msg_with_param(smu,
1317 SMU_MSG_NotifyPowerSource,
1318 pwr_source,
1319 NULL);
1320 }
1321
smu_v15_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1322 static int smu_v15_0_get_dpm_freq_by_index(struct smu_context *smu,
1323 enum smu_clk_type clk_type,
1324 uint16_t level,
1325 uint32_t *value)
1326 {
1327 int ret = 0, clk_id = 0;
1328 uint32_t param;
1329
1330 if (!value)
1331 return -EINVAL;
1332
1333 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1334 return 0;
1335
1336 clk_id = smu_cmn_to_asic_specific_index(smu,
1337 CMN2ASIC_MAPPING_CLK,
1338 clk_type);
1339 if (clk_id < 0)
1340 return clk_id;
1341
1342 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1343
1344 ret = smu_cmn_send_smc_msg_with_param(smu,
1345 SMU_MSG_GetDpmFreqByIndex,
1346 param,
1347 value);
1348 if (ret)
1349 return ret;
1350
1351 *value = *value & 0x7fffffff;
1352
1353 return ret;
1354 }
1355
smu_v15_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1356 static int smu_v15_0_get_dpm_level_count(struct smu_context *smu,
1357 enum smu_clk_type clk_type,
1358 uint32_t *value)
1359 {
1360 int ret;
1361
1362 ret = smu_v15_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1363
1364 return ret;
1365 }
1366
smu_v15_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1367 static int smu_v15_0_get_fine_grained_status(struct smu_context *smu,
1368 enum smu_clk_type clk_type,
1369 bool *is_fine_grained_dpm)
1370 {
1371 int ret = 0, clk_id = 0;
1372 uint32_t param;
1373 uint32_t value;
1374
1375 if (!is_fine_grained_dpm)
1376 return -EINVAL;
1377
1378 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1379 return 0;
1380
1381 clk_id = smu_cmn_to_asic_specific_index(smu,
1382 CMN2ASIC_MAPPING_CLK,
1383 clk_type);
1384 if (clk_id < 0)
1385 return clk_id;
1386
1387 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1388
1389 ret = smu_cmn_send_smc_msg_with_param(smu,
1390 SMU_MSG_GetDpmFreqByIndex,
1391 param,
1392 &value);
1393 if (ret)
1394 return ret;
1395
1396 /*
1397 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1398 * now, we un-support it
1399 */
1400 *is_fine_grained_dpm = value & 0x80000000;
1401
1402 return 0;
1403 }
1404
smu_v15_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_15_0_dpm_table * single_dpm_table)1405 int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
1406 enum smu_clk_type clk_type,
1407 struct smu_15_0_dpm_table *single_dpm_table)
1408 {
1409 int ret = 0;
1410 uint32_t clk;
1411 int i;
1412
1413 ret = smu_v15_0_get_dpm_level_count(smu,
1414 clk_type,
1415 &single_dpm_table->count);
1416 if (ret) {
1417 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1418 return ret;
1419 }
1420
1421 ret = smu_v15_0_get_fine_grained_status(smu,
1422 clk_type,
1423 &single_dpm_table->is_fine_grained);
1424 if (ret) {
1425 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1426 return ret;
1427 }
1428
1429 for (i = 0; i < single_dpm_table->count; i++) {
1430 ret = smu_v15_0_get_dpm_freq_by_index(smu,
1431 clk_type,
1432 i,
1433 &clk);
1434 if (ret) {
1435 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1436 return ret;
1437 }
1438
1439 single_dpm_table->dpm_levels[i].value = clk;
1440 single_dpm_table->dpm_levels[i].enabled = true;
1441
1442 if (i == 0)
1443 single_dpm_table->min = clk;
1444 else if (i == single_dpm_table->count - 1)
1445 single_dpm_table->max = clk;
1446 }
1447
1448 return 0;
1449 }
1450
smu_v15_0_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1451 int smu_v15_0_set_vcn_enable(struct smu_context *smu,
1452 bool enable,
1453 int inst)
1454 {
1455 struct amdgpu_device *adev = smu->adev;
1456 int ret = 0;
1457
1458 if (adev->vcn.harvest_config & (1 << inst))
1459 return ret;
1460
1461 if (smu->is_apu) {
1462 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1463 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1464 inst << 16U, NULL);
1465 }
1466
1467 return ret;
1468 }
1469
smu_v15_0_set_jpeg_enable(struct smu_context * smu,bool enable)1470 int smu_v15_0_set_jpeg_enable(struct smu_context *smu,
1471 bool enable)
1472 {
1473 struct amdgpu_device *adev = smu->adev;
1474 int i, ret = 0;
1475
1476 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
1477 if (adev->jpeg.harvest_config & (1 << i))
1478 continue;
1479
1480 if (smu->is_apu) {
1481 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1482 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1483 i << 16U, NULL);
1484 }
1485
1486 if (ret)
1487 return ret;
1488 }
1489
1490 return ret;
1491 }
1492
smu_v15_0_run_btc(struct smu_context * smu)1493 int smu_v15_0_run_btc(struct smu_context *smu)
1494 {
1495 int res;
1496
1497 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1498 if (res)
1499 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1500
1501 return res;
1502 }
1503
smu_v15_0_gpo_control(struct smu_context * smu,bool enablement)1504 int smu_v15_0_gpo_control(struct smu_context *smu,
1505 bool enablement)
1506 {
1507 int res;
1508
1509 res = smu_cmn_send_smc_msg_with_param(smu,
1510 SMU_MSG_AllowGpo,
1511 enablement ? 1 : 0,
1512 NULL);
1513 if (res)
1514 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1515
1516 return res;
1517 }
1518
smu_v15_0_deep_sleep_control(struct smu_context * smu,bool enablement)1519 int smu_v15_0_deep_sleep_control(struct smu_context *smu,
1520 bool enablement)
1521 {
1522 struct amdgpu_device *adev = smu->adev;
1523 int ret = 0;
1524
1525 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1526 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1527 if (ret) {
1528 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
1529 return ret;
1530 }
1531 }
1532
1533 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1534 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1535 if (ret) {
1536 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
1537 return ret;
1538 }
1539 }
1540
1541 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1542 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1543 if (ret) {
1544 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
1545 return ret;
1546 }
1547 }
1548
1549 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1550 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1551 if (ret) {
1552 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
1553 return ret;
1554 }
1555 }
1556
1557 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1558 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1559 if (ret) {
1560 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
1561 return ret;
1562 }
1563 }
1564
1565 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1566 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1567 if (ret) {
1568 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
1569 return ret;
1570 }
1571 }
1572
1573 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1574 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1575 if (ret) {
1576 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
1577 return ret;
1578 }
1579 }
1580
1581 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1582 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1583 if (ret) {
1584 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
1585 return ret;
1586 }
1587 }
1588
1589 return ret;
1590 }
1591
smu_v15_0_gfx_ulv_control(struct smu_context * smu,bool enablement)1592 int smu_v15_0_gfx_ulv_control(struct smu_context *smu,
1593 bool enablement)
1594 {
1595 int ret = 0;
1596
1597 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1598 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1599
1600 return ret;
1601 }
1602
smu_v15_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1603 int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu,
1604 enum smu_baco_seq baco_seq)
1605 {
1606 struct smu_baco_context *smu_baco = &smu->smu_baco;
1607 int ret;
1608
1609 ret = smu_cmn_send_smc_msg_with_param(smu,
1610 SMU_MSG_ArmD3,
1611 baco_seq,
1612 NULL);
1613 if (ret)
1614 return ret;
1615
1616 if (baco_seq == BACO_SEQ_BAMACO ||
1617 baco_seq == BACO_SEQ_BACO)
1618 smu_baco->state = SMU_BACO_STATE_ENTER;
1619 else
1620 smu_baco->state = SMU_BACO_STATE_EXIT;
1621
1622 return 0;
1623 }
1624
smu_v15_0_get_bamaco_support(struct smu_context * smu)1625 int smu_v15_0_get_bamaco_support(struct smu_context *smu)
1626 {
1627 struct smu_baco_context *smu_baco = &smu->smu_baco;
1628 int bamaco_support = 0;
1629
1630 if (amdgpu_sriov_vf(smu->adev) ||
1631 !smu_baco->platform_support)
1632 return 0;
1633
1634 if (smu_baco->maco_support)
1635 bamaco_support |= MACO_SUPPORT;
1636
1637 /* return true if ASIC is in BACO state already */
1638 if (smu_v15_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1639 return (bamaco_support |= BACO_SUPPORT);
1640
1641 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1642 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1643 return 0;
1644
1645 return (bamaco_support |= BACO_SUPPORT);
1646 }
1647
smu_v15_0_baco_get_state(struct smu_context * smu)1648 enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu)
1649 {
1650 struct smu_baco_context *smu_baco = &smu->smu_baco;
1651
1652 return smu_baco->state;
1653 }
1654
smu_v15_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1655 int smu_v15_0_baco_set_state(struct smu_context *smu,
1656 enum smu_baco_state state)
1657 {
1658 struct smu_baco_context *smu_baco = &smu->smu_baco;
1659 struct amdgpu_device *adev = smu->adev;
1660 int ret = 0;
1661
1662 if (smu_v15_0_baco_get_state(smu) == state)
1663 return 0;
1664
1665 if (state == SMU_BACO_STATE_ENTER) {
1666 ret = smu_cmn_send_smc_msg_with_param(smu,
1667 SMU_MSG_EnterBaco,
1668 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
1669 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
1670 NULL);
1671 } else {
1672 ret = smu_cmn_send_smc_msg(smu,
1673 SMU_MSG_ExitBaco,
1674 NULL);
1675 if (ret)
1676 return ret;
1677
1678 /* clear vbios scratch 6 and 7 for coming asic reinit */
1679 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1680 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1681 }
1682
1683 if (!ret)
1684 smu_baco->state = state;
1685
1686 return ret;
1687 }
1688
smu_v15_0_baco_enter(struct smu_context * smu)1689 int smu_v15_0_baco_enter(struct smu_context *smu)
1690 {
1691 int ret = 0;
1692
1693 ret = smu_v15_0_baco_set_state(smu,
1694 SMU_BACO_STATE_ENTER);
1695 if (ret)
1696 return ret;
1697
1698 msleep(10);
1699
1700 return ret;
1701 }
1702
smu_v15_0_baco_exit(struct smu_context * smu)1703 int smu_v15_0_baco_exit(struct smu_context *smu)
1704 {
1705 return smu_v15_0_baco_set_state(smu,
1706 SMU_BACO_STATE_EXIT);
1707 }
1708
smu_v15_0_set_gfx_power_up_by_imu(struct smu_context * smu)1709 int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1710 {
1711 struct smu_msg_ctl *ctl = &smu->msg_ctl;
1712 struct amdgpu_device *adev = smu->adev;
1713 int ret;
1714
1715 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1716 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
1717 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
1718 }
1719
1720 mutex_lock(&ctl->lock);
1721 ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
1722 ENABLE_IMU_ARG_GFXOFF_ENABLE);
1723 mutex_unlock(&ctl->lock);
1724
1725 return ret;
1726 }
1727
smu_v15_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1728 int smu_v15_0_od_edit_dpm_table(struct smu_context *smu,
1729 enum PP_OD_DPM_TABLE_COMMAND type,
1730 long input[], uint32_t size)
1731 {
1732 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1733 int ret = 0;
1734
1735 /* Only allowed in manual mode */
1736 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1737 return -EINVAL;
1738
1739 switch (type) {
1740 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1741 if (size != 2) {
1742 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1743 return -EINVAL;
1744 }
1745
1746 if (input[0] == 0) {
1747 if (input[1] < smu->gfx_default_hard_min_freq) {
1748 dev_warn(smu->adev->dev,
1749 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1750 input[1], smu->gfx_default_hard_min_freq);
1751 return -EINVAL;
1752 }
1753 smu->gfx_actual_hard_min_freq = input[1];
1754 } else if (input[0] == 1) {
1755 if (input[1] > smu->gfx_default_soft_max_freq) {
1756 dev_warn(smu->adev->dev,
1757 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1758 input[1], smu->gfx_default_soft_max_freq);
1759 return -EINVAL;
1760 }
1761 smu->gfx_actual_soft_max_freq = input[1];
1762 } else {
1763 return -EINVAL;
1764 }
1765 break;
1766 case PP_OD_RESTORE_DEFAULT_TABLE:
1767 if (size != 0) {
1768 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1769 return -EINVAL;
1770 }
1771 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1772 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1773 break;
1774 case PP_OD_COMMIT_DPM_TABLE:
1775 if (size != 0) {
1776 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1777 return -EINVAL;
1778 }
1779 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1780 dev_err(smu->adev->dev,
1781 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1782 smu->gfx_actual_hard_min_freq,
1783 smu->gfx_actual_soft_max_freq);
1784 return -EINVAL;
1785 }
1786
1787 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1788 smu->gfx_actual_hard_min_freq,
1789 NULL);
1790 if (ret) {
1791 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1792 return ret;
1793 }
1794
1795 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1796 smu->gfx_actual_soft_max_freq,
1797 NULL);
1798 if (ret) {
1799 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1800 return ret;
1801 }
1802 break;
1803 default:
1804 return -ENOSYS;
1805 }
1806
1807 return ret;
1808 }
1809
smu_v15_0_allow_ih_interrupt(struct smu_context * smu)1810 static int smu_v15_0_allow_ih_interrupt(struct smu_context *smu)
1811 {
1812 return smu_cmn_send_smc_msg(smu,
1813 SMU_MSG_AllowIHHostInterrupt,
1814 NULL);
1815 }
1816
smu_v15_0_enable_thermal_alert(struct smu_context * smu)1817 int smu_v15_0_enable_thermal_alert(struct smu_context *smu)
1818 {
1819 int ret = 0;
1820
1821 if (!smu->irq_source.num_types)
1822 return 0;
1823
1824 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1825 if (ret)
1826 return ret;
1827
1828 return smu_v15_0_allow_ih_interrupt(smu);
1829 }
1830
smu_v15_0_disable_thermal_alert(struct smu_context * smu)1831 int smu_v15_0_disable_thermal_alert(struct smu_context *smu)
1832 {
1833 if (!smu->irq_source.num_types)
1834 return 0;
1835
1836 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1837 }
1838