1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68 #define SMU11_VOLTAGE_SCALE 4
69
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81
smu_v11_0_poll_baco_exit(struct smu_context * smu)82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
83 {
84 struct amdgpu_device *adev = smu->adev;
85 uint32_t data, loop = 0;
86
87 do {
88 usleep_range(1000, 1100);
89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
90 } while ((data & 0x100) && (++loop < 100));
91 }
92
smu_v11_0_init_microcode(struct smu_context * smu)93 int smu_v11_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[25];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 if (amdgpu_sriov_vf(adev) &&
103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) ||
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7))))
105 return 0;
106
107 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
108 err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
109 if (err)
110 goto out;
111
112 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
113 amdgpu_ucode_print_smc_hdr(&hdr->header);
114 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
115
116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
117 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
118 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
119 ucode->fw = adev->pm.fw;
120 header = (const struct common_firmware_header *)ucode->fw->data;
121 adev->firmware.fw_size +=
122 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
123 }
124
125 out:
126 if (err)
127 amdgpu_ucode_release(&adev->pm.fw);
128 return err;
129 }
130
smu_v11_0_fini_microcode(struct smu_context * smu)131 void smu_v11_0_fini_microcode(struct smu_context *smu)
132 {
133 struct amdgpu_device *adev = smu->adev;
134
135 amdgpu_ucode_release(&adev->pm.fw);
136 adev->pm.fw_version = 0;
137 }
138
smu_v11_0_load_microcode(struct smu_context * smu)139 int smu_v11_0_load_microcode(struct smu_context *smu)
140 {
141 struct amdgpu_device *adev = smu->adev;
142 const uint32_t *src;
143 const struct smc_firmware_header_v1_0 *hdr;
144 uint32_t addr_start = MP1_SRAM;
145 uint32_t i;
146 uint32_t smc_fw_size;
147 uint32_t mp1_fw_flags;
148
149 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
150 src = (const uint32_t *)(adev->pm.fw->data +
151 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
152 smc_fw_size = hdr->header.ucode_size_bytes;
153
154 for (i = 1; i < smc_fw_size/4 - 1; i++) {
155 WREG32_PCIE(addr_start, src[i]);
156 addr_start += 4;
157 }
158
159 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
160 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
162 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
163
164 for (i = 0; i < adev->usec_timeout; i++) {
165 mp1_fw_flags = RREG32_PCIE(MP1_Public |
166 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
167 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
168 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
169 break;
170 udelay(1);
171 }
172
173 if (i == adev->usec_timeout)
174 return -ETIME;
175
176 return 0;
177 }
178
smu_v11_0_check_fw_status(struct smu_context * smu)179 int smu_v11_0_check_fw_status(struct smu_context *smu)
180 {
181 struct amdgpu_device *adev = smu->adev;
182 uint32_t mp1_fw_flags;
183
184 mp1_fw_flags = RREG32_PCIE(MP1_Public |
185 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
186
187 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
188 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
189 return 0;
190
191 return -EIO;
192 }
193
smu_v11_0_check_fw_version(struct smu_context * smu)194 int smu_v11_0_check_fw_version(struct smu_context *smu)
195 {
196 struct amdgpu_device *adev = smu->adev;
197 uint32_t if_version = 0xff, smu_version = 0xff;
198 uint8_t smu_program, smu_major, smu_minor, smu_debug;
199 int ret = 0;
200
201 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
202 if (ret)
203 return ret;
204
205 smu_program = (smu_version >> 24) & 0xff;
206 smu_major = (smu_version >> 16) & 0xff;
207 smu_minor = (smu_version >> 8) & 0xff;
208 smu_debug = (smu_version >> 0) & 0xff;
209 if (smu->is_apu)
210 adev->pm.fw_version = smu_version;
211
212 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
213 case IP_VERSION(11, 0, 0):
214 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
215 break;
216 case IP_VERSION(11, 0, 9):
217 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
218 break;
219 case IP_VERSION(11, 0, 5):
220 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
221 break;
222 case IP_VERSION(11, 0, 7):
223 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
224 break;
225 case IP_VERSION(11, 0, 11):
226 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
227 break;
228 case IP_VERSION(11, 5, 0):
229 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
230 break;
231 case IP_VERSION(11, 0, 12):
232 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
233 break;
234 case IP_VERSION(11, 0, 13):
235 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
236 break;
237 case IP_VERSION(11, 0, 8):
238 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
239 break;
240 case IP_VERSION(11, 0, 2):
241 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
242 break;
243 default:
244 dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
245 amdgpu_ip_version(adev, MP1_HWIP, 0));
246 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
247 break;
248 }
249
250 /*
251 * 1. if_version mismatch is not critical as our fw is designed
252 * to be backward compatible.
253 * 2. New fw usually brings some optimizations. But that's visible
254 * only on the paired driver.
255 * Considering above, we just leave user a verbal message instead
256 * of halt driver loading.
257 */
258 if (if_version != smu->smc_driver_if_version) {
259 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
260 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
261 smu->smc_driver_if_version, if_version,
262 smu_program, smu_version, smu_major, smu_minor, smu_debug);
263 dev_info(smu->adev->dev, "SMU driver if version not matched\n");
264 }
265
266 return ret;
267 }
268
smu_v11_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)269 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
270 {
271 struct amdgpu_device *adev = smu->adev;
272 uint32_t ppt_offset_bytes;
273 const struct smc_firmware_header_v2_0 *v2;
274
275 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
276
277 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
278 *size = le32_to_cpu(v2->ppt_size_bytes);
279 *table = (uint8_t *)v2 + ppt_offset_bytes;
280
281 return 0;
282 }
283
smu_v11_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)284 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
285 uint32_t *size, uint32_t pptable_id)
286 {
287 struct amdgpu_device *adev = smu->adev;
288 const struct smc_firmware_header_v2_1 *v2_1;
289 struct smc_soft_pptable_entry *entries;
290 uint32_t pptable_count = 0;
291 int i = 0;
292
293 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
294 entries = (struct smc_soft_pptable_entry *)
295 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
296 pptable_count = le32_to_cpu(v2_1->pptable_count);
297 for (i = 0; i < pptable_count; i++) {
298 if (le32_to_cpu(entries[i].id) == pptable_id) {
299 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
300 *size = le32_to_cpu(entries[i].ppt_size_bytes);
301 break;
302 }
303 }
304
305 if (i == pptable_count)
306 return -EINVAL;
307
308 return 0;
309 }
310
smu_v11_0_setup_pptable(struct smu_context * smu)311 int smu_v11_0_setup_pptable(struct smu_context *smu)
312 {
313 struct amdgpu_device *adev = smu->adev;
314 const struct smc_firmware_header_v1_0 *hdr;
315 int ret, index;
316 uint32_t size = 0;
317 uint16_t atom_table_size;
318 uint8_t frev, crev;
319 void *table;
320 uint16_t version_major, version_minor;
321
322 if (!amdgpu_sriov_vf(adev)) {
323 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
324 version_major = le16_to_cpu(hdr->header.header_version_major);
325 version_minor = le16_to_cpu(hdr->header.header_version_minor);
326 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
327 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
328 switch (version_minor) {
329 case 0:
330 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
331 break;
332 case 1:
333 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
334 smu->smu_table.boot_values.pp_table_id);
335 break;
336 default:
337 ret = -EINVAL;
338 break;
339 }
340 if (ret)
341 return ret;
342 goto out;
343 }
344 }
345
346 dev_info(adev->dev, "use vbios provided pptable\n");
347 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
348 powerplayinfo);
349
350 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
351 (uint8_t **)&table);
352 if (ret)
353 return ret;
354 size = atom_table_size;
355
356 out:
357 if (!smu->smu_table.power_play_table)
358 smu->smu_table.power_play_table = table;
359 if (!smu->smu_table.power_play_table_size)
360 smu->smu_table.power_play_table_size = size;
361
362 return 0;
363 }
364
smu_v11_0_init_smc_tables(struct smu_context * smu)365 int smu_v11_0_init_smc_tables(struct smu_context *smu)
366 {
367 struct smu_table_context *smu_table = &smu->smu_table;
368 struct smu_table *tables = smu_table->tables;
369 int ret = 0;
370
371 smu_table->driver_pptable =
372 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
373 if (!smu_table->driver_pptable) {
374 ret = -ENOMEM;
375 goto err0_out;
376 }
377
378 smu_table->max_sustainable_clocks =
379 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
380 if (!smu_table->max_sustainable_clocks) {
381 ret = -ENOMEM;
382 goto err1_out;
383 }
384
385 /* Arcturus does not support OVERDRIVE */
386 if (tables[SMU_TABLE_OVERDRIVE].size) {
387 smu_table->overdrive_table =
388 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
389 if (!smu_table->overdrive_table) {
390 ret = -ENOMEM;
391 goto err2_out;
392 }
393
394 smu_table->boot_overdrive_table =
395 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
396 if (!smu_table->boot_overdrive_table) {
397 ret = -ENOMEM;
398 goto err3_out;
399 }
400
401 smu_table->user_overdrive_table =
402 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
403 if (!smu_table->user_overdrive_table) {
404 ret = -ENOMEM;
405 goto err4_out;
406 }
407
408 }
409
410 return 0;
411
412 err4_out:
413 kfree(smu_table->boot_overdrive_table);
414 err3_out:
415 kfree(smu_table->overdrive_table);
416 err2_out:
417 kfree(smu_table->max_sustainable_clocks);
418 err1_out:
419 kfree(smu_table->driver_pptable);
420 err0_out:
421 return ret;
422 }
423
smu_v11_0_fini_smc_tables(struct smu_context * smu)424 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
425 {
426 struct smu_table_context *smu_table = &smu->smu_table;
427 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
428
429 kfree(smu_table->gpu_metrics_table);
430 kfree(smu_table->user_overdrive_table);
431 kfree(smu_table->boot_overdrive_table);
432 kfree(smu_table->overdrive_table);
433 kfree(smu_table->max_sustainable_clocks);
434 kfree(smu_table->driver_pptable);
435 kfree(smu_table->clocks_table);
436 smu_table->gpu_metrics_table = NULL;
437 smu_table->user_overdrive_table = NULL;
438 smu_table->boot_overdrive_table = NULL;
439 smu_table->overdrive_table = NULL;
440 smu_table->max_sustainable_clocks = NULL;
441 smu_table->driver_pptable = NULL;
442 smu_table->clocks_table = NULL;
443 kfree(smu_table->hardcode_pptable);
444 smu_table->hardcode_pptable = NULL;
445
446 kfree(smu_table->driver_smu_config_table);
447 kfree(smu_table->ecc_table);
448 kfree(smu_table->metrics_table);
449 kfree(smu_table->watermarks_table);
450 smu_table->driver_smu_config_table = NULL;
451 smu_table->ecc_table = NULL;
452 smu_table->metrics_table = NULL;
453 smu_table->watermarks_table = NULL;
454 smu_table->metrics_time = 0;
455
456 kfree(smu_dpm->dpm_context);
457 kfree(smu_dpm->golden_dpm_context);
458 kfree(smu_dpm->dpm_current_power_state);
459 kfree(smu_dpm->dpm_request_power_state);
460 smu_dpm->dpm_context = NULL;
461 smu_dpm->golden_dpm_context = NULL;
462 smu_dpm->dpm_context_size = 0;
463 smu_dpm->dpm_current_power_state = NULL;
464 smu_dpm->dpm_request_power_state = NULL;
465
466 return 0;
467 }
468
smu_v11_0_init_power(struct smu_context * smu)469 int smu_v11_0_init_power(struct smu_context *smu)
470 {
471 struct amdgpu_device *adev = smu->adev;
472 struct smu_power_context *smu_power = &smu->smu_power;
473 size_t size = amdgpu_ip_version(adev, MP1_HWIP, 0) ==
474 IP_VERSION(11, 5, 0) ?
475 sizeof(struct smu_11_5_power_context) :
476 sizeof(struct smu_11_0_power_context);
477
478 smu_power->power_context = kzalloc(size, GFP_KERNEL);
479 if (!smu_power->power_context)
480 return -ENOMEM;
481 smu_power->power_context_size = size;
482
483 return 0;
484 }
485
smu_v11_0_fini_power(struct smu_context * smu)486 int smu_v11_0_fini_power(struct smu_context *smu)
487 {
488 struct smu_power_context *smu_power = &smu->smu_power;
489
490 kfree(smu_power->power_context);
491 smu_power->power_context = NULL;
492 smu_power->power_context_size = 0;
493
494 return 0;
495 }
496
smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)497 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
498 uint8_t clk_id,
499 uint8_t syspll_id,
500 uint32_t *clk_freq)
501 {
502 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
503 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
504 int ret, index;
505
506 input.clk_id = clk_id;
507 input.syspll_id = syspll_id;
508 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
509 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
510 getsmuclockinfo);
511
512 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
513 (uint32_t *)&input, sizeof(input));
514 if (ret)
515 return -EINVAL;
516
517 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
518 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
519
520 return 0;
521 }
522
smu_v11_0_get_vbios_bootup_values(struct smu_context * smu)523 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
524 {
525 int ret, index;
526 uint16_t size;
527 uint8_t frev, crev;
528 struct atom_common_table_header *header;
529 struct atom_firmware_info_v3_3 *v_3_3;
530 struct atom_firmware_info_v3_1 *v_3_1;
531
532 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
533 firmwareinfo);
534
535 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
536 (uint8_t **)&header);
537 if (ret)
538 return ret;
539
540 if (header->format_revision != 3) {
541 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
542 return -EINVAL;
543 }
544
545 switch (header->content_revision) {
546 case 0:
547 case 1:
548 case 2:
549 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
550 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
551 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
552 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
553 smu->smu_table.boot_values.socclk = 0;
554 smu->smu_table.boot_values.dcefclk = 0;
555 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
556 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
557 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
558 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
559 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
560 smu->smu_table.boot_values.pp_table_id = 0;
561 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
562 break;
563 case 3:
564 case 4:
565 default:
566 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
567 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
568 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
569 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
570 smu->smu_table.boot_values.socclk = 0;
571 smu->smu_table.boot_values.dcefclk = 0;
572 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
573 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
574 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
575 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
576 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
577 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
578 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
579 }
580
581 smu->smu_table.boot_values.format_revision = header->format_revision;
582 smu->smu_table.boot_values.content_revision = header->content_revision;
583
584 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
585 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
586 (uint8_t)0,
587 &smu->smu_table.boot_values.socclk);
588
589 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
590 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
591 (uint8_t)0,
592 &smu->smu_table.boot_values.dcefclk);
593
594 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
595 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
596 (uint8_t)0,
597 &smu->smu_table.boot_values.eclk);
598
599 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
600 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
601 (uint8_t)0,
602 &smu->smu_table.boot_values.vclk);
603
604 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
605 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
606 (uint8_t)0,
607 &smu->smu_table.boot_values.dclk);
608
609 if ((smu->smu_table.boot_values.format_revision == 3) &&
610 (smu->smu_table.boot_values.content_revision >= 2))
611 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
612 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
613 (uint8_t)SMU11_SYSPLL1_2_ID,
614 &smu->smu_table.boot_values.fclk);
615
616 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
617 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
618 (uint8_t)SMU11_SYSPLL3_1_ID,
619 &smu->smu_table.boot_values.lclk);
620
621 return 0;
622 }
623
smu_v11_0_notify_memory_pool_location(struct smu_context * smu)624 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
625 {
626 struct smu_table_context *smu_table = &smu->smu_table;
627 struct smu_table *memory_pool = &smu_table->memory_pool;
628 int ret = 0;
629 uint64_t address;
630 uint32_t address_low, address_high;
631
632 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
633 return ret;
634
635 address = (uintptr_t)memory_pool->cpu_addr;
636 address_high = (uint32_t)upper_32_bits(address);
637 address_low = (uint32_t)lower_32_bits(address);
638
639 ret = smu_cmn_send_smc_msg_with_param(smu,
640 SMU_MSG_SetSystemVirtualDramAddrHigh,
641 address_high,
642 NULL);
643 if (ret)
644 return ret;
645 ret = smu_cmn_send_smc_msg_with_param(smu,
646 SMU_MSG_SetSystemVirtualDramAddrLow,
647 address_low,
648 NULL);
649 if (ret)
650 return ret;
651
652 address = memory_pool->mc_address;
653 address_high = (uint32_t)upper_32_bits(address);
654 address_low = (uint32_t)lower_32_bits(address);
655
656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
657 address_high, NULL);
658 if (ret)
659 return ret;
660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
661 address_low, NULL);
662 if (ret)
663 return ret;
664 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
665 (uint32_t)memory_pool->size, NULL);
666 if (ret)
667 return ret;
668
669 return ret;
670 }
671
smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)672 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
673 {
674 int ret;
675
676 ret = smu_cmn_send_smc_msg_with_param(smu,
677 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
678 if (ret)
679 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
680
681 return ret;
682 }
683
smu_v11_0_set_driver_table_location(struct smu_context * smu)684 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
685 {
686 struct smu_table *driver_table = &smu->smu_table.driver_table;
687 int ret = 0;
688
689 if (driver_table->mc_address) {
690 ret = smu_cmn_send_smc_msg_with_param(smu,
691 SMU_MSG_SetDriverDramAddrHigh,
692 upper_32_bits(driver_table->mc_address),
693 NULL);
694 if (!ret)
695 ret = smu_cmn_send_smc_msg_with_param(smu,
696 SMU_MSG_SetDriverDramAddrLow,
697 lower_32_bits(driver_table->mc_address),
698 NULL);
699 }
700
701 return ret;
702 }
703
smu_v11_0_set_tool_table_location(struct smu_context * smu)704 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
705 {
706 int ret = 0;
707 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
708
709 if (tool_table->mc_address) {
710 ret = smu_cmn_send_smc_msg_with_param(smu,
711 SMU_MSG_SetToolsDramAddrHigh,
712 upper_32_bits(tool_table->mc_address),
713 NULL);
714 if (!ret)
715 ret = smu_cmn_send_smc_msg_with_param(smu,
716 SMU_MSG_SetToolsDramAddrLow,
717 lower_32_bits(tool_table->mc_address),
718 NULL);
719 }
720
721 return ret;
722 }
723
smu_v11_0_init_display_count(struct smu_context * smu,uint32_t count)724 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
725 {
726 struct amdgpu_device *adev = smu->adev;
727
728 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
729 * display num currently
730 */
731 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) ||
732 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
733 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) ||
734 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
735 return 0;
736
737 return smu_cmn_send_smc_msg_with_param(smu,
738 SMU_MSG_NumOfDisplays,
739 count,
740 NULL);
741 }
742
743
smu_v11_0_set_allowed_mask(struct smu_context * smu)744 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
745 {
746 struct smu_feature *feature = &smu->smu_feature;
747 int ret = 0;
748 uint32_t feature_mask[2];
749
750 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
751 ret = -EINVAL;
752 goto failed;
753 }
754
755 bitmap_to_arr32(feature_mask, feature->allowed, 64);
756
757 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
758 feature_mask[1], NULL);
759 if (ret)
760 goto failed;
761
762 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
763 feature_mask[0], NULL);
764 if (ret)
765 goto failed;
766
767 failed:
768 return ret;
769 }
770
smu_v11_0_system_features_control(struct smu_context * smu,bool en)771 int smu_v11_0_system_features_control(struct smu_context *smu,
772 bool en)
773 {
774 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
775 SMU_MSG_DisableAllSmuFeatures), NULL);
776 }
777
smu_v11_0_notify_display_change(struct smu_context * smu)778 int smu_v11_0_notify_display_change(struct smu_context *smu)
779 {
780 int ret = 0;
781
782 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
783 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
784 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
785
786 return ret;
787 }
788
789 static int
smu_v11_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)790 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
791 enum smu_clk_type clock_select)
792 {
793 int ret = 0;
794 int clk_id;
795
796 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
797 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
798 return 0;
799
800 clk_id = smu_cmn_to_asic_specific_index(smu,
801 CMN2ASIC_MAPPING_CLK,
802 clock_select);
803 if (clk_id < 0)
804 return -EINVAL;
805
806 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
807 clk_id << 16, clock);
808 if (ret) {
809 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
810 return ret;
811 }
812
813 if (*clock != 0)
814 return 0;
815
816 /* if DC limit is zero, return AC limit */
817 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
818 clk_id << 16, clock);
819 if (ret) {
820 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
821 return ret;
822 }
823
824 return 0;
825 }
826
smu_v11_0_init_max_sustainable_clocks(struct smu_context * smu)827 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
828 {
829 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
830 smu->smu_table.max_sustainable_clocks;
831 int ret = 0;
832
833 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
834 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
835 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
836 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
837 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
838 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
839
840 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
841 ret = smu_v11_0_get_max_sustainable_clock(smu,
842 &(max_sustainable_clocks->uclock),
843 SMU_UCLK);
844 if (ret) {
845 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
846 __func__);
847 return ret;
848 }
849 }
850
851 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
852 ret = smu_v11_0_get_max_sustainable_clock(smu,
853 &(max_sustainable_clocks->soc_clock),
854 SMU_SOCCLK);
855 if (ret) {
856 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
857 __func__);
858 return ret;
859 }
860 }
861
862 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
863 ret = smu_v11_0_get_max_sustainable_clock(smu,
864 &(max_sustainable_clocks->dcef_clock),
865 SMU_DCEFCLK);
866 if (ret) {
867 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
868 __func__);
869 return ret;
870 }
871
872 ret = smu_v11_0_get_max_sustainable_clock(smu,
873 &(max_sustainable_clocks->display_clock),
874 SMU_DISPCLK);
875 if (ret) {
876 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
877 __func__);
878 return ret;
879 }
880 ret = smu_v11_0_get_max_sustainable_clock(smu,
881 &(max_sustainable_clocks->phy_clock),
882 SMU_PHYCLK);
883 if (ret) {
884 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
885 __func__);
886 return ret;
887 }
888 ret = smu_v11_0_get_max_sustainable_clock(smu,
889 &(max_sustainable_clocks->pixel_clock),
890 SMU_PIXCLK);
891 if (ret) {
892 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
893 __func__);
894 return ret;
895 }
896 }
897
898 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
899 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
900
901 return 0;
902 }
903
smu_v11_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)904 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
905 uint32_t *power_limit)
906 {
907 int power_src;
908 int ret = 0;
909
910 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
911 return -EINVAL;
912
913 power_src = smu_cmn_to_asic_specific_index(smu,
914 CMN2ASIC_MAPPING_PWR,
915 smu->adev->pm.ac_power ?
916 SMU_POWER_SOURCE_AC :
917 SMU_POWER_SOURCE_DC);
918 if (power_src < 0)
919 return -EINVAL;
920
921 /*
922 * BIT 24-31: ControllerId (only PPT0 is supported for now)
923 * BIT 16-23: PowerSource
924 */
925 ret = smu_cmn_send_smc_msg_with_param(smu,
926 SMU_MSG_GetPptLimit,
927 (0 << 24) | (power_src << 16),
928 power_limit);
929 if (ret)
930 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
931
932 return ret;
933 }
934
smu_v11_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)935 int smu_v11_0_set_power_limit(struct smu_context *smu,
936 enum smu_ppt_limit_type limit_type,
937 uint32_t limit)
938 {
939 int power_src;
940 int ret = 0;
941 uint32_t limit_param;
942
943 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
944 return -EINVAL;
945
946 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
947 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
948 return -EOPNOTSUPP;
949 }
950
951 power_src = smu_cmn_to_asic_specific_index(smu,
952 CMN2ASIC_MAPPING_PWR,
953 smu->adev->pm.ac_power ?
954 SMU_POWER_SOURCE_AC :
955 SMU_POWER_SOURCE_DC);
956 if (power_src < 0)
957 return -EINVAL;
958
959 /*
960 * BIT 24-31: ControllerId (only PPT0 is supported for now)
961 * BIT 16-23: PowerSource
962 * BIT 0-15: PowerLimit
963 */
964 limit_param = (limit & 0xFFFF);
965 limit_param |= 0 << 24;
966 limit_param |= (power_src) << 16;
967 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
968 if (ret) {
969 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
970 return ret;
971 }
972
973 smu->current_power_limit = limit;
974
975 return 0;
976 }
977
smu_v11_0_ack_ac_dc_interrupt(struct smu_context * smu)978 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
979 {
980 return smu_cmn_send_smc_msg(smu,
981 SMU_MSG_ReenableAcDcInterrupt,
982 NULL);
983 }
984
smu_v11_0_process_pending_interrupt(struct smu_context * smu)985 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
986 {
987 int ret = 0;
988
989 if (smu->dc_controlled_by_gpio &&
990 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
991 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
992
993 return ret;
994 }
995
smu_v11_0_interrupt_work(struct smu_context * smu)996 void smu_v11_0_interrupt_work(struct smu_context *smu)
997 {
998 if (smu_v11_0_ack_ac_dc_interrupt(smu))
999 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1000 }
1001
smu_v11_0_enable_thermal_alert(struct smu_context * smu)1002 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1003 {
1004 int ret = 0;
1005
1006 if (smu->smu_table.thermal_controller_type) {
1007 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1008 if (ret)
1009 return ret;
1010 }
1011
1012 /*
1013 * After init there might have been missed interrupts triggered
1014 * before driver registers for interrupt (Ex. AC/DC).
1015 */
1016 return smu_v11_0_process_pending_interrupt(smu);
1017 }
1018
smu_v11_0_disable_thermal_alert(struct smu_context * smu)1019 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1020 {
1021 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1022 }
1023
convert_to_vddc(uint8_t vid)1024 static uint16_t convert_to_vddc(uint8_t vid)
1025 {
1026 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1027 }
1028
smu_v11_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1029 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1030 {
1031 struct amdgpu_device *adev = smu->adev;
1032 uint32_t vdd = 0, val_vid = 0;
1033
1034 if (!value)
1035 return -EINVAL;
1036 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1037 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1038 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1039
1040 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1041
1042 *value = vdd;
1043
1044 return 0;
1045
1046 }
1047
1048 int
smu_v11_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1049 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1050 struct pp_display_clock_request
1051 *clock_req)
1052 {
1053 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1054 int ret = 0;
1055 enum smu_clk_type clk_select = 0;
1056 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1057
1058 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1059 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1060 switch (clk_type) {
1061 case amd_pp_dcef_clock:
1062 clk_select = SMU_DCEFCLK;
1063 break;
1064 case amd_pp_disp_clock:
1065 clk_select = SMU_DISPCLK;
1066 break;
1067 case amd_pp_pixel_clock:
1068 clk_select = SMU_PIXCLK;
1069 break;
1070 case amd_pp_phy_clock:
1071 clk_select = SMU_PHYCLK;
1072 break;
1073 case amd_pp_mem_clock:
1074 clk_select = SMU_UCLK;
1075 break;
1076 default:
1077 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1078 ret = -EINVAL;
1079 break;
1080 }
1081
1082 if (ret)
1083 goto failed;
1084
1085 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1086 return 0;
1087
1088 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1089
1090 if(clk_select == SMU_UCLK)
1091 smu->hard_min_uclk_req_from_dal = clk_freq;
1092 }
1093
1094 failed:
1095 return ret;
1096 }
1097
smu_v11_0_gfx_off_control(struct smu_context * smu,bool enable)1098 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1099 {
1100 int ret = 0;
1101 struct amdgpu_device *adev = smu->adev;
1102
1103 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1104 case IP_VERSION(11, 0, 0):
1105 case IP_VERSION(11, 0, 5):
1106 case IP_VERSION(11, 0, 9):
1107 case IP_VERSION(11, 0, 7):
1108 case IP_VERSION(11, 0, 11):
1109 case IP_VERSION(11, 0, 12):
1110 case IP_VERSION(11, 0, 13):
1111 case IP_VERSION(11, 5, 0):
1112 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1113 return 0;
1114 if (enable)
1115 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1116 else
1117 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1118 break;
1119 default:
1120 break;
1121 }
1122
1123 return ret;
1124 }
1125
1126 uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context * smu)1127 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1128 {
1129 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1130 return AMD_FAN_CTRL_AUTO;
1131 else
1132 return smu->user_dpm_profile.fan_mode;
1133 }
1134
1135 static int
smu_v11_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1136 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1137 {
1138 int ret = 0;
1139
1140 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1141 return 0;
1142
1143 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1144 if (ret)
1145 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1146 __func__, (auto_fan_control ? "Start" : "Stop"));
1147
1148 return ret;
1149 }
1150
1151 static int
smu_v11_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1152 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1153 {
1154 struct amdgpu_device *adev = smu->adev;
1155
1156 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1157 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1158 CG_FDO_CTRL2, TMIN, 0));
1159 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1160 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1161 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1162
1163 return 0;
1164 }
1165
1166 int
smu_v11_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1167 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1168 {
1169 struct amdgpu_device *adev = smu->adev;
1170 uint32_t duty100, duty;
1171 uint64_t tmp64;
1172
1173 speed = min_t(uint32_t, speed, 255);
1174
1175 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1176 CG_FDO_CTRL1, FMAX_DUTY100);
1177 if (!duty100)
1178 return -EINVAL;
1179
1180 tmp64 = (uint64_t)speed * duty100;
1181 do_div(tmp64, 255);
1182 duty = (uint32_t)tmp64;
1183
1184 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1185 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1186 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1187
1188 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1189 }
1190
smu_v11_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1191 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1192 uint32_t speed)
1193 {
1194 struct amdgpu_device *adev = smu->adev;
1195 /*
1196 * crystal_clock_freq used for fan speed rpm calculation is
1197 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1198 */
1199 uint32_t crystal_clock_freq = 2500;
1200 uint32_t tach_period;
1201
1202 if (speed == 0)
1203 return -EINVAL;
1204 /*
1205 * To prevent from possible overheat, some ASICs may have requirement
1206 * for minimum fan speed:
1207 * - For some NV10 SKU, the fan speed cannot be set lower than
1208 * 700 RPM.
1209 * - For some Sienna Cichlid SKU, the fan speed cannot be set
1210 * lower than 500 RPM.
1211 */
1212 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1213 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1214 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1215 CG_TACH_CTRL, TARGET_PERIOD,
1216 tach_period));
1217
1218 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1219 }
1220
smu_v11_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1221 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1222 uint32_t *speed)
1223 {
1224 struct amdgpu_device *adev = smu->adev;
1225 uint32_t duty100, duty;
1226 uint64_t tmp64;
1227
1228 /*
1229 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1230 * detected via register retrieving. To workaround this, we will
1231 * report the fan speed as 0 PWM if user just requested such.
1232 */
1233 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1234 && !smu->user_dpm_profile.fan_speed_pwm) {
1235 *speed = 0;
1236 return 0;
1237 }
1238
1239 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1240 CG_FDO_CTRL1, FMAX_DUTY100);
1241 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1242 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1243 if (!duty100)
1244 return -EINVAL;
1245
1246 tmp64 = (uint64_t)duty * 255;
1247 do_div(tmp64, duty100);
1248 *speed = min_t(uint32_t, tmp64, 255);
1249
1250 return 0;
1251 }
1252
smu_v11_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1253 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1254 uint32_t *speed)
1255 {
1256 struct amdgpu_device *adev = smu->adev;
1257 uint32_t crystal_clock_freq = 2500;
1258 uint32_t tach_status;
1259 uint64_t tmp64;
1260
1261 /*
1262 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1263 * detected via register retrieving. To workaround this, we will
1264 * report the fan speed as 0 RPM if user just requested such.
1265 */
1266 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1267 && !smu->user_dpm_profile.fan_speed_rpm) {
1268 *speed = 0;
1269 return 0;
1270 }
1271
1272 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1273
1274 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
1275 if (tach_status) {
1276 do_div(tmp64, tach_status);
1277 *speed = (uint32_t)tmp64;
1278 } else {
1279 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
1280 *speed = 0;
1281 }
1282
1283 return 0;
1284 }
1285
1286 int
smu_v11_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1287 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1288 uint32_t mode)
1289 {
1290 int ret = 0;
1291
1292 switch (mode) {
1293 case AMD_FAN_CTRL_NONE:
1294 ret = smu_v11_0_auto_fan_control(smu, 0);
1295 if (!ret)
1296 ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1297 break;
1298 case AMD_FAN_CTRL_MANUAL:
1299 ret = smu_v11_0_auto_fan_control(smu, 0);
1300 break;
1301 case AMD_FAN_CTRL_AUTO:
1302 ret = smu_v11_0_auto_fan_control(smu, 1);
1303 break;
1304 default:
1305 break;
1306 }
1307
1308 if (ret) {
1309 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1310 return -EINVAL;
1311 }
1312
1313 return ret;
1314 }
1315
smu_v11_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1316 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1317 uint32_t pstate)
1318 {
1319 return smu_cmn_send_smc_msg_with_param(smu,
1320 SMU_MSG_SetXgmiMode,
1321 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1322 NULL);
1323 }
1324
smu_v11_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1325 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1326 struct amdgpu_irq_src *source,
1327 unsigned tyep,
1328 enum amdgpu_interrupt_state state)
1329 {
1330 struct smu_context *smu = adev->powerplay.pp_handle;
1331 uint32_t low, high;
1332 uint32_t val = 0;
1333
1334 switch (state) {
1335 case AMDGPU_IRQ_STATE_DISABLE:
1336 /* For THM irqs */
1337 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1338 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1339 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1340 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1341
1342 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1343
1344 /* For MP1 SW irqs */
1345 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1346 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1347 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1348
1349 break;
1350 case AMDGPU_IRQ_STATE_ENABLE:
1351 /* For THM irqs */
1352 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1353 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1354 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1355 smu->thermal_range.software_shutdown_temp);
1356
1357 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1358 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1359 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1360 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1361 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1362 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1363 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1364 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1365 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1366
1367 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1368 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1369 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1370 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1371
1372 /* For MP1 SW irqs */
1373 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1374 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1375 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1376 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1377
1378 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1379 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1380 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1381
1382 break;
1383 default:
1384 break;
1385 }
1386
1387 return 0;
1388 }
1389
1390 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1391 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1392
1393 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1394
smu_v11_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1395 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1396 struct amdgpu_irq_src *source,
1397 struct amdgpu_iv_entry *entry)
1398 {
1399 struct smu_context *smu = adev->powerplay.pp_handle;
1400 uint32_t client_id = entry->client_id;
1401 uint32_t src_id = entry->src_id;
1402 /*
1403 * ctxid is used to distinguish different
1404 * events for SMCToHost interrupt.
1405 */
1406 uint32_t ctxid = entry->src_data[0];
1407 uint32_t data;
1408
1409 if (client_id == SOC15_IH_CLIENTID_THM) {
1410 switch (src_id) {
1411 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1412 schedule_delayed_work(&smu->swctf_delayed_work,
1413 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1414 break;
1415 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1416 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1417 break;
1418 default:
1419 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1420 src_id);
1421 break;
1422 }
1423 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1424 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1425 /*
1426 * HW CTF just occurred. Shutdown to prevent further damage.
1427 */
1428 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1429 orderly_poweroff(true);
1430 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1431 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1432 /* ACK SMUToHost interrupt */
1433 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1434 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1435 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1436
1437 switch (ctxid) {
1438 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1439 dev_dbg(adev->dev, "Switched to AC mode!\n");
1440 schedule_work(&smu->interrupt_work);
1441 adev->pm.ac_power = true;
1442 break;
1443 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1444 dev_dbg(adev->dev, "Switched to DC mode!\n");
1445 schedule_work(&smu->interrupt_work);
1446 adev->pm.ac_power = false;
1447 break;
1448 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1449 /*
1450 * Increment the throttle interrupt counter
1451 */
1452 atomic64_inc(&smu->throttle_int_counter);
1453
1454 if (!atomic_read(&adev->throttling_logging_enabled))
1455 return 0;
1456
1457 if (__ratelimit(&adev->throttling_logging_rs))
1458 schedule_work(&smu->throttling_logging_work);
1459
1460 break;
1461 default:
1462 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1463 ctxid, client_id);
1464 break;
1465 }
1466 }
1467 }
1468
1469 return 0;
1470 }
1471
1472 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1473 {
1474 .set = smu_v11_0_set_irq_state,
1475 .process = smu_v11_0_irq_process,
1476 };
1477
smu_v11_0_register_irq_handler(struct smu_context * smu)1478 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1479 {
1480 struct amdgpu_device *adev = smu->adev;
1481 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1482 int ret = 0;
1483
1484 irq_src->num_types = 1;
1485 irq_src->funcs = &smu_v11_0_irq_funcs;
1486
1487 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1488 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1489 irq_src);
1490 if (ret)
1491 return ret;
1492
1493 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1494 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1495 irq_src);
1496 if (ret)
1497 return ret;
1498
1499 /* Register CTF(GPIO_19) interrupt */
1500 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1501 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1502 irq_src);
1503 if (ret)
1504 return ret;
1505
1506 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1507 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1508 irq_src);
1509 if (ret)
1510 return ret;
1511
1512 return ret;
1513 }
1514
smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1515 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1516 struct pp_smu_nv_clock_table *max_clocks)
1517 {
1518 struct smu_table_context *table_context = &smu->smu_table;
1519 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1520
1521 if (!max_clocks || !table_context->max_sustainable_clocks)
1522 return -EINVAL;
1523
1524 sustainable_clocks = table_context->max_sustainable_clocks;
1525
1526 max_clocks->dcfClockInKhz =
1527 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1528 max_clocks->displayClockInKhz =
1529 (unsigned int) sustainable_clocks->display_clock * 1000;
1530 max_clocks->phyClockInKhz =
1531 (unsigned int) sustainable_clocks->phy_clock * 1000;
1532 max_clocks->pixelClockInKhz =
1533 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1534 max_clocks->uClockInKhz =
1535 (unsigned int) sustainable_clocks->uclock * 1000;
1536 max_clocks->socClockInKhz =
1537 (unsigned int) sustainable_clocks->soc_clock * 1000;
1538 max_clocks->dscClockInKhz = 0;
1539 max_clocks->dppClockInKhz = 0;
1540 max_clocks->fabricClockInKhz = 0;
1541
1542 return 0;
1543 }
1544
smu_v11_0_set_azalia_d3_pme(struct smu_context * smu)1545 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1546 {
1547 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1548 }
1549
smu_v11_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1550 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1551 enum smu_baco_seq baco_seq)
1552 {
1553 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1554 }
1555
smu_v11_0_get_bamaco_support(struct smu_context * smu)1556 int smu_v11_0_get_bamaco_support(struct smu_context *smu)
1557 {
1558 struct smu_baco_context *smu_baco = &smu->smu_baco;
1559 int bamaco_support = 0;
1560
1561 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1562 return 0;
1563
1564 if (smu_baco->maco_support)
1565 bamaco_support |= MACO_SUPPORT;
1566
1567 /* return true if ASIC is in BACO state already */
1568 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1569 return bamaco_support |= BACO_SUPPORT;
1570
1571 /* Arcturus does not support this bit mask */
1572 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1573 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1574 return 0;
1575
1576 return (bamaco_support |= BACO_SUPPORT);
1577 }
1578
smu_v11_0_baco_get_state(struct smu_context * smu)1579 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1580 {
1581 struct smu_baco_context *smu_baco = &smu->smu_baco;
1582
1583 return smu_baco->state;
1584 }
1585
1586 #define D3HOT_BACO_SEQUENCE 0
1587 #define D3HOT_BAMACO_SEQUENCE 2
1588
smu_v11_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1589 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1590 {
1591 struct smu_baco_context *smu_baco = &smu->smu_baco;
1592 struct amdgpu_device *adev = smu->adev;
1593 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1594 uint32_t data;
1595 int ret = 0;
1596
1597 if (smu_v11_0_baco_get_state(smu) == state)
1598 return 0;
1599
1600 if (state == SMU_BACO_STATE_ENTER) {
1601 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1602 case IP_VERSION(11, 0, 7):
1603 case IP_VERSION(11, 0, 11):
1604 case IP_VERSION(11, 0, 12):
1605 case IP_VERSION(11, 0, 13):
1606 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
1607 ret = smu_cmn_send_smc_msg_with_param(smu,
1608 SMU_MSG_EnterBaco,
1609 D3HOT_BAMACO_SEQUENCE,
1610 NULL);
1611 else
1612 ret = smu_cmn_send_smc_msg_with_param(smu,
1613 SMU_MSG_EnterBaco,
1614 D3HOT_BACO_SEQUENCE,
1615 NULL);
1616 break;
1617 default:
1618 if (!ras || !adev->ras_enabled ||
1619 adev->gmc.xgmi.pending_reset) {
1620 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1621 IP_VERSION(11, 0, 2)) {
1622 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1623 data |= 0x80000000;
1624 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1625 } else {
1626 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1627 data |= 0x80000000;
1628 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1629 }
1630
1631 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1632 } else {
1633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1634 }
1635 break;
1636 }
1637
1638 } else {
1639 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1640 if (ret)
1641 return ret;
1642
1643 /* clear vbios scratch 6 and 7 for coming asic reinit */
1644 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1645 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1646 }
1647
1648 if (!ret)
1649 smu_baco->state = state;
1650
1651 return ret;
1652 }
1653
smu_v11_0_baco_enter(struct smu_context * smu)1654 int smu_v11_0_baco_enter(struct smu_context *smu)
1655 {
1656 int ret = 0;
1657
1658 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1659 if (ret)
1660 return ret;
1661
1662 msleep(10);
1663
1664 return ret;
1665 }
1666
smu_v11_0_baco_exit(struct smu_context * smu)1667 int smu_v11_0_baco_exit(struct smu_context *smu)
1668 {
1669 int ret;
1670
1671 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1672 if (!ret) {
1673 /*
1674 * Poll BACO exit status to ensure FW has completed
1675 * BACO exit process to avoid timing issues.
1676 */
1677 smu_v11_0_poll_baco_exit(smu);
1678 }
1679
1680 return ret;
1681 }
1682
smu_v11_0_mode1_reset(struct smu_context * smu)1683 int smu_v11_0_mode1_reset(struct smu_context *smu)
1684 {
1685 int ret = 0;
1686
1687 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1688 if (!ret)
1689 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1690
1691 return ret;
1692 }
1693
smu_v11_0_handle_passthrough_sbr(struct smu_context * smu,bool enable)1694 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1695 {
1696 int ret = 0;
1697
1698 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1699
1700 return ret;
1701 }
1702
1703
smu_v11_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1704 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1705 uint32_t *min, uint32_t *max)
1706 {
1707 int ret = 0, clk_id = 0;
1708 uint32_t param = 0;
1709 uint32_t clock_limit;
1710
1711 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1712 switch (clk_type) {
1713 case SMU_MCLK:
1714 case SMU_UCLK:
1715 clock_limit = smu->smu_table.boot_values.uclk;
1716 break;
1717 case SMU_GFXCLK:
1718 case SMU_SCLK:
1719 clock_limit = smu->smu_table.boot_values.gfxclk;
1720 break;
1721 case SMU_SOCCLK:
1722 clock_limit = smu->smu_table.boot_values.socclk;
1723 break;
1724 default:
1725 clock_limit = 0;
1726 break;
1727 }
1728
1729 /* clock in Mhz unit */
1730 if (min)
1731 *min = clock_limit / 100;
1732 if (max)
1733 *max = clock_limit / 100;
1734
1735 return 0;
1736 }
1737
1738 clk_id = smu_cmn_to_asic_specific_index(smu,
1739 CMN2ASIC_MAPPING_CLK,
1740 clk_type);
1741 if (clk_id < 0) {
1742 ret = -EINVAL;
1743 goto failed;
1744 }
1745 param = (clk_id & 0xffff) << 16;
1746
1747 if (max) {
1748 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1749 if (ret)
1750 goto failed;
1751 }
1752
1753 if (min) {
1754 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1755 if (ret)
1756 goto failed;
1757 }
1758
1759 failed:
1760 return ret;
1761 }
1762
smu_v11_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1763 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1764 enum smu_clk_type clk_type,
1765 uint32_t min,
1766 uint32_t max)
1767 {
1768 int ret = 0, clk_id = 0;
1769 uint32_t param;
1770
1771 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1772 return 0;
1773
1774 clk_id = smu_cmn_to_asic_specific_index(smu,
1775 CMN2ASIC_MAPPING_CLK,
1776 clk_type);
1777 if (clk_id < 0)
1778 return clk_id;
1779
1780 if (max > 0) {
1781 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1782 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1783 param, NULL);
1784 if (ret)
1785 goto out;
1786 }
1787
1788 if (min > 0) {
1789 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1791 param, NULL);
1792 if (ret)
1793 goto out;
1794 }
1795
1796 out:
1797 return ret;
1798 }
1799
smu_v11_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1800 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1801 enum smu_clk_type clk_type,
1802 uint32_t min,
1803 uint32_t max)
1804 {
1805 int ret = 0, clk_id = 0;
1806 uint32_t param;
1807
1808 if (min <= 0 && max <= 0)
1809 return -EINVAL;
1810
1811 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1812 return 0;
1813
1814 clk_id = smu_cmn_to_asic_specific_index(smu,
1815 CMN2ASIC_MAPPING_CLK,
1816 clk_type);
1817 if (clk_id < 0)
1818 return clk_id;
1819
1820 if (max > 0) {
1821 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1822 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1823 param, NULL);
1824 if (ret)
1825 return ret;
1826 }
1827
1828 if (min > 0) {
1829 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1830 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1831 param, NULL);
1832 if (ret)
1833 return ret;
1834 }
1835
1836 return ret;
1837 }
1838
smu_v11_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1839 int smu_v11_0_set_performance_level(struct smu_context *smu,
1840 enum amd_dpm_forced_level level)
1841 {
1842 struct smu_11_0_dpm_context *dpm_context =
1843 smu->smu_dpm.dpm_context;
1844 struct smu_11_0_dpm_table *gfx_table =
1845 &dpm_context->dpm_tables.gfx_table;
1846 struct smu_11_0_dpm_table *mem_table =
1847 &dpm_context->dpm_tables.uclk_table;
1848 struct smu_11_0_dpm_table *soc_table =
1849 &dpm_context->dpm_tables.soc_table;
1850 struct smu_umd_pstate_table *pstate_table =
1851 &smu->pstate_table;
1852 struct amdgpu_device *adev = smu->adev;
1853 uint32_t sclk_min = 0, sclk_max = 0;
1854 uint32_t mclk_min = 0, mclk_max = 0;
1855 uint32_t socclk_min = 0, socclk_max = 0;
1856 int ret = 0;
1857
1858 switch (level) {
1859 case AMD_DPM_FORCED_LEVEL_HIGH:
1860 sclk_min = sclk_max = gfx_table->max;
1861 mclk_min = mclk_max = mem_table->max;
1862 socclk_min = socclk_max = soc_table->max;
1863 break;
1864 case AMD_DPM_FORCED_LEVEL_LOW:
1865 sclk_min = sclk_max = gfx_table->min;
1866 mclk_min = mclk_max = mem_table->min;
1867 socclk_min = socclk_max = soc_table->min;
1868 break;
1869 case AMD_DPM_FORCED_LEVEL_AUTO:
1870 sclk_min = gfx_table->min;
1871 sclk_max = gfx_table->max;
1872 mclk_min = mem_table->min;
1873 mclk_max = mem_table->max;
1874 socclk_min = soc_table->min;
1875 socclk_max = soc_table->max;
1876 break;
1877 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1878 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1879 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1880 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1881 break;
1882 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1883 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1884 break;
1885 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1886 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1887 break;
1888 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1889 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1890 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1891 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1892 break;
1893 case AMD_DPM_FORCED_LEVEL_MANUAL:
1894 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1895 return 0;
1896 default:
1897 dev_err(adev->dev, "Invalid performance level %d\n", level);
1898 return -EINVAL;
1899 }
1900
1901 /*
1902 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1903 * on Arcturus.
1904 */
1905 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1906 mclk_min = mclk_max = 0;
1907 socclk_min = socclk_max = 0;
1908 }
1909
1910 if (sclk_min && sclk_max) {
1911 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1912 SMU_GFXCLK,
1913 sclk_min,
1914 sclk_max);
1915 if (ret)
1916 return ret;
1917 }
1918
1919 if (mclk_min && mclk_max) {
1920 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1921 SMU_MCLK,
1922 mclk_min,
1923 mclk_max);
1924 if (ret)
1925 return ret;
1926 }
1927
1928 if (socclk_min && socclk_max) {
1929 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1930 SMU_SOCCLK,
1931 socclk_min,
1932 socclk_max);
1933 if (ret)
1934 return ret;
1935 }
1936
1937 return ret;
1938 }
1939
smu_v11_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1940 int smu_v11_0_set_power_source(struct smu_context *smu,
1941 enum smu_power_src_type power_src)
1942 {
1943 int pwr_source;
1944
1945 pwr_source = smu_cmn_to_asic_specific_index(smu,
1946 CMN2ASIC_MAPPING_PWR,
1947 (uint32_t)power_src);
1948 if (pwr_source < 0)
1949 return -EINVAL;
1950
1951 return smu_cmn_send_smc_msg_with_param(smu,
1952 SMU_MSG_NotifyPowerSource,
1953 pwr_source,
1954 NULL);
1955 }
1956
smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1957 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1958 enum smu_clk_type clk_type,
1959 uint16_t level,
1960 uint32_t *value)
1961 {
1962 int ret = 0, clk_id = 0;
1963 uint32_t param;
1964
1965 if (!value)
1966 return -EINVAL;
1967
1968 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1969 return 0;
1970
1971 clk_id = smu_cmn_to_asic_specific_index(smu,
1972 CMN2ASIC_MAPPING_CLK,
1973 clk_type);
1974 if (clk_id < 0)
1975 return clk_id;
1976
1977 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1978
1979 ret = smu_cmn_send_smc_msg_with_param(smu,
1980 SMU_MSG_GetDpmFreqByIndex,
1981 param,
1982 value);
1983 if (ret)
1984 return ret;
1985
1986 /*
1987 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1988 * now, we un-support it
1989 */
1990 *value = *value & 0x7fffffff;
1991
1992 return ret;
1993 }
1994
smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1995 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1996 enum smu_clk_type clk_type,
1997 uint32_t *value)
1998 {
1999 return smu_v11_0_get_dpm_freq_by_index(smu,
2000 clk_type,
2001 0xff,
2002 value);
2003 }
2004
smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_11_0_dpm_table * single_dpm_table)2005 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2006 enum smu_clk_type clk_type,
2007 struct smu_11_0_dpm_table *single_dpm_table)
2008 {
2009 int ret = 0;
2010 uint32_t clk;
2011 int i;
2012
2013 ret = smu_v11_0_get_dpm_level_count(smu,
2014 clk_type,
2015 &single_dpm_table->count);
2016 if (ret) {
2017 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2018 return ret;
2019 }
2020
2021 for (i = 0; i < single_dpm_table->count; i++) {
2022 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2023 clk_type,
2024 i,
2025 &clk);
2026 if (ret) {
2027 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2028 return ret;
2029 }
2030
2031 single_dpm_table->dpm_levels[i].value = clk;
2032 single_dpm_table->dpm_levels[i].enabled = true;
2033
2034 if (i == 0)
2035 single_dpm_table->min = clk;
2036 else if (i == single_dpm_table->count - 1)
2037 single_dpm_table->max = clk;
2038 }
2039
2040 return 0;
2041 }
2042
smu_v11_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)2043 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
2044 enum smu_clk_type clk_type,
2045 uint32_t *min_value,
2046 uint32_t *max_value)
2047 {
2048 uint32_t level_count = 0;
2049 int ret = 0;
2050
2051 if (!min_value && !max_value)
2052 return -EINVAL;
2053
2054 if (min_value) {
2055 /* by default, level 0 clock value as min value */
2056 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2057 clk_type,
2058 0,
2059 min_value);
2060 if (ret)
2061 return ret;
2062 }
2063
2064 if (max_value) {
2065 ret = smu_v11_0_get_dpm_level_count(smu,
2066 clk_type,
2067 &level_count);
2068 if (ret)
2069 return ret;
2070
2071 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2072 clk_type,
2073 level_count - 1,
2074 max_value);
2075 if (ret)
2076 return ret;
2077 }
2078
2079 return ret;
2080 }
2081
smu_v11_0_get_current_pcie_link_width_level(struct smu_context * smu)2082 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2083 {
2084 struct amdgpu_device *adev = smu->adev;
2085
2086 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2087 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2088 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2089 }
2090
smu_v11_0_get_current_pcie_link_width(struct smu_context * smu)2091 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2092 {
2093 uint32_t width_level;
2094
2095 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2096 if (width_level > LINK_WIDTH_MAX)
2097 width_level = 0;
2098
2099 return link_width[width_level];
2100 }
2101
smu_v11_0_get_current_pcie_link_speed_level(struct smu_context * smu)2102 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2103 {
2104 struct amdgpu_device *adev = smu->adev;
2105
2106 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2107 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2108 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2109 }
2110
smu_v11_0_get_current_pcie_link_speed(struct smu_context * smu)2111 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2112 {
2113 uint32_t speed_level;
2114
2115 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2116 if (speed_level > LINK_SPEED_MAX)
2117 speed_level = 0;
2118
2119 return link_speed[speed_level];
2120 }
2121
smu_v11_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2122 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2123 bool enablement)
2124 {
2125 int ret = 0;
2126
2127 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2128 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2129
2130 return ret;
2131 }
2132
smu_v11_0_deep_sleep_control(struct smu_context * smu,bool enablement)2133 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2134 bool enablement)
2135 {
2136 struct amdgpu_device *adev = smu->adev;
2137 int ret = 0;
2138
2139 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2140 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2141 if (ret) {
2142 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2143 return ret;
2144 }
2145 }
2146
2147 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2148 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2149 if (ret) {
2150 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2151 return ret;
2152 }
2153 }
2154
2155 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2156 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2157 if (ret) {
2158 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2159 return ret;
2160 }
2161 }
2162
2163 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2164 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2165 if (ret) {
2166 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2167 return ret;
2168 }
2169 }
2170
2171 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2172 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2173 if (ret) {
2174 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2175 return ret;
2176 }
2177 }
2178
2179 return ret;
2180 }
2181
smu_v11_0_restore_user_od_settings(struct smu_context * smu)2182 int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2183 {
2184 struct smu_table_context *table_context = &smu->smu_table;
2185 void *user_od_table = table_context->user_overdrive_table;
2186 int ret = 0;
2187
2188 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2189 if (ret)
2190 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2191
2192 return ret;
2193 }
2194
smu_v11_0_set_smu_mailbox_registers(struct smu_context * smu)2195 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
2196 {
2197 struct amdgpu_device *adev = smu->adev;
2198
2199 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2200 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2201 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2202 }
2203