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Searched refs:GCC_VIDEO_AXI0_CLK_ARES (Results 1 – 16 of 16) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,sar2130p-gcc.h166 #define GCC_VIDEO_AXI0_CLK_ARES 29 macro
H A Dqcom,sm8550-gcc.h217 #define GCC_VIDEO_AXI0_CLK_ARES 33 macro
H A Dqcom,gcc-sm8450.h236 #define GCC_VIDEO_AXI0_CLK_ARES 34 macro
H A Dqcom,qcs8300-gcc.h231 #define GCC_VIDEO_AXI0_CLK_ARES 27 macro
H A Dqcom,sm8650-gcc.h240 #define GCC_VIDEO_AXI0_CLK_ARES 33 macro
H A Dqcom,gcc-sm8350.h249 #define GCC_VIDEO_AXI0_CLK_ARES 35 macro
H A Dqcom,gcc-sm8250.h255 #define GCC_VIDEO_AXI0_CLK_ARES 43 macro
H A Dqcom,sa8775p-gcc.h306 #define GCC_VIDEO_AXI0_CLK_ARES 44 macro
H A Dqcom,gcc-sc8280xp.h479 #define GCC_VIDEO_AXI0_CLK_ARES 77 macro
/linux/drivers/clk/qcom/
H A Dgcc-sar2130p.c2259 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
H A Dgcc-sm8250.c3579 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 },
H A Dgcc-sm8450.c3350 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
H A Dgcc-qcs8300.c3541 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
H A Dgcc-sm8350.c3746 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
H A Dgcc-sa8775p.c4598 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
H A Dgcc-sc8280xp.c7451 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },