1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,eliza-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_PCIE_0_PIPE_CLK, 30 DT_PCIE_1_PIPE_CLK, 31 DT_UFS_PHY_RX_SYMBOL_0_CLK, 32 DT_UFS_PHY_RX_SYMBOL_1_CLK, 33 DT_UFS_PHY_TX_SYMBOL_0_CLK, 34 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_GCC_GPLL0_OUT_EVEN, 40 P_GCC_GPLL0_OUT_MAIN, 41 P_GCC_GPLL4_OUT_MAIN, 42 P_GCC_GPLL7_OUT_MAIN, 43 P_GCC_GPLL8_OUT_MAIN, 44 P_GCC_GPLL9_OUT_MAIN, 45 P_PCIE_0_PIPE_CLK, 46 P_PCIE_1_PIPE_CLK, 47 P_SLEEP_CLK, 48 P_UFS_PHY_RX_SYMBOL_0_CLK, 49 P_UFS_PHY_RX_SYMBOL_1_CLK, 50 P_UFS_PHY_TX_SYMBOL_0_CLK, 51 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 52 }; 53 54 static struct clk_alpha_pll gcc_gpll0 = { 55 .offset = 0x0, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 57 .clkr = { 58 .enable_reg = 0x52020, 59 .enable_mask = BIT(0), 60 .hw.init = &(const struct clk_init_data) { 61 .name = "gcc_gpll0", 62 .parent_data = &(const struct clk_parent_data) { 63 .index = DT_BI_TCXO, 64 }, 65 .num_parents = 1, 66 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 67 }, 68 }, 69 }; 70 71 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 72 { 0x1, 2 }, 73 { } 74 }; 75 76 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 77 .offset = 0x0, 78 .post_div_shift = 10, 79 .post_div_table = post_div_table_gcc_gpll0_out_even, 80 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 81 .width = 4, 82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 83 .clkr.hw.init = &(const struct clk_init_data) { 84 .name = "gcc_gpll0_out_even", 85 .parent_hws = (const struct clk_hw*[]) { 86 &gcc_gpll0.clkr.hw, 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 90 }, 91 }; 92 93 static struct clk_alpha_pll gcc_gpll4 = { 94 .offset = 0x4000, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 96 .clkr = { 97 .enable_reg = 0x52020, 98 .enable_mask = BIT(4), 99 .hw.init = &(const struct clk_init_data) { 100 .name = "gcc_gpll4", 101 .parent_data = &(const struct clk_parent_data) { 102 .index = DT_BI_TCXO, 103 }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 106 }, 107 }, 108 }; 109 110 static struct clk_alpha_pll gcc_gpll7 = { 111 .offset = 0x7000, 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 113 .clkr = { 114 .enable_reg = 0x52020, 115 .enable_mask = BIT(7), 116 .hw.init = &(const struct clk_init_data) { 117 .name = "gcc_gpll7", 118 .parent_data = &(const struct clk_parent_data) { 119 .index = DT_BI_TCXO, 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 123 }, 124 }, 125 }; 126 127 static struct clk_alpha_pll gcc_gpll8 = { 128 .offset = 0x8000, 129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 130 .clkr = { 131 .enable_reg = 0x52020, 132 .enable_mask = BIT(8), 133 .hw.init = &(const struct clk_init_data) { 134 .name = "gcc_gpll8", 135 .parent_data = &(const struct clk_parent_data) { 136 .index = DT_BI_TCXO, 137 }, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_alpha_pll gcc_gpll9 = { 145 .offset = 0x9000, 146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 147 .clkr = { 148 .enable_reg = 0x52020, 149 .enable_mask = BIT(9), 150 .hw.init = &(const struct clk_init_data) { 151 .name = "gcc_gpll9", 152 .parent_data = &(const struct clk_parent_data) { 153 .index = DT_BI_TCXO, 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 157 }, 158 }, 159 }; 160 161 static const struct parent_map gcc_parent_map_0[] = { 162 { P_BI_TCXO, 0 }, 163 { P_GCC_GPLL0_OUT_MAIN, 1 }, 164 { P_GCC_GPLL0_OUT_EVEN, 6 }, 165 }; 166 167 static const struct clk_parent_data gcc_parent_data_0[] = { 168 { .index = DT_BI_TCXO }, 169 { .hw = &gcc_gpll0.clkr.hw }, 170 { .hw = &gcc_gpll0_out_even.clkr.hw }, 171 }; 172 173 static const struct parent_map gcc_parent_map_1[] = { 174 { P_BI_TCXO, 0 }, 175 { P_GCC_GPLL0_OUT_MAIN, 1 }, 176 { P_SLEEP_CLK, 5 }, 177 { P_GCC_GPLL0_OUT_EVEN, 6 }, 178 }; 179 180 static const struct clk_parent_data gcc_parent_data_1[] = { 181 { .index = DT_BI_TCXO }, 182 { .hw = &gcc_gpll0.clkr.hw }, 183 { .index = DT_SLEEP_CLK }, 184 { .hw = &gcc_gpll0_out_even.clkr.hw }, 185 }; 186 187 static const struct parent_map gcc_parent_map_2[] = { 188 { P_BI_TCXO, 0 }, 189 { P_GCC_GPLL0_OUT_MAIN, 1 }, 190 { P_GCC_GPLL4_OUT_MAIN, 5 }, 191 { P_GCC_GPLL0_OUT_EVEN, 6 }, 192 }; 193 194 static const struct clk_parent_data gcc_parent_data_2[] = { 195 { .index = DT_BI_TCXO }, 196 { .hw = &gcc_gpll0.clkr.hw }, 197 { .hw = &gcc_gpll4.clkr.hw }, 198 { .hw = &gcc_gpll0_out_even.clkr.hw }, 199 }; 200 201 static const struct parent_map gcc_parent_map_3[] = { 202 { P_BI_TCXO, 0 }, 203 { P_SLEEP_CLK, 5 }, 204 }; 205 206 static const struct clk_parent_data gcc_parent_data_3[] = { 207 { .index = DT_BI_TCXO }, 208 { .index = DT_SLEEP_CLK }, 209 }; 210 211 static const struct parent_map gcc_parent_map_4[] = { 212 { P_BI_TCXO, 0 }, 213 { P_GCC_GPLL0_OUT_MAIN, 1 }, 214 { P_GCC_GPLL7_OUT_MAIN, 2 }, 215 { P_GCC_GPLL0_OUT_EVEN, 6 }, 216 }; 217 218 static const struct clk_parent_data gcc_parent_data_4[] = { 219 { .index = DT_BI_TCXO }, 220 { .hw = &gcc_gpll0.clkr.hw }, 221 { .hw = &gcc_gpll7.clkr.hw }, 222 { .hw = &gcc_gpll0_out_even.clkr.hw }, 223 }; 224 225 static const struct parent_map gcc_parent_map_5[] = { 226 { P_BI_TCXO, 0 }, 227 { P_GCC_GPLL0_OUT_MAIN, 1 }, 228 { P_GCC_GPLL8_OUT_MAIN, 2 }, 229 { P_GCC_GPLL0_OUT_EVEN, 6 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_5[] = { 233 { .index = DT_BI_TCXO }, 234 { .hw = &gcc_gpll0.clkr.hw }, 235 { .hw = &gcc_gpll8.clkr.hw }, 236 { .hw = &gcc_gpll0_out_even.clkr.hw }, 237 }; 238 239 static const struct parent_map gcc_parent_map_6[] = { 240 { P_BI_TCXO, 0 }, 241 }; 242 243 static const struct clk_parent_data gcc_parent_data_6[] = { 244 { .index = DT_BI_TCXO }, 245 }; 246 247 static const struct parent_map gcc_parent_map_7[] = { 248 { P_BI_TCXO, 0 }, 249 { P_GCC_GPLL0_OUT_MAIN, 1 }, 250 { P_GCC_GPLL9_OUT_MAIN, 2 }, 251 { P_GCC_GPLL4_OUT_MAIN, 5 }, 252 { P_GCC_GPLL0_OUT_EVEN, 6 }, 253 }; 254 255 static const struct clk_parent_data gcc_parent_data_7[] = { 256 { .index = DT_BI_TCXO }, 257 { .hw = &gcc_gpll0.clkr.hw }, 258 { .hw = &gcc_gpll9.clkr.hw }, 259 { .hw = &gcc_gpll4.clkr.hw }, 260 { .hw = &gcc_gpll0_out_even.clkr.hw }, 261 }; 262 263 static const struct parent_map gcc_parent_map_8[] = { 264 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 265 { P_BI_TCXO, 2 }, 266 { P_GCC_GPLL0_OUT_EVEN, 3 }, 267 }; 268 269 static const struct clk_parent_data gcc_parent_data_8[] = { 270 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 271 { .index = DT_BI_TCXO }, 272 { .hw = &gcc_gpll0_out_even.clkr.hw }, 273 }; 274 275 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 276 .reg = 0x6b080, 277 .clkr = { 278 .hw.init = &(const struct clk_init_data) { 279 .name = "gcc_pcie_0_pipe_clk_src", 280 .parent_data = &(const struct clk_parent_data){ 281 .index = DT_PCIE_0_PIPE_CLK, 282 }, 283 .num_parents = 1, 284 .ops = &clk_regmap_phy_mux_ops, 285 }, 286 }, 287 }; 288 289 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 290 .reg = 0xac07c, 291 .clkr = { 292 .hw.init = &(const struct clk_init_data) { 293 .name = "gcc_pcie_1_pipe_clk_src", 294 .parent_data = &(const struct clk_parent_data){ 295 .index = DT_PCIE_1_PIPE_CLK, 296 }, 297 .num_parents = 1, 298 .ops = &clk_regmap_phy_mux_ops, 299 }, 300 }, 301 }; 302 303 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 304 .reg = 0x77068, 305 .clkr = { 306 .hw.init = &(const struct clk_init_data) { 307 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 308 .parent_data = &(const struct clk_parent_data){ 309 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 310 }, 311 .num_parents = 1, 312 .ops = &clk_regmap_phy_mux_ops, 313 }, 314 }, 315 }; 316 317 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 318 .reg = 0x770ec, 319 .clkr = { 320 .hw.init = &(const struct clk_init_data) { 321 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 322 .parent_data = &(const struct clk_parent_data){ 323 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 324 }, 325 .num_parents = 1, 326 .ops = &clk_regmap_phy_mux_ops, 327 }, 328 }, 329 }; 330 331 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 332 .reg = 0x77058, 333 .clkr = { 334 .hw.init = &(const struct clk_init_data) { 335 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 336 .parent_data = &(const struct clk_parent_data){ 337 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 338 }, 339 .num_parents = 1, 340 .ops = &clk_regmap_phy_mux_ops, 341 }, 342 }, 343 }; 344 345 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 346 .reg = 0x39070, 347 .shift = 0, 348 .width = 2, 349 .parent_map = gcc_parent_map_8, 350 .clkr = { 351 .hw.init = &(const struct clk_init_data) { 352 .name = "gcc_usb3_prim_phy_pipe_clk_src", 353 .parent_data = gcc_parent_data_8, 354 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 355 .ops = &clk_regmap_mux_closest_ops, 356 }, 357 }, 358 }; 359 360 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 361 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 362 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 363 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 364 { } 365 }; 366 367 static struct clk_rcg2 gcc_gp1_clk_src = { 368 .cmd_rcgr = 0x64004, 369 .mnd_width = 16, 370 .hid_width = 5, 371 .parent_map = gcc_parent_map_1, 372 .freq_tbl = ftbl_gcc_gp1_clk_src, 373 .hw_clk_ctrl = true, 374 .clkr.hw.init = &(const struct clk_init_data) { 375 .name = "gcc_gp1_clk_src", 376 .parent_data = gcc_parent_data_1, 377 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 378 .flags = CLK_SET_RATE_PARENT, 379 .ops = &clk_rcg2_shared_ops, 380 }, 381 }; 382 383 static struct clk_rcg2 gcc_gp2_clk_src = { 384 .cmd_rcgr = 0x65004, 385 .mnd_width = 16, 386 .hid_width = 5, 387 .parent_map = gcc_parent_map_1, 388 .freq_tbl = ftbl_gcc_gp1_clk_src, 389 .hw_clk_ctrl = true, 390 .clkr.hw.init = &(const struct clk_init_data) { 391 .name = "gcc_gp2_clk_src", 392 .parent_data = gcc_parent_data_1, 393 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 394 .flags = CLK_SET_RATE_PARENT, 395 .ops = &clk_rcg2_shared_ops, 396 }, 397 }; 398 399 static struct clk_rcg2 gcc_gp3_clk_src = { 400 .cmd_rcgr = 0x66004, 401 .mnd_width = 16, 402 .hid_width = 5, 403 .parent_map = gcc_parent_map_1, 404 .freq_tbl = ftbl_gcc_gp1_clk_src, 405 .hw_clk_ctrl = true, 406 .clkr.hw.init = &(const struct clk_init_data) { 407 .name = "gcc_gp3_clk_src", 408 .parent_data = gcc_parent_data_1, 409 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 410 .flags = CLK_SET_RATE_PARENT, 411 .ops = &clk_rcg2_shared_ops, 412 }, 413 }; 414 415 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 416 F(19200000, P_BI_TCXO, 1, 0, 0), 417 { } 418 }; 419 420 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 421 .cmd_rcgr = 0x6b084, 422 .mnd_width = 16, 423 .hid_width = 5, 424 .parent_map = gcc_parent_map_3, 425 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 426 .hw_clk_ctrl = true, 427 .clkr.hw.init = &(const struct clk_init_data) { 428 .name = "gcc_pcie_0_aux_clk_src", 429 .parent_data = gcc_parent_data_3, 430 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 431 .flags = CLK_SET_RATE_PARENT, 432 .ops = &clk_rcg2_shared_ops, 433 }, 434 }; 435 436 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 437 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 438 { } 439 }; 440 441 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 442 .cmd_rcgr = 0x6b068, 443 .mnd_width = 0, 444 .hid_width = 5, 445 .parent_map = gcc_parent_map_0, 446 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 447 .hw_clk_ctrl = true, 448 .clkr.hw.init = &(const struct clk_init_data) { 449 .name = "gcc_pcie_0_phy_rchng_clk_src", 450 .parent_data = gcc_parent_data_0, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 452 .flags = CLK_SET_RATE_PARENT, 453 .ops = &clk_rcg2_shared_ops, 454 }, 455 }; 456 457 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 458 .cmd_rcgr = 0xac080, 459 .mnd_width = 16, 460 .hid_width = 5, 461 .parent_map = gcc_parent_map_3, 462 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 463 .hw_clk_ctrl = true, 464 .clkr.hw.init = &(const struct clk_init_data) { 465 .name = "gcc_pcie_1_aux_clk_src", 466 .parent_data = gcc_parent_data_3, 467 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 468 .flags = CLK_SET_RATE_PARENT, 469 .ops = &clk_rcg2_shared_ops, 470 }, 471 }; 472 473 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 474 .cmd_rcgr = 0xac064, 475 .mnd_width = 0, 476 .hid_width = 5, 477 .parent_map = gcc_parent_map_0, 478 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 479 .hw_clk_ctrl = true, 480 .clkr.hw.init = &(const struct clk_init_data) { 481 .name = "gcc_pcie_1_phy_rchng_clk_src", 482 .parent_data = gcc_parent_data_0, 483 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 484 .flags = CLK_SET_RATE_PARENT, 485 .ops = &clk_rcg2_shared_ops, 486 }, 487 }; 488 489 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 490 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 491 { } 492 }; 493 494 static struct clk_rcg2 gcc_pdm2_clk_src = { 495 .cmd_rcgr = 0x33010, 496 .mnd_width = 0, 497 .hid_width = 5, 498 .parent_map = gcc_parent_map_0, 499 .freq_tbl = ftbl_gcc_pdm2_clk_src, 500 .hw_clk_ctrl = true, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "gcc_pdm2_clk_src", 503 .parent_data = gcc_parent_data_0, 504 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 505 .flags = CLK_SET_RATE_PARENT, 506 .ops = &clk_rcg2_shared_ops, 507 }, 508 }; 509 510 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 511 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 512 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 513 F(19200000, P_BI_TCXO, 1, 0, 0), 514 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 515 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 516 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 517 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 518 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 519 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 520 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 521 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 522 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 523 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 524 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 525 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 526 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 527 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 528 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 529 { } 530 }; 531 532 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 533 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 534 .parent_data = gcc_parent_data_4, 535 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 536 .flags = CLK_SET_RATE_PARENT, 537 .ops = &clk_rcg2_shared_no_init_park_ops, 538 }; 539 540 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 541 .cmd_rcgr = 0x188c0, 542 .mnd_width = 16, 543 .hid_width = 5, 544 .parent_map = gcc_parent_map_4, 545 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 546 .hw_clk_ctrl = true, 547 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 548 }; 549 550 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 551 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 552 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 553 F(19200000, P_BI_TCXO, 1, 0, 0), 554 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 555 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 556 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 557 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 558 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 559 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 560 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 561 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 562 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 563 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 564 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 565 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 566 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 567 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 568 { } 569 }; 570 571 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 572 .name = "gcc_qupv3_wrap1_s0_clk_src", 573 .parent_data = gcc_parent_data_0, 574 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 575 .flags = CLK_SET_RATE_PARENT, 576 .ops = &clk_rcg2_shared_no_init_park_ops, 577 }; 578 579 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 580 .cmd_rcgr = 0x18014, 581 .mnd_width = 16, 582 .hid_width = 5, 583 .parent_map = gcc_parent_map_0, 584 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 585 .hw_clk_ctrl = true, 586 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 587 }; 588 589 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 590 .name = "gcc_qupv3_wrap1_s1_clk_src", 591 .parent_data = gcc_parent_data_0, 592 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 593 .flags = CLK_SET_RATE_PARENT, 594 .ops = &clk_rcg2_shared_no_init_park_ops, 595 }; 596 597 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 598 .cmd_rcgr = 0x18150, 599 .mnd_width = 16, 600 .hid_width = 5, 601 .parent_map = gcc_parent_map_0, 602 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 603 .hw_clk_ctrl = true, 604 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 605 }; 606 607 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = { 608 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 609 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 610 F(19200000, P_BI_TCXO, 1, 0, 0), 611 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 612 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 613 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 614 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 615 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 616 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 617 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 618 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 619 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 620 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 621 { } 622 }; 623 624 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 625 .name = "gcc_qupv3_wrap1_s3_clk_src", 626 .parent_data = gcc_parent_data_0, 627 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 628 .flags = CLK_SET_RATE_PARENT, 629 .ops = &clk_rcg2_shared_no_init_park_ops, 630 }; 631 632 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 633 .cmd_rcgr = 0x182a0, 634 .mnd_width = 16, 635 .hid_width = 5, 636 .parent_map = gcc_parent_map_0, 637 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 638 .hw_clk_ctrl = true, 639 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 640 }; 641 642 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 643 .name = "gcc_qupv3_wrap1_s4_clk_src", 644 .parent_data = gcc_parent_data_0, 645 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_rcg2_shared_no_init_park_ops, 648 }; 649 650 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 651 .cmd_rcgr = 0x183dc, 652 .mnd_width = 16, 653 .hid_width = 5, 654 .parent_map = gcc_parent_map_0, 655 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 656 .hw_clk_ctrl = true, 657 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 658 }; 659 660 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s5_clk_src[] = { 661 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 662 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 663 F(19200000, P_BI_TCXO, 1, 0, 0), 664 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 665 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 666 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 667 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 668 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 669 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 670 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 671 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 672 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 673 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 674 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 675 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 676 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 677 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 678 { } 679 }; 680 681 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 682 .name = "gcc_qupv3_wrap1_s5_clk_src", 683 .parent_data = gcc_parent_data_0, 684 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_rcg2_shared_no_init_park_ops, 687 }; 688 689 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 690 .cmd_rcgr = 0x18518, 691 .mnd_width = 16, 692 .hid_width = 5, 693 .parent_map = gcc_parent_map_0, 694 .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src, 695 .hw_clk_ctrl = true, 696 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 697 }; 698 699 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 700 .name = "gcc_qupv3_wrap1_s6_clk_src", 701 .parent_data = gcc_parent_data_0, 702 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 703 .flags = CLK_SET_RATE_PARENT, 704 .ops = &clk_rcg2_shared_no_init_park_ops, 705 }; 706 707 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 708 .cmd_rcgr = 0x18654, 709 .mnd_width = 16, 710 .hid_width = 5, 711 .parent_map = gcc_parent_map_0, 712 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 713 .hw_clk_ctrl = true, 714 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 715 }; 716 717 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 718 .name = "gcc_qupv3_wrap1_s7_clk_src", 719 .parent_data = gcc_parent_data_0, 720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 721 .flags = CLK_SET_RATE_PARENT, 722 .ops = &clk_rcg2_shared_no_init_park_ops, 723 }; 724 725 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 726 .cmd_rcgr = 0x18790, 727 .mnd_width = 16, 728 .hid_width = 5, 729 .parent_map = gcc_parent_map_0, 730 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 731 .hw_clk_ctrl = true, 732 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 733 }; 734 735 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 736 .name = "gcc_qupv3_wrap2_s0_clk_src", 737 .parent_data = gcc_parent_data_0, 738 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 739 .flags = CLK_SET_RATE_PARENT, 740 .ops = &clk_rcg2_shared_no_init_park_ops, 741 }; 742 743 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 744 .cmd_rcgr = 0x1e014, 745 .mnd_width = 16, 746 .hid_width = 5, 747 .parent_map = gcc_parent_map_0, 748 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 749 .hw_clk_ctrl = true, 750 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 751 }; 752 753 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 754 .name = "gcc_qupv3_wrap2_s1_clk_src", 755 .parent_data = gcc_parent_data_0, 756 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 757 .flags = CLK_SET_RATE_PARENT, 758 .ops = &clk_rcg2_shared_no_init_park_ops, 759 }; 760 761 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 762 .cmd_rcgr = 0x1e150, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = gcc_parent_map_0, 766 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 767 .hw_clk_ctrl = true, 768 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 769 }; 770 771 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s2_clk_src[] = { 772 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 773 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 774 F(19200000, P_BI_TCXO, 1, 0, 0), 775 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 776 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 777 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 778 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 779 F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625), 780 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 781 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 782 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 783 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 784 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 785 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 786 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 787 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 788 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 789 { } 790 }; 791 792 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 793 .name = "gcc_qupv3_wrap2_s2_clk_src", 794 .parent_data = gcc_parent_data_4, 795 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 796 .flags = CLK_SET_RATE_PARENT, 797 .ops = &clk_rcg2_shared_no_init_park_ops, 798 }; 799 800 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 801 .cmd_rcgr = 0x1e28c, 802 .mnd_width = 16, 803 .hid_width = 5, 804 .parent_map = gcc_parent_map_4, 805 .freq_tbl = ftbl_gcc_qupv3_wrap2_s2_clk_src, 806 .hw_clk_ctrl = true, 807 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 808 }; 809 810 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 811 .name = "gcc_qupv3_wrap2_s3_clk_src", 812 .parent_data = gcc_parent_data_0, 813 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 814 .flags = CLK_SET_RATE_PARENT, 815 .ops = &clk_rcg2_shared_no_init_park_ops, 816 }; 817 818 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 819 .cmd_rcgr = 0x1e3c8, 820 .mnd_width = 16, 821 .hid_width = 5, 822 .parent_map = gcc_parent_map_0, 823 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 824 .hw_clk_ctrl = true, 825 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 826 }; 827 828 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 829 .name = "gcc_qupv3_wrap2_s4_clk_src", 830 .parent_data = gcc_parent_data_0, 831 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 832 .flags = CLK_SET_RATE_PARENT, 833 .ops = &clk_rcg2_shared_no_init_park_ops, 834 }; 835 836 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 837 .cmd_rcgr = 0x1e504, 838 .mnd_width = 16, 839 .hid_width = 5, 840 .parent_map = gcc_parent_map_0, 841 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 842 .hw_clk_ctrl = true, 843 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 844 }; 845 846 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 847 .name = "gcc_qupv3_wrap2_s5_clk_src", 848 .parent_data = gcc_parent_data_0, 849 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 850 .flags = CLK_SET_RATE_PARENT, 851 .ops = &clk_rcg2_shared_no_init_park_ops, 852 }; 853 854 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 855 .cmd_rcgr = 0x1e640, 856 .mnd_width = 16, 857 .hid_width = 5, 858 .parent_map = gcc_parent_map_0, 859 .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src, 860 .hw_clk_ctrl = true, 861 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 862 }; 863 864 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 865 .name = "gcc_qupv3_wrap2_s6_clk_src", 866 .parent_data = gcc_parent_data_4, 867 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 868 .flags = CLK_SET_RATE_PARENT, 869 .ops = &clk_rcg2_shared_no_init_park_ops, 870 }; 871 872 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 873 .cmd_rcgr = 0x1e77c, 874 .mnd_width = 16, 875 .hid_width = 5, 876 .parent_map = gcc_parent_map_4, 877 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 878 .hw_clk_ctrl = true, 879 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 880 }; 881 882 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 883 .name = "gcc_qupv3_wrap2_s7_clk_src", 884 .parent_data = gcc_parent_data_0, 885 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 886 .flags = CLK_SET_RATE_PARENT, 887 .ops = &clk_rcg2_shared_no_init_park_ops, 888 }; 889 890 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 891 .cmd_rcgr = 0x1e8b8, 892 .mnd_width = 16, 893 .hid_width = 5, 894 .parent_map = gcc_parent_map_0, 895 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 896 .hw_clk_ctrl = true, 897 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 898 }; 899 900 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 901 F(144000, P_BI_TCXO, 16, 3, 25), 902 F(400000, P_BI_TCXO, 12, 1, 4), 903 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 904 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 905 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 906 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 907 F(192000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 908 F(384000000, P_GCC_GPLL8_OUT_MAIN, 1, 0, 0), 909 { } 910 }; 911 912 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 913 .cmd_rcgr = 0xa9018, 914 .mnd_width = 8, 915 .hid_width = 5, 916 .parent_map = gcc_parent_map_5, 917 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 918 .hw_clk_ctrl = true, 919 .clkr.hw.init = &(const struct clk_init_data) { 920 .name = "gcc_sdcc1_apps_clk_src", 921 .parent_data = gcc_parent_data_5, 922 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_rcg2_shared_floor_ops, 925 }, 926 }; 927 928 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 929 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 930 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 931 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 932 { } 933 }; 934 935 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 936 .cmd_rcgr = 0xa9040, 937 .mnd_width = 0, 938 .hid_width = 5, 939 .parent_map = gcc_parent_map_5, 940 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 941 .hw_clk_ctrl = true, 942 .clkr.hw.init = &(const struct clk_init_data) { 943 .name = "gcc_sdcc1_ice_core_clk_src", 944 .parent_data = gcc_parent_data_5, 945 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 946 .flags = CLK_SET_RATE_PARENT, 947 .ops = &clk_rcg2_shared_floor_ops, 948 }, 949 }; 950 951 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 952 F(400000, P_BI_TCXO, 12, 1, 4), 953 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 954 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 955 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 956 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 957 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 958 { } 959 }; 960 961 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 962 .cmd_rcgr = 0x1401c, 963 .mnd_width = 8, 964 .hid_width = 5, 965 .parent_map = gcc_parent_map_7, 966 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 967 .hw_clk_ctrl = true, 968 .clkr.hw.init = &(const struct clk_init_data) { 969 .name = "gcc_sdcc2_apps_clk_src", 970 .parent_data = gcc_parent_data_7, 971 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 972 .flags = CLK_SET_RATE_PARENT, 973 .ops = &clk_rcg2_shared_floor_ops, 974 }, 975 }; 976 977 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 978 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 979 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 980 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 981 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 986 .cmd_rcgr = 0x77034, 987 .mnd_width = 8, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_2, 990 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 991 .hw_clk_ctrl = true, 992 .clkr.hw.init = &(const struct clk_init_data) { 993 .name = "gcc_ufs_phy_axi_clk_src", 994 .parent_data = gcc_parent_data_2, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_rcg2_shared_no_init_park_ops, 998 }, 999 }; 1000 1001 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1002 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1003 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1004 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1005 { } 1006 }; 1007 1008 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1009 .cmd_rcgr = 0x7708c, 1010 .mnd_width = 0, 1011 .hid_width = 5, 1012 .parent_map = gcc_parent_map_2, 1013 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1014 .hw_clk_ctrl = true, 1015 .clkr.hw.init = &(const struct clk_init_data) { 1016 .name = "gcc_ufs_phy_ice_core_clk_src", 1017 .parent_data = gcc_parent_data_2, 1018 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_rcg2_shared_no_init_park_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1025 F(9600000, P_BI_TCXO, 2, 0, 0), 1026 F(19200000, P_BI_TCXO, 1, 0, 0), 1027 { } 1028 }; 1029 1030 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1031 .cmd_rcgr = 0x770c0, 1032 .mnd_width = 0, 1033 .hid_width = 5, 1034 .parent_map = gcc_parent_map_6, 1035 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1036 .hw_clk_ctrl = true, 1037 .clkr.hw.init = &(const struct clk_init_data) { 1038 .name = "gcc_ufs_phy_phy_aux_clk_src", 1039 .parent_data = gcc_parent_data_6, 1040 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_rcg2_shared_no_init_park_ops, 1043 }, 1044 }; 1045 1046 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1047 .cmd_rcgr = 0x770a4, 1048 .mnd_width = 0, 1049 .hid_width = 5, 1050 .parent_map = gcc_parent_map_2, 1051 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1052 .hw_clk_ctrl = true, 1053 .clkr.hw.init = &(const struct clk_init_data) { 1054 .name = "gcc_ufs_phy_unipro_core_clk_src", 1055 .parent_data = gcc_parent_data_2, 1056 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_rcg2_shared_no_init_park_ops, 1059 }, 1060 }; 1061 1062 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1063 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1064 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1065 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1066 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1067 { } 1068 }; 1069 1070 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1071 .cmd_rcgr = 0x39030, 1072 .mnd_width = 8, 1073 .hid_width = 5, 1074 .parent_map = gcc_parent_map_0, 1075 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1076 .hw_clk_ctrl = true, 1077 .clkr.hw.init = &(const struct clk_init_data) { 1078 .name = "gcc_usb30_prim_master_clk_src", 1079 .parent_data = gcc_parent_data_0, 1080 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1081 .flags = CLK_SET_RATE_PARENT, 1082 .ops = &clk_rcg2_shared_ops, 1083 }, 1084 }; 1085 1086 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1087 .cmd_rcgr = 0x39048, 1088 .mnd_width = 0, 1089 .hid_width = 5, 1090 .parent_map = gcc_parent_map_0, 1091 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1092 .hw_clk_ctrl = true, 1093 .clkr.hw.init = &(const struct clk_init_data) { 1094 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1095 .parent_data = gcc_parent_data_0, 1096 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1097 .flags = CLK_SET_RATE_PARENT, 1098 .ops = &clk_rcg2_shared_ops, 1099 }, 1100 }; 1101 1102 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1103 .cmd_rcgr = 0x39074, 1104 .mnd_width = 0, 1105 .hid_width = 5, 1106 .parent_map = gcc_parent_map_3, 1107 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1108 .hw_clk_ctrl = true, 1109 .clkr.hw.init = &(const struct clk_init_data) { 1110 .name = "gcc_usb3_prim_phy_aux_clk_src", 1111 .parent_data = gcc_parent_data_3, 1112 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1113 .flags = CLK_SET_RATE_PARENT, 1114 .ops = &clk_rcg2_shared_ops, 1115 }, 1116 }; 1117 1118 static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = { 1119 .reg = 0x6b0a4, 1120 .shift = 0, 1121 .width = 4, 1122 .clkr.hw.init = &(const struct clk_init_data) { 1123 .name = "gcc_pcie_0_pipe_div2_clk_src", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_regmap_div_ro_ops, 1130 }, 1131 }; 1132 1133 static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = { 1134 .reg = 0xac0a0, 1135 .shift = 0, 1136 .width = 4, 1137 .clkr.hw.init = &(const struct clk_init_data) { 1138 .name = "gcc_pcie_1_pipe_div2_clk_src", 1139 .parent_hws = (const struct clk_hw*[]) { 1140 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 .ops = &clk_regmap_div_ro_ops, 1145 }, 1146 }; 1147 1148 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1149 .reg = 0x1828c, 1150 .shift = 0, 1151 .width = 4, 1152 .clkr.hw.init = &(const struct clk_init_data) { 1153 .name = "gcc_qupv3_wrap1_s2_clk_src", 1154 .parent_hws = (const struct clk_hw*[]) { 1155 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 .ops = &clk_regmap_div_ro_ops, 1160 }, 1161 }; 1162 1163 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1164 .reg = 0x39060, 1165 .shift = 0, 1166 .width = 4, 1167 .clkr.hw.init = &(const struct clk_init_data) { 1168 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1169 .parent_hws = (const struct clk_hw*[]) { 1170 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_regmap_div_ro_ops, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1179 .halt_reg = 0x10068, 1180 .halt_check = BRANCH_HALT_SKIP, 1181 .hwcg_reg = 0x10068, 1182 .hwcg_bit = 1, 1183 .clkr = { 1184 .enable_reg = 0x52000, 1185 .enable_mask = BIT(30), 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "gcc_aggre_noc_pcie_axi_clk", 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1194 .halt_reg = 0x770f4, 1195 .halt_check = BRANCH_HALT_VOTED, 1196 .hwcg_reg = 0x770f4, 1197 .hwcg_bit = 1, 1198 .clkr = { 1199 .enable_reg = 0x770f4, 1200 .enable_mask = BIT(0), 1201 .hw.init = &(const struct clk_init_data) { 1202 .name = "gcc_aggre_ufs_phy_axi_clk", 1203 .parent_hws = (const struct clk_hw*[]) { 1204 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1205 }, 1206 .num_parents = 1, 1207 .flags = CLK_SET_RATE_PARENT, 1208 .ops = &clk_branch2_ops, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1214 .halt_reg = 0x39094, 1215 .halt_check = BRANCH_HALT_VOTED, 1216 .clkr = { 1217 .enable_reg = 0x39094, 1218 .enable_mask = BIT(0), 1219 .hw.init = &(const struct clk_init_data) { 1220 .name = "gcc_aggre_usb3_prim_axi_clk", 1221 .parent_hws = (const struct clk_hw*[]) { 1222 &gcc_usb30_prim_master_clk_src.clkr.hw, 1223 }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch gcc_boot_rom_ahb_clk = { 1232 .halt_reg = 0x38004, 1233 .halt_check = BRANCH_HALT_VOTED, 1234 .hwcg_reg = 0x38004, 1235 .hwcg_bit = 1, 1236 .clkr = { 1237 .enable_reg = 0x52000, 1238 .enable_mask = BIT(10), 1239 .hw.init = &(const struct clk_init_data) { 1240 .name = "gcc_boot_rom_ahb_clk", 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_camera_hf_axi_clk = { 1247 .halt_reg = 0x26014, 1248 .halt_check = BRANCH_HALT_SKIP, 1249 .hwcg_reg = 0x26014, 1250 .hwcg_bit = 1, 1251 .clkr = { 1252 .enable_reg = 0x26014, 1253 .enable_mask = BIT(0), 1254 .hw.init = &(const struct clk_init_data) { 1255 .name = "gcc_camera_hf_axi_clk", 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch gcc_camera_sf_axi_clk = { 1262 .halt_reg = 0x26024, 1263 .halt_check = BRANCH_HALT_SKIP, 1264 .hwcg_reg = 0x26024, 1265 .hwcg_bit = 1, 1266 .clkr = { 1267 .enable_reg = 0x26024, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "gcc_camera_sf_axi_clk", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1277 .halt_reg = 0x10050, 1278 .halt_check = BRANCH_HALT_SKIP, 1279 .hwcg_reg = 0x10050, 1280 .hwcg_bit = 1, 1281 .clkr = { 1282 .enable_reg = 0x52000, 1283 .enable_mask = BIT(20), 1284 .hw.init = &(const struct clk_init_data) { 1285 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1292 .halt_reg = 0x39090, 1293 .halt_check = BRANCH_HALT_VOTED, 1294 .clkr = { 1295 .enable_reg = 0x39090, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(const struct clk_init_data) { 1298 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1299 .parent_hws = (const struct clk_hw*[]) { 1300 &gcc_usb30_prim_master_clk_src.clkr.hw, 1301 }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_branch2_ops, 1305 }, 1306 }, 1307 }; 1308 1309 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1310 .halt_reg = 0x10058, 1311 .halt_check = BRANCH_HALT_VOTED, 1312 .hwcg_reg = 0x10058, 1313 .hwcg_bit = 1, 1314 .clkr = { 1315 .enable_reg = 0x52008, 1316 .enable_mask = BIT(6), 1317 .hw.init = &(const struct clk_init_data) { 1318 .name = "gcc_cnoc_pcie_sf_axi_clk", 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1325 .halt_reg = 0x71158, 1326 .halt_check = BRANCH_HALT_SKIP, 1327 .hwcg_reg = 0x71158, 1328 .hwcg_bit = 1, 1329 .clkr = { 1330 .enable_reg = 0x71158, 1331 .enable_mask = BIT(0), 1332 .hw.init = &(const struct clk_init_data) { 1333 .name = "gcc_ddrss_gpu_axi_clk", 1334 .ops = &clk_branch2_aon_ops, 1335 }, 1336 }, 1337 }; 1338 1339 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1340 .halt_reg = 0x1007c, 1341 .halt_check = BRANCH_HALT_SKIP, 1342 .hwcg_reg = 0x1007c, 1343 .hwcg_bit = 1, 1344 .clkr = { 1345 .enable_reg = 0x52000, 1346 .enable_mask = BIT(19), 1347 .hw.init = &(const struct clk_init_data) { 1348 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_disp_hf_axi_clk = { 1355 .halt_reg = 0x27008, 1356 .halt_check = BRANCH_HALT_SKIP, 1357 .clkr = { 1358 .enable_reg = 0x27008, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "gcc_disp_hf_axi_clk", 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_gp1_clk = { 1368 .halt_reg = 0x64000, 1369 .halt_check = BRANCH_HALT, 1370 .clkr = { 1371 .enable_reg = 0x64000, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(const struct clk_init_data) { 1374 .name = "gcc_gp1_clk", 1375 .parent_hws = (const struct clk_hw*[]) { 1376 &gcc_gp1_clk_src.clkr.hw, 1377 }, 1378 .num_parents = 1, 1379 .flags = CLK_SET_RATE_PARENT, 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383 }; 1384 1385 static struct clk_branch gcc_gp2_clk = { 1386 .halt_reg = 0x65000, 1387 .halt_check = BRANCH_HALT, 1388 .clkr = { 1389 .enable_reg = 0x65000, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(const struct clk_init_data) { 1392 .name = "gcc_gp2_clk", 1393 .parent_hws = (const struct clk_hw*[]) { 1394 &gcc_gp2_clk_src.clkr.hw, 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch gcc_gp3_clk = { 1404 .halt_reg = 0x66000, 1405 .halt_check = BRANCH_HALT, 1406 .clkr = { 1407 .enable_reg = 0x66000, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(const struct clk_init_data) { 1410 .name = "gcc_gp3_clk", 1411 .parent_hws = (const struct clk_hw*[]) { 1412 &gcc_gp3_clk_src.clkr.hw, 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1422 .halt_reg = 0x71010, 1423 .halt_check = BRANCH_HALT_VOTED, 1424 .hwcg_reg = 0x71010, 1425 .hwcg_bit = 1, 1426 .clkr = { 1427 .enable_reg = 0x71010, 1428 .enable_mask = BIT(0), 1429 .hw.init = &(const struct clk_init_data) { 1430 .name = "gcc_gpu_gemnoc_gfx_clk", 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch gcc_gpu_gpll0_cph_clk_src = { 1437 .halt_reg = 0x71150, 1438 .halt_check = BRANCH_HALT_ENABLE_VOTED, 1439 .clkr = { 1440 .enable_reg = 0x71150, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "gcc_gpu_gpll0_cph_clk_src", 1444 .parent_hws = (const struct clk_hw*[]) { 1445 &gcc_gpll0.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = { 1455 .halt_reg = 0x71154, 1456 .halt_check = BRANCH_HALT_ENABLE_VOTED, 1457 .clkr = { 1458 .enable_reg = 0x71154, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "gcc_gpu_gpll0_div_cph_clk_src", 1462 .parent_hws = (const struct clk_hw*[]) { 1463 &gcc_gpll0_out_even.clkr.hw, 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch gcc_gpu_smmu_vote_clk = { 1473 .halt_reg = 0x7d000, 1474 .halt_check = BRANCH_HALT_VOTED, 1475 .clkr = { 1476 .enable_reg = 0x7d000, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(const struct clk_init_data) { 1479 .name = "gcc_gpu_smmu_vote_clk", 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_mmu_tcu_vote_clk = { 1486 .halt_reg = 0x7d02c, 1487 .halt_check = BRANCH_HALT_VOTED, 1488 .clkr = { 1489 .enable_reg = 0x7d02c, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(const struct clk_init_data) { 1492 .name = "gcc_mmu_tcu_vote_clk", 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_pcie_0_aux_clk = { 1499 .halt_reg = 0x6b044, 1500 .halt_check = BRANCH_HALT_VOTED, 1501 .clkr = { 1502 .enable_reg = 0x52008, 1503 .enable_mask = BIT(3), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_pcie_0_aux_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &gcc_pcie_0_aux_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1517 .halt_reg = 0x6b040, 1518 .halt_check = BRANCH_HALT_VOTED, 1519 .hwcg_reg = 0x6b040, 1520 .hwcg_bit = 1, 1521 .clkr = { 1522 .enable_reg = 0x52008, 1523 .enable_mask = BIT(2), 1524 .hw.init = &(const struct clk_init_data) { 1525 .name = "gcc_pcie_0_cfg_ahb_clk", 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1532 .halt_reg = 0x6b030, 1533 .halt_check = BRANCH_HALT_SKIP, 1534 .hwcg_reg = 0x6b030, 1535 .hwcg_bit = 1, 1536 .clkr = { 1537 .enable_reg = 0x52008, 1538 .enable_mask = BIT(1), 1539 .hw.init = &(const struct clk_init_data) { 1540 .name = "gcc_pcie_0_mstr_axi_clk", 1541 .ops = &clk_branch2_ops, 1542 }, 1543 }, 1544 }; 1545 1546 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1547 .halt_reg = 0x6b064, 1548 .halt_check = BRANCH_HALT_VOTED, 1549 .clkr = { 1550 .enable_reg = 0x52000, 1551 .enable_mask = BIT(22), 1552 .hw.init = &(const struct clk_init_data) { 1553 .name = "gcc_pcie_0_phy_rchng_clk", 1554 .parent_hws = (const struct clk_hw*[]) { 1555 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1556 }, 1557 .num_parents = 1, 1558 .flags = CLK_SET_RATE_PARENT, 1559 .ops = &clk_branch2_ops, 1560 }, 1561 }, 1562 }; 1563 1564 static struct clk_branch gcc_pcie_0_pipe_clk = { 1565 .halt_reg = 0x6b054, 1566 .halt_check = BRANCH_HALT_SKIP, 1567 .clkr = { 1568 .enable_reg = 0x52008, 1569 .enable_mask = BIT(4), 1570 .hw.init = &(const struct clk_init_data) { 1571 .name = "gcc_pcie_0_pipe_clk", 1572 .parent_hws = (const struct clk_hw*[]) { 1573 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1574 }, 1575 .num_parents = 1, 1576 .flags = CLK_SET_RATE_PARENT, 1577 .ops = &clk_branch2_ops, 1578 }, 1579 }, 1580 }; 1581 1582 static struct clk_branch gcc_pcie_0_pipe_div2_clk = { 1583 .halt_reg = 0x6b0a8, 1584 .halt_check = BRANCH_HALT_SKIP, 1585 .clkr = { 1586 .enable_reg = 0x52018, 1587 .enable_mask = BIT(13), 1588 .hw.init = &(const struct clk_init_data) { 1589 .name = "gcc_pcie_0_pipe_div2_clk", 1590 .parent_hws = (const struct clk_hw*[]) { 1591 &gcc_pcie_0_pipe_div2_clk_src.clkr.hw, 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1601 .halt_reg = 0x6b020, 1602 .halt_check = BRANCH_HALT_VOTED, 1603 .hwcg_reg = 0x6b020, 1604 .hwcg_bit = 1, 1605 .clkr = { 1606 .enable_reg = 0x52008, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(const struct clk_init_data) { 1609 .name = "gcc_pcie_0_slv_axi_clk", 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1616 .halt_reg = 0x6b01c, 1617 .halt_check = BRANCH_HALT_VOTED, 1618 .clkr = { 1619 .enable_reg = 0x52008, 1620 .enable_mask = BIT(5), 1621 .hw.init = &(const struct clk_init_data) { 1622 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1623 .ops = &clk_branch2_ops, 1624 }, 1625 }, 1626 }; 1627 1628 static struct clk_branch gcc_pcie_1_aux_clk = { 1629 .halt_reg = 0xac040, 1630 .halt_check = BRANCH_HALT_VOTED, 1631 .clkr = { 1632 .enable_reg = 0x52000, 1633 .enable_mask = BIT(29), 1634 .hw.init = &(const struct clk_init_data) { 1635 .name = "gcc_pcie_1_aux_clk", 1636 .parent_hws = (const struct clk_hw*[]) { 1637 &gcc_pcie_1_aux_clk_src.clkr.hw, 1638 }, 1639 .num_parents = 1, 1640 .flags = CLK_SET_RATE_PARENT, 1641 .ops = &clk_branch2_ops, 1642 }, 1643 }, 1644 }; 1645 1646 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1647 .halt_reg = 0xac03c, 1648 .halt_check = BRANCH_HALT_VOTED, 1649 .hwcg_reg = 0xac03c, 1650 .hwcg_bit = 1, 1651 .clkr = { 1652 .enable_reg = 0x52000, 1653 .enable_mask = BIT(28), 1654 .hw.init = &(const struct clk_init_data) { 1655 .name = "gcc_pcie_1_cfg_ahb_clk", 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1662 .halt_reg = 0xac02c, 1663 .halt_check = BRANCH_HALT_SKIP, 1664 .hwcg_reg = 0xac02c, 1665 .hwcg_bit = 1, 1666 .clkr = { 1667 .enable_reg = 0x52000, 1668 .enable_mask = BIT(27), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "gcc_pcie_1_mstr_axi_clk", 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1677 .halt_reg = 0xac060, 1678 .halt_check = BRANCH_HALT_VOTED, 1679 .clkr = { 1680 .enable_reg = 0x52000, 1681 .enable_mask = BIT(24), 1682 .hw.init = &(const struct clk_init_data) { 1683 .name = "gcc_pcie_1_phy_rchng_clk", 1684 .parent_hws = (const struct clk_hw*[]) { 1685 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1686 }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_pcie_1_pipe_clk = { 1695 .halt_reg = 0xac050, 1696 .halt_check = BRANCH_HALT_SKIP, 1697 .clkr = { 1698 .enable_reg = 0x52000, 1699 .enable_mask = BIT(23), 1700 .hw.init = &(const struct clk_init_data) { 1701 .name = "gcc_pcie_1_pipe_clk", 1702 .parent_hws = (const struct clk_hw*[]) { 1703 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1704 }, 1705 .num_parents = 1, 1706 .flags = CLK_SET_RATE_PARENT, 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch gcc_pcie_1_pipe_div2_clk = { 1713 .halt_reg = 0xac0a4, 1714 .halt_check = BRANCH_HALT_SKIP, 1715 .clkr = { 1716 .enable_reg = 0x52018, 1717 .enable_mask = BIT(15), 1718 .hw.init = &(const struct clk_init_data) { 1719 .name = "gcc_pcie_1_pipe_div2_clk", 1720 .parent_hws = (const struct clk_hw*[]) { 1721 &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, 1722 }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1731 .halt_reg = 0xac01c, 1732 .halt_check = BRANCH_HALT_VOTED, 1733 .hwcg_reg = 0xac01c, 1734 .hwcg_bit = 1, 1735 .clkr = { 1736 .enable_reg = 0x52000, 1737 .enable_mask = BIT(26), 1738 .hw.init = &(const struct clk_init_data) { 1739 .name = "gcc_pcie_1_slv_axi_clk", 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1746 .halt_reg = 0xac018, 1747 .halt_check = BRANCH_HALT_VOTED, 1748 .clkr = { 1749 .enable_reg = 0x52000, 1750 .enable_mask = BIT(25), 1751 .hw.init = &(const struct clk_init_data) { 1752 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_pdm2_clk = { 1759 .halt_reg = 0x3300c, 1760 .halt_check = BRANCH_HALT, 1761 .clkr = { 1762 .enable_reg = 0x3300c, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(const struct clk_init_data) { 1765 .name = "gcc_pdm2_clk", 1766 .parent_hws = (const struct clk_hw*[]) { 1767 &gcc_pdm2_clk_src.clkr.hw, 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_pdm_ahb_clk = { 1777 .halt_reg = 0x33004, 1778 .halt_check = BRANCH_HALT_VOTED, 1779 .hwcg_reg = 0x33004, 1780 .hwcg_bit = 1, 1781 .clkr = { 1782 .enable_reg = 0x33004, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "gcc_pdm_ahb_clk", 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_pdm_xo4_clk = { 1792 .halt_reg = 0x33008, 1793 .halt_check = BRANCH_HALT, 1794 .clkr = { 1795 .enable_reg = 0x33008, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(const struct clk_init_data) { 1798 .name = "gcc_pdm_xo4_clk", 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 1805 .halt_reg = 0x26010, 1806 .halt_check = BRANCH_HALT_VOTED, 1807 .hwcg_reg = 0x26010, 1808 .hwcg_bit = 1, 1809 .clkr = { 1810 .enable_reg = 0x26010, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(const struct clk_init_data) { 1813 .name = "gcc_qmip_camera_cmd_ahb_clk", 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1820 .halt_reg = 0x26008, 1821 .halt_check = BRANCH_HALT_VOTED, 1822 .hwcg_reg = 0x26008, 1823 .hwcg_bit = 1, 1824 .clkr = { 1825 .enable_reg = 0x26008, 1826 .enable_mask = BIT(0), 1827 .hw.init = &(const struct clk_init_data) { 1828 .name = "gcc_qmip_camera_nrt_ahb_clk", 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832 }; 1833 1834 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1835 .halt_reg = 0x2600c, 1836 .halt_check = BRANCH_HALT_VOTED, 1837 .hwcg_reg = 0x2600c, 1838 .hwcg_bit = 1, 1839 .clkr = { 1840 .enable_reg = 0x2600c, 1841 .enable_mask = BIT(0), 1842 .hw.init = &(const struct clk_init_data) { 1843 .name = "gcc_qmip_camera_rt_ahb_clk", 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1850 .halt_reg = 0x71008, 1851 .halt_check = BRANCH_HALT_VOTED, 1852 .hwcg_reg = 0x71008, 1853 .hwcg_bit = 1, 1854 .clkr = { 1855 .enable_reg = 0x71008, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(const struct clk_init_data) { 1858 .name = "gcc_qmip_gpu_ahb_clk", 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1865 .halt_reg = 0x6b018, 1866 .halt_check = BRANCH_HALT_VOTED, 1867 .hwcg_reg = 0x6b018, 1868 .hwcg_bit = 1, 1869 .clkr = { 1870 .enable_reg = 0x52000, 1871 .enable_mask = BIT(11), 1872 .hw.init = &(const struct clk_init_data) { 1873 .name = "gcc_qmip_pcie_ahb_clk", 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1880 .halt_reg = 0x32010, 1881 .halt_check = BRANCH_HALT_VOTED, 1882 .hwcg_reg = 0x32010, 1883 .hwcg_bit = 1, 1884 .clkr = { 1885 .enable_reg = 0x32010, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(const struct clk_init_data) { 1888 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1895 .halt_reg = 0x3200c, 1896 .halt_check = BRANCH_HALT_VOTED, 1897 .hwcg_reg = 0x3200c, 1898 .hwcg_bit = 1, 1899 .clkr = { 1900 .enable_reg = 0x3200c, 1901 .enable_mask = BIT(0), 1902 .hw.init = &(const struct clk_init_data) { 1903 .name = "gcc_qmip_video_vcodec_ahb_clk", 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1910 .halt_reg = 0x2301c, 1911 .halt_check = BRANCH_HALT_VOTED, 1912 .clkr = { 1913 .enable_reg = 0x52008, 1914 .enable_mask = BIT(18), 1915 .hw.init = &(const struct clk_init_data) { 1916 .name = "gcc_qupv3_wrap1_core_2x_clk", 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1923 .halt_reg = 0x23008, 1924 .halt_check = BRANCH_HALT_VOTED, 1925 .clkr = { 1926 .enable_reg = 0x52008, 1927 .enable_mask = BIT(19), 1928 .hw.init = &(const struct clk_init_data) { 1929 .name = "gcc_qupv3_wrap1_core_clk", 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 1936 .halt_reg = 0x188bc, 1937 .halt_check = BRANCH_HALT_VOTED, 1938 .clkr = { 1939 .enable_reg = 0x52010, 1940 .enable_mask = BIT(29), 1941 .hw.init = &(const struct clk_init_data) { 1942 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 1943 .parent_hws = (const struct clk_hw*[]) { 1944 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1954 .halt_reg = 0x18004, 1955 .halt_check = BRANCH_HALT_VOTED, 1956 .clkr = { 1957 .enable_reg = 0x52008, 1958 .enable_mask = BIT(22), 1959 .hw.init = &(const struct clk_init_data) { 1960 .name = "gcc_qupv3_wrap1_s0_clk", 1961 .parent_hws = (const struct clk_hw*[]) { 1962 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1972 .halt_reg = 0x18140, 1973 .halt_check = BRANCH_HALT_VOTED, 1974 .clkr = { 1975 .enable_reg = 0x52008, 1976 .enable_mask = BIT(23), 1977 .hw.init = &(const struct clk_init_data) { 1978 .name = "gcc_qupv3_wrap1_s1_clk", 1979 .parent_hws = (const struct clk_hw*[]) { 1980 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1990 .halt_reg = 0x1827c, 1991 .halt_check = BRANCH_HALT_VOTED, 1992 .clkr = { 1993 .enable_reg = 0x52008, 1994 .enable_mask = BIT(24), 1995 .hw.init = &(const struct clk_init_data) { 1996 .name = "gcc_qupv3_wrap1_s2_clk", 1997 .parent_hws = (const struct clk_hw*[]) { 1998 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2008 .halt_reg = 0x18290, 2009 .halt_check = BRANCH_HALT_VOTED, 2010 .clkr = { 2011 .enable_reg = 0x52008, 2012 .enable_mask = BIT(25), 2013 .hw.init = &(const struct clk_init_data) { 2014 .name = "gcc_qupv3_wrap1_s3_clk", 2015 .parent_hws = (const struct clk_hw*[]) { 2016 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2026 .halt_reg = 0x183cc, 2027 .halt_check = BRANCH_HALT_VOTED, 2028 .clkr = { 2029 .enable_reg = 0x52008, 2030 .enable_mask = BIT(26), 2031 .hw.init = &(const struct clk_init_data) { 2032 .name = "gcc_qupv3_wrap1_s4_clk", 2033 .parent_hws = (const struct clk_hw*[]) { 2034 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2035 }, 2036 .num_parents = 1, 2037 .flags = CLK_SET_RATE_PARENT, 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2044 .halt_reg = 0x18508, 2045 .halt_check = BRANCH_HALT_VOTED, 2046 .clkr = { 2047 .enable_reg = 0x52008, 2048 .enable_mask = BIT(27), 2049 .hw.init = &(const struct clk_init_data) { 2050 .name = "gcc_qupv3_wrap1_s5_clk", 2051 .parent_hws = (const struct clk_hw*[]) { 2052 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2062 .halt_reg = 0x18644, 2063 .halt_check = BRANCH_HALT_VOTED, 2064 .clkr = { 2065 .enable_reg = 0x52008, 2066 .enable_mask = BIT(28), 2067 .hw.init = &(const struct clk_init_data) { 2068 .name = "gcc_qupv3_wrap1_s6_clk", 2069 .parent_hws = (const struct clk_hw*[]) { 2070 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2071 }, 2072 .num_parents = 1, 2073 .flags = CLK_SET_RATE_PARENT, 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2080 .halt_reg = 0x18780, 2081 .halt_check = BRANCH_HALT_VOTED, 2082 .clkr = { 2083 .enable_reg = 0x52010, 2084 .enable_mask = BIT(16), 2085 .hw.init = &(const struct clk_init_data) { 2086 .name = "gcc_qupv3_wrap1_s7_clk", 2087 .parent_hws = (const struct clk_hw*[]) { 2088 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2089 }, 2090 .num_parents = 1, 2091 .flags = CLK_SET_RATE_PARENT, 2092 .ops = &clk_branch2_ops, 2093 }, 2094 }, 2095 }; 2096 2097 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2098 .halt_reg = 0x23174, 2099 .halt_check = BRANCH_HALT_VOTED, 2100 .clkr = { 2101 .enable_reg = 0x52010, 2102 .enable_mask = BIT(3), 2103 .hw.init = &(const struct clk_init_data) { 2104 .name = "gcc_qupv3_wrap2_core_2x_clk", 2105 .ops = &clk_branch2_ops, 2106 }, 2107 }, 2108 }; 2109 2110 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2111 .halt_reg = 0x23160, 2112 .halt_check = BRANCH_HALT_VOTED, 2113 .clkr = { 2114 .enable_reg = 0x52010, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(const struct clk_init_data) { 2117 .name = "gcc_qupv3_wrap2_core_clk", 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2124 .halt_reg = 0x1e004, 2125 .halt_check = BRANCH_HALT_VOTED, 2126 .clkr = { 2127 .enable_reg = 0x52010, 2128 .enable_mask = BIT(4), 2129 .hw.init = &(const struct clk_init_data) { 2130 .name = "gcc_qupv3_wrap2_s0_clk", 2131 .parent_hws = (const struct clk_hw*[]) { 2132 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2133 }, 2134 .num_parents = 1, 2135 .flags = CLK_SET_RATE_PARENT, 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2142 .halt_reg = 0x1e140, 2143 .halt_check = BRANCH_HALT_VOTED, 2144 .clkr = { 2145 .enable_reg = 0x52010, 2146 .enable_mask = BIT(5), 2147 .hw.init = &(const struct clk_init_data) { 2148 .name = "gcc_qupv3_wrap2_s1_clk", 2149 .parent_hws = (const struct clk_hw*[]) { 2150 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2151 }, 2152 .num_parents = 1, 2153 .flags = CLK_SET_RATE_PARENT, 2154 .ops = &clk_branch2_ops, 2155 }, 2156 }, 2157 }; 2158 2159 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2160 .halt_reg = 0x1e27c, 2161 .halt_check = BRANCH_HALT_VOTED, 2162 .clkr = { 2163 .enable_reg = 0x52010, 2164 .enable_mask = BIT(6), 2165 .hw.init = &(const struct clk_init_data) { 2166 .name = "gcc_qupv3_wrap2_s2_clk", 2167 .parent_hws = (const struct clk_hw*[]) { 2168 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2178 .halt_reg = 0x1e3b8, 2179 .halt_check = BRANCH_HALT_VOTED, 2180 .clkr = { 2181 .enable_reg = 0x52010, 2182 .enable_mask = BIT(7), 2183 .hw.init = &(const struct clk_init_data) { 2184 .name = "gcc_qupv3_wrap2_s3_clk", 2185 .parent_hws = (const struct clk_hw*[]) { 2186 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2187 }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT, 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2196 .halt_reg = 0x1e4f4, 2197 .halt_check = BRANCH_HALT_VOTED, 2198 .clkr = { 2199 .enable_reg = 0x52010, 2200 .enable_mask = BIT(8), 2201 .hw.init = &(const struct clk_init_data) { 2202 .name = "gcc_qupv3_wrap2_s4_clk", 2203 .parent_hws = (const struct clk_hw*[]) { 2204 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2205 }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2214 .halt_reg = 0x1e630, 2215 .halt_check = BRANCH_HALT_VOTED, 2216 .clkr = { 2217 .enable_reg = 0x52010, 2218 .enable_mask = BIT(9), 2219 .hw.init = &(const struct clk_init_data) { 2220 .name = "gcc_qupv3_wrap2_s5_clk", 2221 .parent_hws = (const struct clk_hw*[]) { 2222 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2223 }, 2224 .num_parents = 1, 2225 .flags = CLK_SET_RATE_PARENT, 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2232 .halt_reg = 0x1e76c, 2233 .halt_check = BRANCH_HALT_VOTED, 2234 .clkr = { 2235 .enable_reg = 0x52010, 2236 .enable_mask = BIT(10), 2237 .hw.init = &(const struct clk_init_data) { 2238 .name = "gcc_qupv3_wrap2_s6_clk", 2239 .parent_hws = (const struct clk_hw*[]) { 2240 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2241 }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2250 .halt_reg = 0x1e8a8, 2251 .halt_check = BRANCH_HALT_VOTED, 2252 .clkr = { 2253 .enable_reg = 0x52010, 2254 .enable_mask = BIT(17), 2255 .hw.init = &(const struct clk_init_data) { 2256 .name = "gcc_qupv3_wrap2_s7_clk", 2257 .parent_hws = (const struct clk_hw*[]) { 2258 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2259 }, 2260 .num_parents = 1, 2261 .flags = CLK_SET_RATE_PARENT, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2268 .halt_reg = 0x23000, 2269 .halt_check = BRANCH_HALT_VOTED, 2270 .clkr = { 2271 .enable_reg = 0x52008, 2272 .enable_mask = BIT(20), 2273 .hw.init = &(const struct clk_init_data) { 2274 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2275 .ops = &clk_branch2_ops, 2276 }, 2277 }, 2278 }; 2279 2280 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2281 .halt_reg = 0x23004, 2282 .halt_check = BRANCH_HALT_VOTED, 2283 .hwcg_reg = 0x23004, 2284 .hwcg_bit = 1, 2285 .clkr = { 2286 .enable_reg = 0x52008, 2287 .enable_mask = BIT(21), 2288 .hw.init = &(const struct clk_init_data) { 2289 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2290 .ops = &clk_branch2_ops, 2291 }, 2292 }, 2293 }; 2294 2295 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2296 .halt_reg = 0x23158, 2297 .halt_check = BRANCH_HALT_VOTED, 2298 .hwcg_reg = 0x23158, 2299 .hwcg_bit = 1, 2300 .clkr = { 2301 .enable_reg = 0x52010, 2302 .enable_mask = BIT(2), 2303 .hw.init = &(const struct clk_init_data) { 2304 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2305 .ops = &clk_branch2_ops, 2306 }, 2307 }, 2308 }; 2309 2310 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2311 .halt_reg = 0x2315c, 2312 .halt_check = BRANCH_HALT_VOTED, 2313 .hwcg_reg = 0x2315c, 2314 .hwcg_bit = 1, 2315 .clkr = { 2316 .enable_reg = 0x52010, 2317 .enable_mask = BIT(1), 2318 .hw.init = &(const struct clk_init_data) { 2319 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gcc_sdcc1_ahb_clk = { 2326 .halt_reg = 0xa9004, 2327 .halt_check = BRANCH_HALT, 2328 .clkr = { 2329 .enable_reg = 0xa9004, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(const struct clk_init_data) { 2332 .name = "gcc_sdcc1_ahb_clk", 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_sdcc1_apps_clk = { 2339 .halt_reg = 0xa9008, 2340 .halt_check = BRANCH_HALT, 2341 .clkr = { 2342 .enable_reg = 0xa9008, 2343 .enable_mask = BIT(0), 2344 .hw.init = &(const struct clk_init_data) { 2345 .name = "gcc_sdcc1_apps_clk", 2346 .parent_hws = (const struct clk_hw*[]) { 2347 &gcc_sdcc1_apps_clk_src.clkr.hw, 2348 }, 2349 .num_parents = 1, 2350 .flags = CLK_SET_RATE_PARENT, 2351 .ops = &clk_branch2_ops, 2352 }, 2353 }, 2354 }; 2355 2356 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2357 .halt_reg = 0xa9030, 2358 .halt_check = BRANCH_HALT_VOTED, 2359 .hwcg_reg = 0xa9030, 2360 .hwcg_bit = 1, 2361 .clkr = { 2362 .enable_reg = 0xa9030, 2363 .enable_mask = BIT(0), 2364 .hw.init = &(const struct clk_init_data) { 2365 .name = "gcc_sdcc1_ice_core_clk", 2366 .parent_hws = (const struct clk_hw*[]) { 2367 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2368 }, 2369 .num_parents = 1, 2370 .flags = CLK_SET_RATE_PARENT, 2371 .ops = &clk_branch2_ops, 2372 }, 2373 }, 2374 }; 2375 2376 static struct clk_branch gcc_sdcc2_ahb_clk = { 2377 .halt_reg = 0x14014, 2378 .halt_check = BRANCH_HALT, 2379 .clkr = { 2380 .enable_reg = 0x14014, 2381 .enable_mask = BIT(0), 2382 .hw.init = &(const struct clk_init_data) { 2383 .name = "gcc_sdcc2_ahb_clk", 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch gcc_sdcc2_apps_clk = { 2390 .halt_reg = 0x14004, 2391 .halt_check = BRANCH_HALT, 2392 .clkr = { 2393 .enable_reg = 0x14004, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(const struct clk_init_data) { 2396 .name = "gcc_sdcc2_apps_clk", 2397 .parent_hws = (const struct clk_hw*[]) { 2398 &gcc_sdcc2_apps_clk_src.clkr.hw, 2399 }, 2400 .num_parents = 1, 2401 .flags = CLK_SET_RATE_PARENT, 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2408 .halt_reg = 0x77028, 2409 .halt_check = BRANCH_HALT_VOTED, 2410 .hwcg_reg = 0x77028, 2411 .hwcg_bit = 1, 2412 .clkr = { 2413 .enable_reg = 0x77028, 2414 .enable_mask = BIT(0), 2415 .hw.init = &(const struct clk_init_data) { 2416 .name = "gcc_ufs_phy_ahb_clk", 2417 .ops = &clk_branch2_ops, 2418 }, 2419 }, 2420 }; 2421 2422 static struct clk_branch gcc_ufs_phy_axi_clk = { 2423 .halt_reg = 0x77018, 2424 .halt_check = BRANCH_HALT_VOTED, 2425 .hwcg_reg = 0x77018, 2426 .hwcg_bit = 1, 2427 .clkr = { 2428 .enable_reg = 0x77018, 2429 .enable_mask = BIT(0), 2430 .hw.init = &(const struct clk_init_data) { 2431 .name = "gcc_ufs_phy_axi_clk", 2432 .parent_hws = (const struct clk_hw*[]) { 2433 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2434 }, 2435 .num_parents = 1, 2436 .flags = CLK_SET_RATE_PARENT, 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440 }; 2441 2442 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2443 .halt_reg = 0x7707c, 2444 .halt_check = BRANCH_HALT_VOTED, 2445 .hwcg_reg = 0x7707c, 2446 .hwcg_bit = 1, 2447 .clkr = { 2448 .enable_reg = 0x7707c, 2449 .enable_mask = BIT(0), 2450 .hw.init = &(const struct clk_init_data) { 2451 .name = "gcc_ufs_phy_ice_core_clk", 2452 .parent_hws = (const struct clk_hw*[]) { 2453 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2454 }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2463 .halt_reg = 0x770bc, 2464 .halt_check = BRANCH_HALT_VOTED, 2465 .hwcg_reg = 0x770bc, 2466 .hwcg_bit = 1, 2467 .clkr = { 2468 .enable_reg = 0x770bc, 2469 .enable_mask = BIT(0), 2470 .hw.init = &(const struct clk_init_data) { 2471 .name = "gcc_ufs_phy_phy_aux_clk", 2472 .parent_hws = (const struct clk_hw*[]) { 2473 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2474 }, 2475 .num_parents = 1, 2476 .flags = CLK_SET_RATE_PARENT, 2477 .ops = &clk_branch2_ops, 2478 }, 2479 }, 2480 }; 2481 2482 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2483 .halt_reg = 0x77030, 2484 .halt_check = BRANCH_HALT_DELAY, 2485 .clkr = { 2486 .enable_reg = 0x77030, 2487 .enable_mask = BIT(0), 2488 .hw.init = &(const struct clk_init_data) { 2489 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2490 .parent_hws = (const struct clk_hw*[]) { 2491 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2492 }, 2493 .num_parents = 1, 2494 .flags = CLK_SET_RATE_PARENT, 2495 .ops = &clk_branch2_ops, 2496 }, 2497 }, 2498 }; 2499 2500 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2501 .halt_reg = 0x770d8, 2502 .halt_check = BRANCH_HALT_DELAY, 2503 .clkr = { 2504 .enable_reg = 0x770d8, 2505 .enable_mask = BIT(0), 2506 .hw.init = &(const struct clk_init_data) { 2507 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2508 .parent_hws = (const struct clk_hw*[]) { 2509 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2510 }, 2511 .num_parents = 1, 2512 .flags = CLK_SET_RATE_PARENT, 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2519 .halt_reg = 0x7702c, 2520 .halt_check = BRANCH_HALT_DELAY, 2521 .clkr = { 2522 .enable_reg = 0x7702c, 2523 .enable_mask = BIT(0), 2524 .hw.init = &(const struct clk_init_data) { 2525 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2526 .parent_hws = (const struct clk_hw*[]) { 2527 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2528 }, 2529 .num_parents = 1, 2530 .flags = CLK_SET_RATE_PARENT, 2531 .ops = &clk_branch2_ops, 2532 }, 2533 }, 2534 }; 2535 2536 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2537 .halt_reg = 0x7706c, 2538 .halt_check = BRANCH_HALT_VOTED, 2539 .hwcg_reg = 0x7706c, 2540 .hwcg_bit = 1, 2541 .clkr = { 2542 .enable_reg = 0x7706c, 2543 .enable_mask = BIT(0), 2544 .hw.init = &(const struct clk_init_data) { 2545 .name = "gcc_ufs_phy_unipro_core_clk", 2546 .parent_hws = (const struct clk_hw*[]) { 2547 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2548 }, 2549 .num_parents = 1, 2550 .flags = CLK_SET_RATE_PARENT, 2551 .ops = &clk_branch2_ops, 2552 }, 2553 }, 2554 }; 2555 2556 static struct clk_branch gcc_usb30_prim_atb_clk = { 2557 .halt_reg = 0x3908c, 2558 .halt_check = BRANCH_HALT_VOTED, 2559 .clkr = { 2560 .enable_reg = 0x3908c, 2561 .enable_mask = BIT(0), 2562 .hw.init = &(const struct clk_init_data) { 2563 .name = "gcc_usb30_prim_atb_clk", 2564 .parent_hws = (const struct clk_hw*[]) { 2565 &gcc_usb30_prim_master_clk_src.clkr.hw, 2566 }, 2567 .num_parents = 1, 2568 .flags = CLK_SET_RATE_PARENT, 2569 .ops = &clk_branch2_ops, 2570 }, 2571 }, 2572 }; 2573 2574 static struct clk_branch gcc_usb30_prim_master_clk = { 2575 .halt_reg = 0x39018, 2576 .halt_check = BRANCH_HALT, 2577 .clkr = { 2578 .enable_reg = 0x39018, 2579 .enable_mask = BIT(0), 2580 .hw.init = &(const struct clk_init_data) { 2581 .name = "gcc_usb30_prim_master_clk", 2582 .parent_hws = (const struct clk_hw*[]) { 2583 &gcc_usb30_prim_master_clk_src.clkr.hw, 2584 }, 2585 .num_parents = 1, 2586 .flags = CLK_SET_RATE_PARENT, 2587 .ops = &clk_branch2_ops, 2588 }, 2589 }, 2590 }; 2591 2592 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2593 .halt_reg = 0x3902c, 2594 .halt_check = BRANCH_HALT, 2595 .clkr = { 2596 .enable_reg = 0x3902c, 2597 .enable_mask = BIT(0), 2598 .hw.init = &(const struct clk_init_data) { 2599 .name = "gcc_usb30_prim_mock_utmi_clk", 2600 .parent_hws = (const struct clk_hw*[]) { 2601 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2602 }, 2603 .num_parents = 1, 2604 .flags = CLK_SET_RATE_PARENT, 2605 .ops = &clk_branch2_ops, 2606 }, 2607 }, 2608 }; 2609 2610 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2611 .halt_reg = 0x39028, 2612 .halt_check = BRANCH_HALT, 2613 .clkr = { 2614 .enable_reg = 0x39028, 2615 .enable_mask = BIT(0), 2616 .hw.init = &(const struct clk_init_data) { 2617 .name = "gcc_usb30_prim_sleep_clk", 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2624 .halt_reg = 0x39064, 2625 .halt_check = BRANCH_HALT, 2626 .clkr = { 2627 .enable_reg = 0x39064, 2628 .enable_mask = BIT(0), 2629 .hw.init = &(const struct clk_init_data) { 2630 .name = "gcc_usb3_prim_phy_aux_clk", 2631 .parent_hws = (const struct clk_hw*[]) { 2632 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2633 }, 2634 .num_parents = 1, 2635 .flags = CLK_SET_RATE_PARENT, 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639 }; 2640 2641 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2642 .halt_reg = 0x39068, 2643 .halt_check = BRANCH_HALT, 2644 .clkr = { 2645 .enable_reg = 0x39068, 2646 .enable_mask = BIT(0), 2647 .hw.init = &(const struct clk_init_data) { 2648 .name = "gcc_usb3_prim_phy_com_aux_clk", 2649 .parent_hws = (const struct clk_hw*[]) { 2650 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2651 }, 2652 .num_parents = 1, 2653 .flags = CLK_SET_RATE_PARENT, 2654 .ops = &clk_branch2_ops, 2655 }, 2656 }, 2657 }; 2658 2659 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2660 .halt_reg = 0x3906c, 2661 .halt_check = BRANCH_HALT_DELAY, 2662 .hwcg_reg = 0x3906c, 2663 .hwcg_bit = 1, 2664 .clkr = { 2665 .enable_reg = 0x3906c, 2666 .enable_mask = BIT(0), 2667 .hw.init = &(const struct clk_init_data) { 2668 .name = "gcc_usb3_prim_phy_pipe_clk", 2669 .parent_hws = (const struct clk_hw*[]) { 2670 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2671 }, 2672 .num_parents = 1, 2673 .flags = CLK_SET_RATE_PARENT, 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677 }; 2678 2679 static struct clk_branch gcc_video_axi0_clk = { 2680 .halt_reg = 0x32018, 2681 .halt_check = BRANCH_HALT_SKIP, 2682 .hwcg_reg = 0x32018, 2683 .hwcg_bit = 1, 2684 .clkr = { 2685 .enable_reg = 0x32018, 2686 .enable_mask = BIT(0), 2687 .hw.init = &(const struct clk_init_data) { 2688 .name = "gcc_video_axi0_clk", 2689 .ops = &clk_branch2_ops, 2690 }, 2691 }, 2692 }; 2693 2694 static struct clk_branch gcc_video_axi1_clk = { 2695 .halt_reg = 0x32028, 2696 .halt_check = BRANCH_HALT_SKIP, 2697 .hwcg_reg = 0x32028, 2698 .hwcg_bit = 1, 2699 .clkr = { 2700 .enable_reg = 0x32028, 2701 .enable_mask = BIT(0), 2702 .hw.init = &(const struct clk_init_data) { 2703 .name = "gcc_video_axi1_clk", 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707 }; 2708 2709 static struct gdsc gcc_pcie_0_gdsc = { 2710 .gdscr = 0x6b004, 2711 .en_rest_wait_val = 0x2, 2712 .en_few_wait_val = 0x2, 2713 .clk_dis_wait_val = 0xf, 2714 .collapse_ctrl = 0x5214c, 2715 .collapse_mask = BIT(0), 2716 .pd = { 2717 .name = "gcc_pcie_0_gdsc", 2718 }, 2719 .pwrsts = PWRSTS_OFF_ON, 2720 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2721 }; 2722 2723 static struct gdsc gcc_pcie_0_phy_gdsc = { 2724 .gdscr = 0x6c000, 2725 .en_rest_wait_val = 0x2, 2726 .en_few_wait_val = 0x2, 2727 .clk_dis_wait_val = 0x2, 2728 .collapse_ctrl = 0x5214c, 2729 .collapse_mask = BIT(2), 2730 .pd = { 2731 .name = "gcc_pcie_0_phy_gdsc", 2732 }, 2733 .pwrsts = PWRSTS_OFF_ON, 2734 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2735 }; 2736 2737 static struct gdsc gcc_pcie_1_gdsc = { 2738 .gdscr = 0xac004, 2739 .en_rest_wait_val = 0x2, 2740 .en_few_wait_val = 0x2, 2741 .clk_dis_wait_val = 0xf, 2742 .collapse_ctrl = 0x5214c, 2743 .collapse_mask = BIT(3), 2744 .pd = { 2745 .name = "gcc_pcie_1_gdsc", 2746 }, 2747 .pwrsts = PWRSTS_OFF_ON, 2748 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2749 }; 2750 2751 static struct gdsc gcc_pcie_1_phy_gdsc = { 2752 .gdscr = 0xad000, 2753 .en_rest_wait_val = 0x2, 2754 .en_few_wait_val = 0x2, 2755 .clk_dis_wait_val = 0x2, 2756 .collapse_ctrl = 0x5214c, 2757 .collapse_mask = BIT(4), 2758 .pd = { 2759 .name = "gcc_pcie_1_phy_gdsc", 2760 }, 2761 .pwrsts = PWRSTS_OFF_ON, 2762 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2763 }; 2764 2765 static struct gdsc gcc_ufs_mem_phy_gdsc = { 2766 .gdscr = 0x9e000, 2767 .en_rest_wait_val = 0x2, 2768 .en_few_wait_val = 0x2, 2769 .clk_dis_wait_val = 0x2, 2770 .pd = { 2771 .name = "gcc_ufs_mem_phy_gdsc", 2772 }, 2773 .pwrsts = PWRSTS_OFF_ON, 2774 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2775 }; 2776 2777 static struct gdsc gcc_ufs_phy_gdsc = { 2778 .gdscr = 0x77004, 2779 .en_rest_wait_val = 0x2, 2780 .en_few_wait_val = 0x2, 2781 .clk_dis_wait_val = 0xf, 2782 .pd = { 2783 .name = "gcc_ufs_phy_gdsc", 2784 }, 2785 .pwrsts = PWRSTS_OFF_ON, 2786 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2787 }; 2788 2789 static struct gdsc gcc_usb30_prim_gdsc = { 2790 .gdscr = 0x39004, 2791 .en_rest_wait_val = 0x2, 2792 .en_few_wait_val = 0x2, 2793 .clk_dis_wait_val = 0xf, 2794 .pd = { 2795 .name = "gcc_usb30_prim_gdsc", 2796 }, 2797 .pwrsts = PWRSTS_OFF_ON, 2798 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2799 }; 2800 2801 static struct gdsc gcc_usb3_phy_gdsc = { 2802 .gdscr = 0x50018, 2803 .en_rest_wait_val = 0x2, 2804 .en_few_wait_val = 0x2, 2805 .clk_dis_wait_val = 0x2, 2806 .pd = { 2807 .name = "gcc_usb3_phy_gdsc", 2808 }, 2809 .pwrsts = PWRSTS_OFF_ON, 2810 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2811 }; 2812 2813 static struct clk_regmap *gcc_eliza_clocks[] = { 2814 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 2815 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2816 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2817 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2818 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2819 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2820 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2821 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2822 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 2823 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2824 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 2825 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2826 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2827 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2828 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2829 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2830 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2831 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2832 [GCC_GPLL0] = &gcc_gpll0.clkr, 2833 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2834 [GCC_GPLL4] = &gcc_gpll4.clkr, 2835 [GCC_GPLL7] = &gcc_gpll7.clkr, 2836 [GCC_GPLL8] = &gcc_gpll8.clkr, 2837 [GCC_GPLL9] = &gcc_gpll9.clkr, 2838 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 2839 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr, 2840 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr, 2841 [GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr, 2842 [GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr, 2843 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2844 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2845 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2846 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2847 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2848 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2849 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2850 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2851 [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr, 2852 [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr, 2853 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2854 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2855 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2856 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 2857 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2858 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2859 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 2860 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 2861 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2862 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 2863 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, 2864 [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr, 2865 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2866 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 2867 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2868 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2869 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2870 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2871 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 2872 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2873 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2874 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 2875 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 2876 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 2877 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2878 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2879 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2880 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 2881 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 2882 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2883 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2884 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2885 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2886 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2887 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2888 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2889 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2890 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2891 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2892 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2893 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2894 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2895 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2896 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2897 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2898 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 2899 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 2900 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 2901 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 2902 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 2903 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 2904 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 2905 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 2906 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 2907 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 2908 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 2909 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 2910 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 2911 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 2912 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 2913 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 2914 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 2915 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 2916 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2917 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2918 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 2919 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 2920 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2921 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2922 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2923 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2924 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2925 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2926 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2927 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2928 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2929 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2930 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2931 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2932 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2933 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2934 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2935 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2936 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 2937 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 2938 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 2939 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2940 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 2941 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2942 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 2943 [GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr, 2944 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2945 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2946 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2947 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2948 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2949 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2950 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2951 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2952 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2953 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2954 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2955 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2956 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 2957 }; 2958 2959 static struct gdsc *gcc_eliza_gdscs[] = { 2960 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 2961 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 2962 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 2963 [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc, 2964 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 2965 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 2966 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2967 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 2968 }; 2969 2970 static const struct qcom_reset_map gcc_eliza_resets[] = { 2971 [GCC_CAMERA_BCR] = { 0x26000 }, 2972 [GCC_DISPLAY_BCR] = { 0x27000 }, 2973 [GCC_GPU_BCR] = { 0x71000 }, 2974 [GCC_PCIE_0_BCR] = { 0x6b000 }, 2975 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 2976 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 2977 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 2978 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 2979 [GCC_PCIE_1_BCR] = { 0xac000 }, 2980 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 2981 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 2982 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 2983 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 2984 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 2985 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 2986 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 2987 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 2988 [GCC_PDM_BCR] = { 0x33000 }, 2989 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 2990 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 2991 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 2992 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 2993 [GCC_SDCC1_BCR] = { 0xa9000 }, 2994 [GCC_SDCC2_BCR] = { 0x14000 }, 2995 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2996 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 2997 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 2998 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 2999 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3000 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3001 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3002 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3003 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3004 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 }, 3005 [GCC_VIDEO_BCR] = { 0x32000 }, 3006 }; 3007 3008 static const u32 gcc_eliza_critical_cbcrs[] = { 3009 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3010 0x26004, /* GCC_CAMERA_AHB_CLK */ 3011 0x26034, /* GCC_CAMERA_XO_CLK */ 3012 0x27004, /* GCC_DISP_AHB_CLK */ 3013 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3014 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ 3015 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 3016 0x32004, /* GCC_VIDEO_AHB_CLK */ 3017 0x32038, /* GCC_VIDEO_XO_CLK */ 3018 }; 3019 3020 static const struct clk_rcg_dfs_data gcc_eliza_dfs_clocks[] = { 3021 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3022 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3023 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3024 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3025 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3026 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3027 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3028 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3029 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3030 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3031 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3032 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3033 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3034 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3035 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3036 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3037 }; 3038 3039 static const struct regmap_config gcc_eliza_regmap_config = { 3040 .reg_bits = 32, 3041 .reg_stride = 4, 3042 .val_bits = 32, 3043 .max_register = 0x1f41f0, 3044 .fast_io = true, 3045 }; 3046 3047 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap) 3048 { 3049 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ 3050 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3051 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); 3052 } 3053 3054 static const struct qcom_cc_driver_data gcc_eliza_driver_data = { 3055 .clk_cbcrs = gcc_eliza_critical_cbcrs, 3056 .num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs), 3057 .dfs_rcgs = gcc_eliza_dfs_clocks, 3058 .num_dfs_rcgs = ARRAY_SIZE(gcc_eliza_dfs_clocks), 3059 .clk_regs_configure = clk_eliza_regs_configure, 3060 }; 3061 3062 static const struct qcom_cc_desc gcc_eliza_desc = { 3063 .config = &gcc_eliza_regmap_config, 3064 .clks = gcc_eliza_clocks, 3065 .num_clks = ARRAY_SIZE(gcc_eliza_clocks), 3066 .resets = gcc_eliza_resets, 3067 .num_resets = ARRAY_SIZE(gcc_eliza_resets), 3068 .gdscs = gcc_eliza_gdscs, 3069 .num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs), 3070 .driver_data = &gcc_eliza_driver_data, 3071 }; 3072 3073 static const struct of_device_id gcc_eliza_match_table[] = { 3074 { .compatible = "qcom,eliza-gcc" }, 3075 { } 3076 }; 3077 MODULE_DEVICE_TABLE(of, gcc_eliza_match_table); 3078 3079 static int gcc_eliza_probe(struct platform_device *pdev) 3080 { 3081 return qcom_cc_probe(pdev, &gcc_eliza_desc); 3082 } 3083 3084 static struct platform_driver gcc_eliza_driver = { 3085 .probe = gcc_eliza_probe, 3086 .driver = { 3087 .name = "gcc-eliza", 3088 .of_match_table = gcc_eliza_match_table, 3089 }, 3090 }; 3091 3092 static int __init gcc_eliza_init(void) 3093 { 3094 return platform_driver_register(&gcc_eliza_driver); 3095 } 3096 subsys_initcall(gcc_eliza_init); 3097 3098 static void __exit gcc_eliza_exit(void) 3099 { 3100 platform_driver_unregister(&gcc_eliza_driver); 3101 } 3102 module_exit(gcc_eliza_exit); 3103 3104 MODULE_DESCRIPTION("QTI GCC Eliza Driver"); 3105 MODULE_LICENSE("GPL"); 3106