Home
last modified time | relevance | path

Searched refs:g5 (Results 1 – 25 of 94) sorted by relevance

1234

/illumos-gate/usr/src/uts/sfmmu/ml/
H A Dsfmmu_kdi.S70 set KHATID, %g5; \
71 ldx [%g5], %g5; \
72 cmp %g2, %g5; \
77 set UHMEHASH_SZ, %g5; \
78 ld [%g5], %g5; \
79 and %g4, %g5, %g4; \
81 set uhme_hash_pa, %g5; \
82 ldx [%g5], %g5; \
84 add %g4, %g5, %g4; \
87 set KHMEHASH_SZ, %g5; \
[all …]
H A Dsfmmu_asm.S619 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
642 cmp %g5, %o4
670 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
686 cmp %g5, %o4
1308 MAKE_JMP_INSTR(5, %o1, %o2) ! jmp %g5
1578 USE_ALTERNATE_GLOBALS(%g5)
1579 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g6, %g4)
1587 mov %g5, %g2
1619 USE_ALTERNATE_GLOBALS(%g5)
1620 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g6)
[all …]
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dmach_interrupt.S53 ! %g5 PC for fasttrap TL>0 handler
484 ldxa [%g7]ASI_MEM, %g5 ! %g5 = first 8 byte of ER buf
485 cmp 0, %g5
490 set 0, %g5
491 ldxa [%g4 + %g5]ASI_MEM, %g1
492 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 0 - 7
493 add %g5, 8, %g5
494 ldxa [%g4 + %g5]ASI_MEM, %g1
495 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 8 - 15
496 add %g5, 8, %g5
[all …]
H A Dwbuf.S60 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
61 ! sfar (g5 == T_ALIGNMENT)
77 cmp %g5, T_ALIGNMENT
88 rdpr %tstate, %g5
89 and %g5, TSTATE_CWP, %g5
91 wrpr %g0, %g5, %cwp
157 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
158 CPU_PADDR(%g5, %g6)
163 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
164 lda [%g6 + MPCB_WBCNT]%asi, %g5
[all …]
H A Dtrap_table.S485 add %sp, 32, %g5 ;\
486 stxa %l4, [%g5 + %g1]asi_num ;\
487 stxa %l5, [%g5 + %g2]asi_num ;\
488 stxa %l6, [%g5 + %g3]asi_num ;\
489 stxa %l7, [%g5 + %g4]asi_num ;\
490 add %g5, 32, %g5 ;\
491 stxa %i0, [%g5 + %g1]asi_num ;\
492 stxa %i1, [%g5 + %g2]asi_num ;\
493 stxa %i2, [%g5 + %g3]asi_num ;\
494 stxa %i3, [%g5 + %g4]asi_num ;\
[all …]
/illumos-gate/usr/src/uts/sun4u/ml/
H A Dwbuf.S59 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
60 ! sfar (g5 == T_ALIGNMENT)
76 cmp %g5, T_ALIGNMENT
87 rdpr %tstate, %g5
88 and %g5, TSTATE_CWP, %g5
90 wrpr %g0, %g5, %cwp
155 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
156 CPU_ADDR(%g5, %g6)
160 ldn [%g5 + CPU_MPCB], %g6
161 ld [%g6 + MPCB_WBCNT], %g5
[all …]
H A Dtrap_table.S542 add %sp, 32, %g5 ;\
543 stxa %l4, [%g5 + %g1]asi_num ;\
544 stxa %l5, [%g5 + %g2]asi_num ;\
545 stxa %l6, [%g5 + %g3]asi_num ;\
546 stxa %l7, [%g5 + %g4]asi_num ;\
547 add %g5, 32, %g5 ;\
548 stxa %i0, [%g5 + %g1]asi_num ;\
549 stxa %i1, [%g5 + %g2]asi_num ;\
550 stxa %i2, [%g5 + %g3]asi_num ;\
551 stxa %i3, [%g5 + %g4]asi_num ;\
[all …]
H A Dmach_interrupt.S55 ldxa [%g2]ASI_INTR_RECEIVE, %g5 ! %g5 = PC or Interrupt Number
59 brlz,pt %g5, dmv_vector
65 cmp %g5, %g4
72 cmp %g5, %g4
106 ! g5: TL>0 handler
129 stna %g5, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
142 1: jmp %g5 ! call the fast trap handler
145 jmp %g5
154 ! %g5 - inum
255 mov %g1, %g5
[all …]
/illumos-gate/usr/src/common/crypto/arcfour/sun4u/
H A Darcfour_crypt_asm.S105 add %g3, %g4, %g5
107 and %g5, 255, %g5
119 ldub [%i5 + %g5], %g5
124 sllx %g5, 48, %g5
128 or %o0, %g5, %o0
144 add %g3, %g4, %g5
146 and %g5, 255, %g5
159 ldub [%i5 + %g5], %g5
164 sllx %g5, 32, %g5
168 or %o0, %g5, %o0
[all …]
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus_asm.S176 add %g1, CH_ERR_TL1_LOGOUT, %g5
177 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
192 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
193 stxa %g5, [%g0]ASI_ESTATE_ERR
201 PN_L2_FLUSHALL(%g3, %g4, %g5)
204 set CH_ECACHE_MIN_LSIZE, %g5
213 CHP_ECACHE_FLUSHALL(%g4, %g5, %g3)
233 ASM_LD(%g5, dcache_linesize)
234 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
260 mov CH_ICACHE_LSIZE, %g5
[all …]
H A Dus3_cheetah_asm.S105 add %g1, CH_ERR_TL1_LOGOUT, %g5
106 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
121 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
122 stxa %g5, [%g0]ASI_ESTATE_ERR
131 set CH_ECACHE_MIN_LSIZE, %g5
141 CH_ECACHE_FLUSHALL(%g4, %g5, %g6)
161 ASM_LD(%g5, dcache_linesize)
162 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
184 ASM_LD(%g5, icache_linesize)
185 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
[all …]
H A Dus3_jalapeno_asm.S391 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
398 CPU_INDEX(%g4, %g5)
400 set cpunodes, %g5
401 add %g4, %g5, %g4
402 ld [%g4 + ECACHE_LINESIZE], %g5
412 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
426 ASM_LD(%g5, dcache_size)
428 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
435 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4);
436 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
[all …]
H A Dus3_common_asm.S290 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
291 srlx %g5, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
297 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
333 sethi %hi(FLUSH_ADDR), %g5
337 flush %g5 ! flush required by immu
350 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
356 or %g5, %g4, %g5
362 or %g5, %g2, %g5 /* %g5 = nucleus pgsz | primary pgsz | cnum */
363 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
366 sethi %hi(FLUSH_ADDR), %g5
[all …]
H A Dspitfire_asm.S467 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
472 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
502 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
507 stxa %g5, [%g4]ASI_DMMU /* write new ctxum */
510 sethi %hi(FLUSH_ADDR), %g5
514 flush %g5
564 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
723 andn %g4, PSTATE_IE, %g5
724 wrpr %g0, %g5, %pstate ! disable interrupts
727 or %g0, 1, %g5
[all …]
/illumos-gate/usr/src/common/bignum/sun4u/
H A Dmont_mulf_v9.s232 /* 0x0008 77 */ sra %i3,0,%g5
241 /* 0x0014 86 */ sub %g5,1,%g2
249 /* 0x0034 */ sub %g5,1,%g4
252 /* 0x0040 */ sub %g5,2,%l0
277 /* 0x0074 */ or %g0,3,%g5
279 /* 0x007c */ or %g0,32,%g5
293 /* 0x00b4 87 */ ldd [%i1+%g5],%f0
294 /* 0x00b8 91 */ sllx %g3,16,%g5
296 /* 0x00c0 86 */ add %l6,%g5,%l7
307 /* 0x00ec 90 */ ldx [%sp+2223],%g5
[all …]
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu_asm.S87 CPU_TSBMISS_AREA(%g5, %g6) /* load cpu tsbmiss area */
88 ldx [%g5 + TSBMISS_UHATID], %g5 /* load usfmmup */
89 cmp %g5, %g1 /* hat toBe-invalid running? */
94 sethi %hi(shctx_on), %g5
95 ld [%g5 + %lo(shctx_on)], %g5
96 brz %g5, 1f
97 mov MMU_SHARED_CONTEXT, %g5
99 stxa %g0, [%g5]ASI_MMU_CTX
103 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = pgsz | sec-ctx */
105 and %g5, %g4, %g5 /* %g5 = sec-ctx */
[all …]
/illumos-gate/usr/src/lib/libc/sparcv9/gen/
H A Dstrncpy.S105 andcc %g5, 7, %g0 ! dst word aligned ?
114 sub %o1, %o4, %g5 ! dword - 0x0101010101010101
115 andcc %g5, %g1, %g0 ! ((dword - 0x0101010101010101) & ~dword & 0x8080808080808080)
274 sub %o1, %o4, %g5 ! x - 0x0101010101010101
275 andcc %g5, %g1, %g0 ! ((x - 0x0101010101010101) & ~x & 0x8080808080808080)
277 add %o2, %g4, %g5 ! dst (in pointer form)
279 stb %g1, [%g5] ! store first byte
281 stw %g1, [%g5 + 1] ! store bytes 2, 3, 4, 5
283 sth %g1, [%g5 + 5] ! store bytes 6, 7
285 stb %o1, [%g5 + 7] ! store eigth byte
[all …]
H A Dmemcpy.S61 mov %o0, %g5 ! save des address for return val
71 stb %o3, [%g5] ! move a byte to align src
72 inc 1, %g5
76 andcc %g5, 3, %o5
81 stb %o4, [%g5] ! have to do bytes,
82 stb %o3, [%g5 + 1] ! don't know dst alingment
/illumos-gate/usr/src/lib/libc/sparcv9/crt/
H A D__align_cpy_2.S44 mov %o0, %g5 ! save des address for return val
54 sth %o3, [%g5] ! move 2 bytes to align src
55 inc 2, %g5
59 andcc %g5, 6, %o5
64 sth %o4, [%g5] ! have to do 2-bytes,
65 sth %o3, [%g5 + 2] ! don't know dst alignment
/illumos-gate/usr/src/uts/sun4u/sunfire/ml/
H A Dsysctrl_asm.S61 CPU_INDEX(%g4, %g5)
68 sethi %hi(panicstr), %g5
69 ldn [%g5 + %lo(panicstr)], %g5
70 brnz %g5, 2f ! exit if in panic
/illumos-gate/usr/src/uts/sun4/ml/
H A Dinterrupt.S51 ! %g3, %g5, %g6, %g7 - temps
58 CPU_ADDR(%g1, %g5) ! %g1 = cpu
61 sll %g4, CPTRSHIFT, %g5 ! %g5 = offset to the pil entry
63 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
76 add %g7, %g3, %g7 ! %g5 = &iv->iv_xpil_next[cpuid]
82 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
83 mov 1, %g5 ! %g5 = 1
84 sll %g5, %g4, %g5 ! %g5 = 1 << pil
85 wr %g5, CLEAR_SOFTINT ! clear interrupt on this pil
88 TRACE_PTR(%g5, %g6)
[all …]
/illumos-gate/usr/src/lib/libmvec/common/vis/
H A D__vatan2.S79 ! g5
185 sethi %hi(0x80000000),%g5
188 andn %o0,%g5,%o0
189 andn %l3,%g5,%l3
214 sub %l3,%o3,%g5
221 andcc %g5,%o7,%g0
259 sethi %hi(0x80000000),%g5
263 andn %o0,%g5,%o0
264 andn %l3,%g5,%l3
286 sub %l3,%o3,%g5
[all …]
H A D__vrsqrtf.S400 lda [stridex+%l7]0x82,%g5 ! (5_0) ax1 = *(int*)(px + stridex);
412 sra %g5,13,%l6 ! (5_0) si1 = ax1 >> 13;
417 sra %g5,24,%l7 ! (5_0) iexp1 = ax1 >> 24;
449 cmp %g5,_0x7f800000 ! (5_1) ax1 ? 0x7f800000
454 cmp %g5,_0x00800000 ! (5_1) ax1 ? 0x00800000
461 sra %i4,13,%g5 ! (1_0) si1 = ax1 >> 13;
466 and %g5,2032,%o7 ! (1_0) si1 &= 0x7f0;
474 sub %l0,%i3,%g5 ! (0_0) iexp0 = 0x3f - iexp0;
487 sllx %g5,55,%g5 ! (0_0) lexp0 = iexp0 << 55;
490 or %g5,%i0,%g5 ! (0_0) lexp0 |= lexp1;
[all …]
/illumos-gate/usr/src/uts/sparc/dtrace/
H A Ddtrace_asm.S134 rd %pc, %g5
136 add %g5, 12, %g5
156 add %g5, %o1, %g5 ! %g5 now contains the instr. to pick
353 rdpr %otherwin, %g5 ! compute the number of iterations
354 cmp %g5, %o1 ! (windows to observe) by taking the
355 movg %icc, %o1, %g5 ! min of %otherwin and pcstack_limit
357 brlez,a,pn %g5, 2f ! return 0 if count <= 0
/illumos-gate/usr/src/uts/sun4/brand/common/
H A Dbrand_solaris.S223 ldn [%g4 + P_BRAND_DATA], %g5; /* get brand data ptr */
224 ldn [%g5 + SPD_HANDLER], %g5; /* get userland brnd hdlr ptr */
225 brz %g5, _exit; /* has it been set? */
250 wrpr %g0, %g5, %tnpc; /* setup tnpc */
252 mov %l1, %g5; /* pass tnpc to user code in %g5 */

1234