Lines Matching refs:g5
60 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
61 ! sfar (g5 == T_ALIGNMENT)
77 cmp %g5, T_ALIGNMENT
88 rdpr %tstate, %g5
89 and %g5, TSTATE_CWP, %g5
91 wrpr %g0, %g5, %cwp
157 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
158 CPU_PADDR(%g5, %g6)
163 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
164 lda [%g6 + MPCB_WBCNT]%asi, %g5
165 add %g5, 1, %g7
170 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
173 sll %g5, RWIN32SHIFT, %g7
174 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
175 add %g5, %g7, %g7
178 set sys_trap, %g5
179 wrpr %g5, %tnpc
196 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
197 ! sfar (g5 == T_ALIGNMENT)
212 mov %g5, %g3 ! arg3 = traptype
213 cmp %g5, T_ALIGNMENT
224 rdpr %tstate, %g5
225 and %g5, TSTATE_CWP, %g5
227 wrpr %g0, %g5, %cwp
350 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
351 CPU_PADDR(%g5, %g6)
356 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
357 lda [%g6 + MPCB_WBCNT]%asi, %g5
358 add %g5, 1, %g7
363 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
366 sll %g5, RWIN64SHIFT, %g7
367 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
368 add %g5, %g7, %g7
371 set sys_trap, %g5
372 wrpr %g5, %tnpc
396 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
397 ! sfar (g5 == T_ALIGNMENT)
402 cmp %g5, T_ALIGNMENT
413 rdpr %tstate, %g5
414 and %g5, TSTATE_CWP, %g5
416 wrpr %g0, %g5, %cwp