Lines Matching refs:g5
290 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
291 srlx %g5, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
297 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
333 sethi %hi(FLUSH_ADDR), %g5
337 flush %g5 ! flush required by immu
350 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
356 or %g5, %g4, %g5
362 or %g5, %g2, %g5 /* %g5 = nucleus pgsz | primary pgsz | cnum */
363 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
366 sethi %hi(FLUSH_ADDR), %g5
370 flush %g5 ! flush required by immu
422 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
598 PN_L2_FLUSHALL(%g3, %g4, %g5)
874 mov 1, %g5
875 sll %g5, PIL_15, %g5
876 wr %g5, CLEAR_SOFTINT
1030 PARK_SIBLING_CORE(%g1, %g5, %g4)
1048 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1055 PN_L2_FLUSHALL(%g4, %g5, %g6)
1057 CPU_INDEX(%g4, %g5)
1059 set cpunodes, %g5
1060 add %g4, %g5, %g4
1061 ld [%g4 + ECACHE_LINESIZE], %g5
1065 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
1071 ASM_LD(%g5, dcache_size)
1073 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1080 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_5);
1081 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1083 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1085 ASM_LD(%g5, icache_size)
1088 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1096 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1314 PARK_SIBLING_CORE(%g1, %g5, %g4)
1331 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1338 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, ce_err_1);
1339 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1341 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1343 ASM_LD(%g5, icache_size)
1346 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1354 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1512 andcc %g5, T_TL1, %g0
1516 sllx %g5, CLO_FLAGS_TT_SHIFT, %g4
1523 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1541 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, async_err_1);
1542 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1544 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1546 ASM_LD(%g5, icache_size)
1549 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1559 ASM_LD(%g5, dcache_size)
1561 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1569 UNPARK_SIBLING_CORE(%g1, %g5, %g7)
1608 RESET_USER_RTT_REGS(%g4, %g5, async_err_resetskip)
1688 CPU_INDEX(%g6, %g5)
1690 set trap_trace_ctl, %g5
1691 add %g6, %g5, %g6
1692 ld [%g6 + TRAPTR_LIMIT], %g5
1693 tst %g5
1696 ldx [%g6 + TRAPTR_PBASE], %g5
1698 add %g5, %g4, %g5
1706 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
1708 stha %g4, [%g5 + TRAP_ENT_TL]%asi
1710 stha %g4, [%g5 + TRAP_ENT_TT]%asi
1712 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
1714 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
1715 stna %sp, [%g5 + TRAP_ENT_SP]%asi
1716 stna %g0, [%g5 + TRAP_ENT_TR]%asi
1717 stna %g0, [%g5 + TRAP_ENT_F1]%asi
1718 stna %g0, [%g5 + TRAP_ENT_F2]%asi
1719 stna %g0, [%g5 + TRAP_ENT_F3]%asi
1720 stna %g0, [%g5 + TRAP_ENT_F4]%asi
1726 ld [%g6 + TRAPTR_OFFSET], %g5
1728 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
1729 add %g5, TRAP_ENT_SIZE, %g5
1731 cmp %g5, %g4
1732 movge %icc, 0, %g5
1733 st %g5, [%g6 + TRAPTR_OFFSET]
1833 CPU_INDEX(%g6, %g5)
1835 set trap_trace_ctl, %g5
1836 add %g6, %g5, %g6
1837 ld [%g6 + TRAPTR_LIMIT], %g5
1838 tst %g5
1841 ldx [%g6 + TRAPTR_PBASE], %g5
1843 add %g5, %g4, %g5
1851 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
1853 stha %g4, [%g5 + TRAP_ENT_TL]%asi
1855 stha %g4, [%g5 + TRAP_ENT_TT]%asi
1857 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
1859 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
1860 stna %sp, [%g5 + TRAP_ENT_SP]%asi
1861 stna %g0, [%g5 + TRAP_ENT_TR]%asi
1862 stna %g0, [%g5 + TRAP_ENT_F1]%asi
1863 stna %g0, [%g5 + TRAP_ENT_F2]%asi
1864 stna %g0, [%g5 + TRAP_ENT_F3]%asi
1865 stna %g0, [%g5 + TRAP_ENT_F4]%asi
1871 ld [%g6 + TRAPTR_OFFSET], %g5
1873 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
1874 add %g5, TRAP_ENT_SIZE, %g5
1876 cmp %g5, %g4
1877 movge %icc, 0, %g5
1878 st %g5, [%g6 + TRAPTR_OFFSET]
2215 ! %g2, %g3, %g5 - scratch
2223 GET_CPU_PRIVATE_PTR(%g2, %g4, %g5, 1f);