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Searched refs:wr32 (Results 1 – 25 of 30) sorted by relevance

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/freebsd/sys/dev/iavf/
H A Diavf_adminq.c289 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
290 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
293 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in iavf_config_asq_regs()
295 wr32(hw, hw->aq.asq.bal, IAVF_LO_DWORD(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
296 wr32(hw, hw->aq.asq.bah, IAVF_HI_DWORD(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
318 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
319 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
322 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in iavf_config_arq_regs()
324 wr32(hw, hw->aq.arq.bal, IAVF_LO_DWORD(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
325 wr32(hw, hw->aq.arq.bah, IAVF_HI_DWORD(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
[all …]
H A Diavf_lib.c370 wr32(hw, IAVF_VFINT_DYN_CTL01, in iavf_enable_adminq_irq()
374 wr32(hw, IAVF_VFINT_ICR0_ENA1, IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK); in iavf_enable_adminq_irq()
388 wr32(hw, IAVF_VFINT_DYN_CTL01, 0); in iavf_disable_adminq_irq()
389 wr32(hw, IAVF_VFINT_ICR0_ENA1, 0); in iavf_disable_adminq_irq()
766 wr32(hw, IAVF_VFINT_ITRN1(IAVF_TX_ITR, i), in iavf_configure_tx_itr()
791 wr32(hw, IAVF_VFINT_ITRN1(IAVF_RX_ITR, i), in iavf_configure_rx_itr()
1088 wr32(hw, IAVF_VFQF_HENA(0), 0); in iavf_config_rss_reg()
1089 wr32(hw, IAVF_VFQF_HENA(1), 0); in iavf_config_rss_reg()
1103 wr32(hw, IAVF_VFQF_HKEY(i), rss_seed[i]); in iavf_config_rss_reg()
1128 wr32(hw, IAVF_VFQF_HENA(0), (u32)hena); in iavf_config_rss_reg()
[all …]
H A Dif_iavf_iflib.c702 wr32(vsi->hw, rxr->tail, 0); in iavf_init_queues()
1158 wr32(hw, hw->aq.arq.len, reg); in iavf_check_aq_errors()
1177 wr32(hw, hw->aq.asq.len, reg); in iavf_check_aq_errors()
1238 wr32(hw, IAVF_VFINT_ICR0_ENA1, reg); in iavf_process_adminq()
1611 wr32(hw, IAVF_VFINT_ICR0_ENA1, mask); in iavf_msix_adminq()
1667 wr32(hw, IAVF_VFINT_DYN_CTLN1(id), reg); in iavf_enable_queue_irq()
1680 wr32(hw, IAVF_VFINT_DYN_CTLN1(id), in iavf_disable_queue_irq()
1718 wr32(hw, IAVF_VFINT_ITRN1(IAVF_RX_ITR, in iavf_set_queue_rx_itr()
H A Diavf_txrx_iflib.c417 wr32(vsi->hw, txr->tail, pidx); in iavf_isc_txd_flush()
437 wr32(vsi->hw, txr->tail, 0); in iavf_init_tx_ring()
607 wr32(vsi->hw, rxr->tail, pidx); in iavf_isc_rxd_flush()
H A Diavf_osdep.h247 #define wr32(hw, reg, val) iavf_wr32(hw, reg, val) macro
/freebsd/sys/dev/ixl/
H A Di40e_hmc.h139 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
140 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
141 wr32((hw), I40E_PFHMC_SDCMD, val3); \
158 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
159 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
160 wr32((hw), I40E_PFHMC_SDCMD, val3); \
170 wr32((hw), I40E_PFHMC_PDINV, \
H A Di40e_adminq.c304 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
305 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
309 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
314 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
315 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
337 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
338 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
342 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
345 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
[all …]
H A Dixl_pf_iflib.c48 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), in ixl_configure_tx_itr()
67 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), in ixl_configure_rx_itr()
87 wr32(hw, I40E_PFINT_DYN_CTL0, in ixl_intr()
216 wr32(hw, I40E_PFHMC_ERRORINFO, 0); in ixl_msix_adminq()
227 wr32(hw, I40E_PFINT_ICR0_ENA, mask); in ixl_msix_adminq()
251 wr32(hw, I40E_PFINT_DYN_CTLN(i), 0); in ixl_configure_queue_intr_msix()
258 wr32(hw, I40E_PFINT_LNKLSTN(i), reg); in ixl_configure_queue_intr_msix()
265 wr32(hw, I40E_QINT_RQCTL(i), reg); in ixl_configure_queue_intr_msix()
272 wr32(hw, I40E_QINT_TQCTL(i), reg); in ixl_configure_queue_intr_msix()
298 wr32(hw, I40E_PFINT_ICR0_ENA, reg); in ixl_configure_legacy()
[all …]
H A Dixl_pf_i2c.c176 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_clock_in_i2c_bit()
213 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_get_i2c_ack()
305 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_clock_out_i2c_byte()
326 wr32(hw, IXL_I2C_REG(hw), *i2cctl); in ixl_lower_i2c_clk()
352 wr32(hw, IXL_I2C_REG(hw), *i2cctl); in ixl_raise_i2c_clk()
405 wr32(hw, IXL_I2C_REG(hw), *i2cctl); in ixl_set_i2c_data()
468 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_read_i2c_byte_bb()
535 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_read_i2c_byte_bb()
555 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_write_i2c_byte_bb()
601 wr32(hw, IXL_I2C_REG(hw), i2cctl); in ixl_write_i2c_byte_bb()
[all …]
H A Dixl_iw.c59 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); in ixl_iw_pf_msix_reset()
342 wr32(hw, I40E_PFINT_AEQCTL, reg); in ixl_iw_pf_msix_init()
351 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); in ixl_iw_pf_msix_init()
356 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); in ixl_iw_pf_msix_init()
364 wr32(hw, I40E_PFINT_CEQCTL(i), reg); in ixl_iw_pf_msix_init()
H A Dixl_pf_iov.c258 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num), in ixl_vf_map_queues()
267 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), qtable); in ixl_vf_map_queues()
270 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), in ixl_vf_map_queues()
305 wr32(hw, vfint_reg, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); in ixl_vf_disable_queue_intr()
313 wr32(hw, vpint_reg, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | in ixl_vf_unregister_intr()
360 wr32(hw, I40E_PF_PCI_CIAA, IXL_PF_PCI_CIAA_VF_DEVICE_STATUS | in ixl_flush_pcie()
384 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); in ixl_reset_vf()
418 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), VIRTCHNL_VFR_COMPLETED); in ixl_reinit_vf()
422 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); in ixl_reinit_vf()
432 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), VIRTCHNL_VFR_VFACTIVE); in ixl_reinit_vf()
[all …]
H A Di40e_lan_hmc.c521 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
523 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
527 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
529 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
533 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id), in i40e_configure_lan_hmc()
535 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
539 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id), in i40e_configure_lan_hmc()
541 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
H A Dixl_pf_main.c708 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ in ixl_configure_intr0_msix()
719 wr32(hw, I40E_PFINT_ICR0_ENA, reg); in ixl_configure_intr0_msix()
726 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); in ixl_configure_intr0_msix()
728 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x3E); in ixl_configure_intr0_msix()
730 wr32(hw, I40E_PFINT_DYN_CTL0, in ixl_configure_intr0_msix()
734 wr32(hw, I40E_PFINT_STAT_CTL0, 0); in ixl_configure_intr0_msix()
1620 wr32(hw, I40E_QTX_ENA(pf_qidx), reg); in ixl_enable_tx_ring()
1654 wr32(hw, I40E_QRX_ENA(pf_qidx), reg); in ixl_enable_rx_ring()
1706 wr32(hw, I40E_QTX_ENA(pf_qidx), reg); in ixl_disable_tx_ring()
1742 wr32(hw, I40E_QRX_ENA(pf_qidx), reg); in ixl_disable_rx_ring()
[all …]
H A Di40e_common.c1175 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
1381 wr32(hw, I40E_PFGEN_CTRL, in i40e_pf_reset()
1453 wr32(hw, I40E_PFINT_ICR0_ENA, 0); in i40e_clear_hw()
1456 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); in i40e_clear_hw()
1460 wr32(hw, I40E_PFINT_LNKLST0, val); in i40e_clear_hw()
1462 wr32(hw, I40E_PFINT_LNKLSTN(i), val); in i40e_clear_hw()
1465 wr32(hw, I40E_VPINT_LNKLST0(i), val); in i40e_clear_hw()
1467 wr32(hw, I40E_VPINT_LNKLSTN(i), val); in i40e_clear_hw()
1484 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); in i40e_clear_hw()
1490 wr32(hw, I40E_QINT_TQCTL(i), 0); in i40e_clear_hw()
[all …]
H A Dixl_txrx.c425 wr32(vsi->hw, txr->tail, pidx); in ixl_isc_txd_flush()
444 wr32(vsi->hw, txr->tail, 0); in ixl_init_tx_ring()
574 wr32(vsi->hw, rxr->tail, pidx); in ixl_isc_rxd_flush()
H A Di40e_osdep.h224 #define wr32(a, reg, value) wr32_osdep((a)->back, (reg), (value)) macro
/freebsd/sys/dev/ice/
H A Dice_controlq.c271 wr32(hw, ring->head, 0);
272 wr32(hw, ring->tail, 0);
275 wr32(hw, ring->len, (num_entries | ring->len_ena_mask));
276 wr32(hw, ring->bal, ICE_LO_DWORD(ring->desc_buf.pa));
277 wr32(hw, ring->bah, ICE_HI_DWORD(ring->desc_buf.pa));
316 wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));
482 wr32(hw, cq->sq.head, 0); in ice_shutdown_sq()
483 wr32(hw, cq->sq.tail, 0);
484 wr32(hw, cq->sq.len, 0);
485 wr32(h
[all...]
H A Dice_iflib_txrx.c232 wr32(hw, txq->tail, pidx); in ice_ift_txd_credits_update()
544 wr32(&sc->hw, rxq->tail, pidx);
666 wr32(hw, txq->tail, pidx);
H A Dice_lib.c1385 wr32(hw, QINT_RQCTL(rxqid), val);
1433 wr32(hw, QINT_TQCTL(txqid), val); in ice_flush_rxq_interrupts()
1483 wr32(hw, QINT_RQCTL(reg), val);
1490 wr32(hw, GLINT_DYN_CTL(rxq->irqv->me), in ice_configure_rx_itr()
1520 wr32(hw, QINT_TQCTL(reg), val); in ice_configure_tx_itr()
1527 wr32(hw, GLINT_DYN_CTL(txq->irqv->me),
1549 wr32(hw, GLINT_ITR(ICE_RX_ITR, rxq->irqv->me), in ice_setup_tx_ctx()
1573 wr32(hw, GLINT_ITR(ICE_TX_ITR, txq->irqv->me), in ice_setup_tx_ctx()
1759 wr32(hw, QRXFLXP_CNTXT(pf_q), regval); in ice_is_rxq_ready()
1770 wr32(h in ice_is_rxq_ready()
[all...]
H A Dice_lib.h852 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl); in ice_enable_intr()
869 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl); in ice_disable_intr()
H A Dice_osdep.c229 * wr32 - Write a 32bit hardware register
237 wr32(struct ice_hw *hw, uint32_t reg, uint32_t val) in wr32() function
H A Dice_common.c1297 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); in ice_copy_rxq_ctx_to_hw()
1354 wr32(hw, GLGEN_RTRIG, val);
1382 wr32(hw, QRX_CONTEXT(i, rxq_index),
1516 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1579 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1642 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1669 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1734 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); in ice_sq_send_cmd_retry()
5997 wr32(hw, GLV_REPC(vsi_num), 0);
6006 wr32(h in ice_aq_read_i2c()
[all...]
H A Dice_osdep.h87 void wr32(struct ice_hw *hw, uint32_t reg, uint32_t val);
/freebsd/sys/dev/irdma/
H A Dicrdma_hw.c390 wr32(hw, GLPE_WQMTXIDXADDR, 0x12); in disable_prefetch()
395 wr32(hw, GLPE_WQMTXIDXDATA, wqm_data); in disable_prefetch()
403 wr32(hw, GLPE_WQMTXIDXADDR, 0x12); in disable_tx_spad()
408 wr32(hw, GLPE_WQMTXIDXDATA, wqm_data); in disable_tx_spad()
420 wr32(hw, GL_RDPU_CNTRL, val); in rdpu_ackreqpmthresh()
H A Dosdep.h184 #define wr32(a, reg, value) irdma_wr32((a)->dev_context, (reg), (value)) macro

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