1175 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);  in i40e_pre_tx_queue_cfg()
1381 		wr32(hw, I40E_PFGEN_CTRL,  in i40e_pf_reset()
1453 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);  in i40e_clear_hw()
1456 		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);  in i40e_clear_hw()
1460 	wr32(hw, I40E_PFINT_LNKLST0, val);  in i40e_clear_hw()
1462 		wr32(hw, I40E_PFINT_LNKLSTN(i), val);  in i40e_clear_hw()
1465 		wr32(hw, I40E_VPINT_LNKLST0(i), val);  in i40e_clear_hw()
1467 		wr32(hw, I40E_VPINT_LNKLSTN(i), val);  in i40e_clear_hw()
1484 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);  in i40e_clear_hw()
1490 		wr32(hw, I40E_QINT_TQCTL(i), 0);  in i40e_clear_hw()
1491 		wr32(hw, I40E_QTX_ENA(i), 0);  in i40e_clear_hw()
1492 		wr32(hw, I40E_QINT_RQCTL(i), 0);  in i40e_clear_hw()
1493 		wr32(hw, I40E_QRX_ENA(i), 0);  in i40e_clear_hw()
1638 		wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);  in i40e_led_set()
1913 	wr32(hw, I40E_GLLAN_RCTL_0, 0x1);  in i40e_aq_clear_pxe_mode()
6445 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_read_phy_register_clause22()
6486 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);  in i40e_write_phy_register_clause22()
6494 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_write_phy_register_clause22()
6533 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_read_phy_register_clause45()
6558 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_read_phy_register_clause45()
6607 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_write_phy_register_clause45()
6624 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);  in i40e_write_phy_register_clause45()
6634 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);  in i40e_write_phy_register_clause45()
7289 		wr32(hw, reg_addr, reg_val);  in i40e_write_rx_ctl()