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Searched refs:vdst (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_vector_clock.cpp43 m128* __restrict vdst = reinterpret_cast<m128*>(clk_); in Acquire() local
47 m128 d = _mm_load_si128(&vdst[i]); in Acquire()
49 _mm_store_si128(&vdst[i], m); in Acquire()
75 m128* __restrict vdst = reinterpret_cast<m128*>(clk_); in operator =()
79 _mm_store_si128(&vdst[i], s); in operator =()
94 m128* __restrict vdst = reinterpret_cast<m128*>(dst->clk_); in ReleaseStoreAcquire() local
97 m128 t = _mm_load_si128(&vdst[i]); in ReleaseStoreAcquire()
100 _mm_store_si128(&vdst[i], c); in ReleaseStoreAcquire()
114 m128* __restrict vdst = reinterpret_cast<m128*>(dst->clk_); in ReleaseAcquire() local
118 m128 d = _mm_load_si128(&vdst[i]); in ReleaseAcquire()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DDSDIRInstructions.td18 bits<8> vdst;
27 let Inst{7-0} = vdst;
35 bits<8> vdst;
46 let Inst{7-0} = vdst;
69 InstSI<(outs VGPR_32:$vdst), ins, asm> {
98 " $vdst$waitvdst",
99 " $vdst, $attr$attrchan$waitvdst"
105 " $vdst$waitvdst$waitvsrc",
106 " $vdst, $attr$attrchan$waitvdst$waitvsrc"
H A DLDSDIRInstructions.td
H A DVINTERPInstructions.td14 bits<8> vdst;
27 let Inst{7-0} = vdst;
76 let Outs64 = (outs VGPR_32:$vdst);
83 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
94 let Outs64 = (outs VGPR_32:$vdst);
101 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
H A DVOPInstructions.td267 bits<8> vdst;
268 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
272 bits<8> vdst;
273 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
279 bits<8> vdst;
280 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
355 bits<8> vdst;
365 let Inst{7-0} = vdst;
378 bits<8> vdst;
389 let Inst{7-0} = vdst;
[all …]
H A DVOP1Instructions.td15 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
25 bits<8> vdst;
29 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
34 bits<8> vdst;
38 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
183 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
[all …]
H A DVOP2Instructions.td14 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
26 bits<8> vdst;
33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
40 bits<8> vdst;
45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
51 bits<8> vdst;
56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
132 [(set P.DstVT:$vdst,
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
[all …]
H A DSIPeepholeSDWA.cpp405 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
421 AMDGPU::OpName::vdst); in convertToSDWA()
489 MachineOperand *Operand = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
529 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
591 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
628 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
690 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
719 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
853 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
942 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) in pseudoOpConvertToVOP2()
[all …]
H A DDSInstructions.td81 bits<10> vdst;
93 bits<1> acc = !if(ps.has_vdst, vdst{9},
178 (outs dst_op:$vdst),
180 " $vdst, $data0$offset gds"> {
192 (outs data_op:$vdst),
194 " $vdst, $addr, $data0$offset$gds"> {
221 (outs dst_op:$vdst),
223 " $vdst, $addr, $data0, $data1$offset$gds"> {
245 (outs dst_op:$vdst),
247 " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
[all …]
H A DVOP3Instructions.td11 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
13 let Outs64 = (outs DstRC.RegClass:$vdst);
19 let Outs64 = (outs DstRC.RegClass:$vdst);
25 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
26 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
39 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
40 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
69 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
77 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
87 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
[all …]
H A DSIInstructions.td47 (outs VINTRPDst:$vdst),
49 "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
50 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
61 Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
66 // Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
73 (outs VINTRPDst:$vdst),
76 "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
[all …]
H A DVOP3PInstructions.td54 "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
76 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", "");
84 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", "");
555 let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp";
571 let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid";
572 let Outs64 = (outs DstRC:$vdst);
689 let Constraints = !if(NoDstOverlap, "@earlyclobber $vdst", "") in {
701 let Constraints = !if(NoDstOverlap, "$vdst = $src2", ""),
777 let Constraints = "$vdst = $src2", DisableEncoding = "$src2",
920 // 1) Map the intrinsic to the pseudo where D is tied to C ($vdst = $src2).
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H A DGCNDPPCombine.cpp242 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
260 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
500 auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in createDPPInst()
528 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
H A DMIMGInstructions.td877 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
878 let Constraints = "$vdst = $vdata";
883 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
888 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
889 let Constraints = "$vdst = $vdata";
895 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
922 : MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst),
924 let Constraints = "$vdst = $vdata";
929 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
935 : MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs,
[all …]
H A DFLATInstructions.td112 bits<10> vdst;
126 bits<1> acc = !if(ps.has_vdst, vdst{9}, !if(ps.has_data, vdata{9}, 0));
146 let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, ?);
174 bits<8> vdst;
183 let Inst{39-32} = !if(ps.has_vdst, vdst, ?);
206 (outs vdata_op:$vdst),
216 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
222 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
255 (outs regClass:$vdst),
259 " $vdst, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
[all …]
H A DSIInstrInfo.td1966 (outs DstRCDPP:$vdst)),
1975 (outs DstRCSDWA:$vdst)),
1982 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1993 string dst = "$vdst" # XorY;
2005 string dst = "$vdst";
2027 string dst = "$vdst";
2054 "$vdst"),
2083 "$vdst"),
2130 "$vdst"),
2159 "$vdst"), // VOP1/2
[all …]
H A DSIInstrFormats.td325 bits<8> vdst;
334 let Inst{25-18} = vdst;
H A DGCNHazardRecognizer.cpp897 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
932 if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in checkVALUHazards()
1206 SDSTName = AMDGPU::OpName::vdst; in fixSMEMtoVectorWriteHazards()
1413 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVALUHazard()
1456 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVMEMHazard()
1740 TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg(); in fixWMMAHazards()
H A DSILoadStoreOptimizer.cpp1145 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1339 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); in mergeRead2Pair()
1647 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); in mergeFlatLoadPair()
/freebsd/sys/opencrypto/
H A Dcriov.c543 crypto_cursor_copydata(struct crypto_buffer_cursor *cc, int size, void *vdst) in crypto_cursor_copydata() argument
549 dst = vdst; in crypto_cursor_copydata()
638 void *vdst) in crypto_cursor_copydata_noadv() argument
643 crypto_cursor_copydata(&copy, size, vdst); in crypto_cursor_copydata_noadv()
H A Dcryptodev.h683 void *vdst);
685 void *vdst);
/freebsd/contrib/tcsh/
H A Dtc.os.c980 xmemmove(void *vdst, const void *vsrc, size_t len) in xmemmove() argument
983 char *dst = vdst; in xmemmove()
986 return vdst; in xmemmove()
998 return vdst; in xmemmove()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td2460 [llvm_i32_ty, llvm_i32_ty], // %vdst, %addr
2873 // llvm.amdgcn.mfma.*.* vdst, srcA, srcB, srcC, cbsz, abid, blgp
2941 // llvm.amdgcn.smfmac.?32.* vdst, srcA, srcB, srcC, index, cbsz, abid
2982 // llvm.amdgcn.cvt.f32.bf8 float vdst, int srcA, imm byte_sel [0..3]
2989 // llvm.amdgcn.cvt.f32.fp8 float vdst, int srcA, imm byte_sel [0..3]
2995 // llvm.amdgcn.cvt.pk.f32.bf8 float2 vdst, int srcA, imm word_sel
3002 // llvm.amdgcn.cvt.pk.f32.fp8 float2 vdst, int srcA, imm word_sel.
3008 // llvm.amdgcn.cvt.pk.bf8.f32 int vdst, float srcA, float srcB, int old, imm word_sel
3009 // word_sel = 1 selects 2 high bytes in the vdst, 0 selects 2 low bytes.
3015 // llvm.amdgcn.cvt.pk.fp8.f32 int vdst, float srcA, float srcB, int old, imm word_sel
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp409 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeAVLdSt()
844 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, in convertTrue16OpSel()
949 AMDGPU::OpName::vdst); in convertMIMGInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp621 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst); in getMachineOpValueT16()

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