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Searched refs:vdst (Results 1 – 25 of 35) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_vector_clock.cpp43 m128* __restrict vdst = reinterpret_cast<m128*>(clk_); in Acquire() local
47 m128 d = _mm_load_si128(&vdst[i]); in Acquire()
49 _mm_store_si128(&vdst[i], m); in Acquire()
75 m128* __restrict vdst = reinterpret_cast<m128*>(clk_); in operator =()
79 _mm_store_si128(&vdst[i], s); in operator =()
94 m128* __restrict vdst = reinterpret_cast<m128*>(dst->clk_); in ReleaseStoreAcquire() local
97 m128 t = _mm_load_si128(&vdst[i]); in ReleaseStoreAcquire()
100 _mm_store_si128(&vdst[i], c); in ReleaseStoreAcquire()
114 m128* __restrict vdst = reinterpret_cast<m128*>(dst->clk_); in ReleaseAcquire() local
118 m128 d = _mm_load_si128(&vdst[i]); in ReleaseAcquire()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DDSDIRInstructions.td18 bits<8> vdst;
27 let Inst{7-0} = vdst;
35 bits<8> vdst;
46 let Inst{7-0} = vdst;
69 InstSI<(outs VGPR_32:$vdst), ins, asm> {
98 " $vdst$waitvdst",
99 " $vdst, $attr$attrchan$waitvdst"
105 " $vdst$waitvdst$waitvsrc",
106 " $vdst, $attr$attrchan$waitvdst$waitvsrc"
H A DLDSDIRInstructions.td
H A DVOP1Instructions.td15 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
25 bits<8> vdst;
29 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
34 bits<8> vdst;
38 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
115 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
117 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
189 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
[all …]
H A DVOPInstructions.td255 bits<11> vdst;
265 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
305 bits<8> vdst;
306 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
310 bits<8> vdst;
311 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
321 bits<8> vdst;
322 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
413 bits<8> vdst;
423 let Inst{7-0} = vdst;
[all …]
H A DVOP2Instructions.td14 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
26 bits<8> vdst;
33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
40 bits<8> vdst;
47 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
54 bits<8> vdst;
59 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
65 bits<8> vdst;
70 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
[all …]
H A DVINTERPInstructions.td14 bits<11> vdst;
27 let Inst{7-0} = vdst{7-0};
78 let Outs64 = (outs VGPR_32:$vdst);
85 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
100 let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
116 let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
H A DSIPeepholeSDWA.cpp472 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
488 AMDGPU::OpName::vdst); in convertToSDWA()
599 MachineOperand *Operand = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
650 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
717 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
756 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
820 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
849 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
983 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
1073 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) in pseudoOpConvertToVOP2()
[all …]
H A DDSInstructions.td82 bits<10> vdst;
94 bits<1> acc = !if(ps.has_vdst, vdst{9},
188 (outs dst_op:$vdst),
190 " $vdst, $data0$offset gds"> {
202 (outs data_op:$vdst),
204 " $vdst, $addr, $data0$offset$gds"> {
230 (outs dst_op:$vdst),
232 " $vdst, $addr, $data0, $data1$offset$gds"> {
253 (outs dst_op:$vdst),
255 " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
[all …]
H A DVOP3Instructions.td14 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
16 let Outs64 = (outs DstRC.RegClass:$vdst);
22 let Outs64 = (outs DstRC.RegClass:$vdst);
28 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
29 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
43 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
44 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
78 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
86 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
96 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
[all …]
H A DAMDGPUMCInstLower.cpp131 OpName = llvm::AMDGPU::OpName::vdst; in lowerT16D16Helper()
139 : llvm::AMDGPU::OpName::vdst; in lowerT16D16Helper()
257 TII->getNamedOperand(*MI, MI->mayLoad() ? AMDGPU::OpName::vdst in emitVGPRBlockComment()
H A DSIInstructions.td47 (outs VINTRPDst:$vdst),
49 "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
50 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
61 Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
66 // Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
73 (outs VINTRPDst:$vdst),
76 "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
[all …]
H A DVOP3PInstructions.td60 "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
82 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", "");
90 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", "");
618 let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz"#!if(HasAbid,"$abid","")#"$blgp";
637 let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid";
638 let Outs64 = (outs DstRC:$vdst);
811 // Does this MFMA use "AGPR" or "VGPR" for srcC/vdst
901 "$vdst, $src0, $src1, $src2, $scale_src0, $scale_src1"
915 let Constraints = !if(NoDstOverlap, "@earlyclobber $vdst", "") in {
927 let Constraints = !if(NoDstOverlap, "$vdst = $src2", ""),
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H A DGCNDPPCombine.cpp248 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
266 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
506 auto *MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in createDPPInst()
534 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
H A DMIMGInstructions.td877 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
878 let Constraints = "$vdst = $vdata";
883 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
888 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
889 let Constraints = "$vdst = $vdata";
895 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
922 : MIMG_gfx10<op.GFX10M, (outs DataRC:$vdst),
924 let Constraints = "$vdst = $vdata";
929 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
935 : MIMG_nsa_gfx10<op.GFX10M, (outs DataRC:$vdst), num_addrs,
[all …]
H A DFLATInstructions.td121 bits<10> vdst;
135 bits<1> acc = !if(ps.has_vdst, vdst{9}, !if(ps.has_data, vdata{9}, 0));
155 let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, ?);
184 bits<8> vdst;
193 let Inst{39-32} = !if(ps.has_vdst, vdst, ?);
217 let OutOperandList = (outs vdata_op:$vdst);
227 let AsmOperands = " $vdst, $vaddr"
236 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
296 (outs regClass:$vdst),
300 " $vdst, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
[all …]
H A DGCNHazardRecognizer.cpp898 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
906 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
912 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
918 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
958 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
1297 SDSTName = AMDGPU::OpName::vdst; in fixSMEMtoVectorWriteHazards()
1505 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVALUHazard()
1548 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVMEMHazard()
1831 TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg(); in fixWMMAHazards()
H A DSIInstrFormats.td341 bits<8> vdst;
350 let Inst{25-18} = vdst;
H A DSIInstrInfo.td2274 (outs DstRCDPP:$vdst)),
2283 (outs DstRCSDWA:$vdst)),
2290 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2302 string dst = "$vdst" # XorY;
2316 string dst = !if(HasDst, "$vdst"# !if(!gt(NumSrcArgs, 0), ",", ""), "");
2336 "$vdst"),
2365 "$vdst"),
2414 "$vdst"),
2443 "$vdst"), // VOP1/2
2681 field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
[all …]
/freebsd/crypto/openssl/providers/implementations/ciphers/
H A Dcipher_aes_gcm_siv.h28 int (*dup_ctx)(void *vdst, void *vsrc);
H A Dcipher_aes_gcm_siv_hw.c301 static int aes_gcm_siv_dup_ctx(void *vdst, void *vsrc) in aes_gcm_siv_dup_ctx() argument
303 PROV_AES_GCM_SIV_CTX *dst = (PROV_AES_GCM_SIV_CTX *)vdst; in aes_gcm_siv_dup_ctx()
/freebsd/sys/opencrypto/
H A Dcriov.c541 crypto_cursor_copydata(struct crypto_buffer_cursor *cc, int size, void *vdst) in crypto_cursor_copydata() argument
547 dst = vdst; in crypto_cursor_copydata()
636 void *vdst) in crypto_cursor_copydata_noadv() argument
641 crypto_cursor_copydata(&copy, size, vdst); in crypto_cursor_copydata_noadv()
H A Dcryptodev.h683 void *vdst);
685 void *vdst);
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td2781 class IntDSBVHStackRtn<LLVMType vdst, LLVMType data1> :
2783 [vdst, llvm_i32_ty], // %vdst, %addr
2793 def int_amdgcn_ds_bvh_stack_rtn : IntDSBVHStackRtn<vdst = llvm_i32_ty,
2871 def int_amdgcn_ds_bvh_stack_push4_pop1_rtn : IntDSBVHStackRtn<vdst = llvm_i32_ty,
2874 def int_amdgcn_ds_bvh_stack_push8_pop1_rtn : IntDSBVHStackRtn<vdst = llvm_i32_ty,
2877 def int_amdgcn_ds_bvh_stack_push8_pop2_rtn : IntDSBVHStackRtn<vdst = llvm_i64_ty,
3270 // llvm.amdgcn.mfma.*.* vdst, srcA, srcB, srcC, cbsz, abid, blgp
3359 // llvm.amdgcn.smfmac.?32.* vdst, srcA, srcB, srcC, index, cbsz, abid
3396 // llvm.amdgcn.cvt.f32.bf8 float vdst, int srcA, imm byte_sel [0..3]
3403 // llvm.amdgcn.cvt.f32.fp8 float vdst, int srcA, imm byte_sel [0..3]
[all …]
/freebsd/contrib/tcsh/
H A Dtc.os.c980 xmemmove(void *vdst, const void *vsrc, size_t len) in xmemmove() argument
983 char *dst = vdst; in xmemmove()
986 return vdst; in xmemmove()
998 return vdst; in xmemmove()

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