Lines Matching refs:vdst

47   (outs VINTRPDst:$vdst),
49   "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
50   [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
61     Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
66   //     Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
73   (outs VINTRPDst:$vdst),
76   "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
77   [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
84   (outs VINTRPDst:$vdst),
86   "v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
87   [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
123 def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
132 def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
162 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
166 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
171 // accidentally clobber inactive channels of $vdst.
172 let Constraints = "@earlyclobber $vdst" in {
173 def STRICT_WWM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
174 def STRICT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
235 def FPTRUNC_UPWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
237   [(set f16:$vdst, (SIfptrunc_round_upward f32:$src0))]>;
239 def FPTRUNC_DOWNWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
241   [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
247 def V_SET_INACTIVE_B32 : VPseudoInstSI <(outs VGPR_32:$vdst),
250 def V_SET_INACTIVE_B64 : VPseudoInstSI <(outs VReg_64:$vdst),
284   (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
285   [(set VReg_64:$vdst, (DivergentBinFrag<add> i64:$src0, i64:$src1))]
289   (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
290   [(set VReg_64:$vdst, (DivergentBinFrag<sub> i64:$src0, i64:$src1))]
756   (outs VGPR_32:$vdst),
762   (outs rc:$vdst),
764   let Constraints = "$src = $vdst";
797   (outs rc:$vdst), (ins rc:$vsrc, val_ty:$val, i32imm:$subreg)> {
798   let Constraints = "$vsrc = $vdst";
860   (outs rc:$vdst), (ins rc:$vsrc, VSrc_b32:$val, SSrc_b32:$idx, i32imm:$subreg)> {
861   let Constraints = "$vsrc = $vdst";
881   (outs VGPR_32:$vdst), (ins rc:$vsrc, SSrc_b32:$idx, i32imm:$subreg)> {
938 def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst),
946   let Constraints = "$vdst = $vdst_in";
4002   let OutOperandList = (outs type0:$vdst);
4008   let OutOperandList = (outs type0:$vdst);