Lines Matching refs:vdst
15 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
25 bits<8> vdst;
29 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
34 bits<8> vdst;
38 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
183 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
194 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
246 let Asm32 = " $vdst, $src0";
374 // Special case because there are no true output operands. Hack vdst
383 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
384 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
387 let OutsSDWA = (outs Src0RC32:$vdst);
393 let OutsDPP = (outs Src0RC32:$vdst);
401 let OutsVOP3DPP = (outs Src0RC64:$vdst);
412 let EmitDst = 1; // force vdst emission
539 let Outs32 = (outs VGPR_32:$vdst, VRegSrc_32:$vdst1);
541 let Asm32 = " $vdst, $src0";
546 let Constraints = "$vdst = $src1, $vdst1 = $src0";
579 let AsmSDWA = "$vdst, $src0_modifiers$clamp$omod $src0_sel"; // No dst_sel
711 let Constraints = "$vdst = $src1, $vdst1 = $src0";
723 let Asm32 = " $vdst, $src0";
765 bits<8> vdst;
768 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
793 bits<8> vdst;
796 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
1214 bits<8> vdst;
1217 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1343 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
1344 // indexing mode. vdst can't be treated as a def for codegen purposes,
1347 (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32, 0>.ret:$src0)>,
1348 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
1354 (outs getVALUDstForVT<i32>.ret:$vdst),
1356 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,