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Searched refs:mt76_rr (Results 1 – 25 of 64) sorted by relevance

123

/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dusb_mac.c104 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); in mt76x2u_mac_stop()
112 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_mac_stop()
120 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) && in mt76x2u_mac_stop()
121 !(mt76_rr(dev, 0x0a30) & 0x000000ff) && in mt76x2u_mac_stop()
122 !(mt76_rr(dev, 0x0a34) & 0xff00ff00)) in mt76x2u_mac_stop()
134 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) && in mt76x2u_mac_stop()
135 !mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2u_mac_stop()
152 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) && in mt76x2u_mac_stop()
153 !(mt76_rr(dev, 0x0a30) & 0xffffffff) && in mt76x2u_mac_stop()
154 !(mt76_rr(dev, 0x0a34) & 0xffffffff) && in mt76x2u_mac_stop()
[all …]
H A Dmac.c20 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); in mt76x2_mac_stop()
25 if ((mt76_rr(dev, MT_MAC_STATUS) & in mt76x2_mac_stop()
27 mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2_mac_stop()
H A Dphy.c18 mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_high_lna_gain()
28 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_agc_gain()
218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate()
302 val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; in mt76x2_phy_update_channel_gain()
347 mt76_rr(dev, MT_RX_STAT_1); in mt76x2_phy_update_channel_gain()
H A Dusb_init.c15 u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_init_dma()
118 val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i)); in mt76x2u_init_eeprom()
160 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); in mt76x2u_init_hardware()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dcoredump.c173 dump->last_msg_id = mt76_rr(dev, MT_FW_LAST_MSG_ID); in mt7915_coredump_fw_trace()
180 irq = mt76_rr(dev, base + 0x8); in mt7915_coredump_fw_trace()
185 sch = mt76_rr(dev, MT_FW_SCHED_INFO); in mt7915_coredump_fw_trace()
236 dump->call_stack[i] = mt76_rr(dev, 0x89050204 + idx * 4); in mt7915_coredump_fw_stack()
252 dump->taskq[0].read = mt76_rr(dev, MT_FW_TASK_QID1); in mt7915_coredump_fw_task()
253 dump->taskq[0].write = mt76_rr(dev, MT_FW_TASK_QID1 - 4); in mt7915_coredump_fw_task()
254 dump->taskq[1].read = mt76_rr(dev, MT_FW_TASK_QID2); in mt7915_coredump_fw_task()
255 dump->taskq[1].write = mt76_rr(dev, MT_FW_TASK_QID2 - 4); in mt7915_coredump_fw_task()
260 dump->taski[0].start = mt76_rr(dev, MT_FW_TASK_START); in mt7915_coredump_fw_task()
261 dump->taski[0].end = mt76_rr(dev, MT_FW_TASK_END); in mt7915_coredump_fw_task()
[all …]
H A Dmac.c148 msta->airtime_ac[i] = mt76_rr(dev, addr); in mt7915_mac_sta_poll()
149 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); in mt7915_mac_sta_poll()
192 val = mt76_rr(dev, addr); in mt7915_mac_sta_poll()
223 val = mt76_rr(dev, addr); in mt7915_mac_sta_poll()
1168 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); in mt7915_mac_reset_counters()
1169 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); in mt7915_mac_reset_counters()
1270 val = mt76_rr(dev, reg); in mt7915_phy_get_nf()
1739 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); in mt7915_mac_update_stats()
1744 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); in mt7915_mac_update_stats()
1747 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); in mt7915_mac_update_stats()
[all …]
H A Ddebugfs.c166 mt76_rr(dev, MT_SWDEF_SER_STATS)); in mt7915_sys_recovery_get()
169 mt76_rr(dev, MT_SWDEF_PLE_STATS)); in mt7915_sys_recovery_get()
172 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); in mt7915_sys_recovery_get()
175 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); in mt7915_sys_recovery_get()
178 mt76_rr(dev, MT_SWDEF_PSE_STATS)); in mt7915_sys_recovery_get()
181 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); in mt7915_sys_recovery_get()
184 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); in mt7915_sys_recovery_get()
187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); in mt7915_sys_recovery_get()
190 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); in mt7915_sys_recovery_get()
193 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); in mt7915_sys_recovery_get()
[all …]
H A Dsoc.c48 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), in mt76_wmac_spi_read()
58 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), in mt76_wmac_spi_read()
64 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); in mt76_wmac_spi_read()
75 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), in mt76_wmac_spi_write()
85 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), in mt76_wmac_spi_write()
153 read_poll_timeout(mt76_rr, cur, in mt76_wmac_spi_lock()
280 return read_poll_timeout(mt76_rr, cur, (cur == con_infra_version), in mt798x_wmac_coninfra_check()
325 mt76_rr(dev, MT_CONN_INFRA_EFUSE); in mt798x_wmac_coninfra_setup()
906 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), in mt7986_wmac_clock_enable()
914 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), in mt7986_wmac_clock_enable()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_mac.c98 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0)); in mt792x_mac_update_mib_stats()
99 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0)); in mt792x_mac_update_mib_stats()
100 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0)); in mt792x_mac_update_mib_stats()
102 val = mt76_rr(dev, MT_MIB_SDR32(0)); in mt792x_mac_update_mib_stats()
106 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0)); in mt792x_mac_update_mib_stats()
110 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0)); in mt792x_mac_update_mib_stats()
116 mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0)); in mt792x_mac_update_mib_stats()
117 mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0)); in mt792x_mac_update_mib_stats()
118 mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0)); in mt792x_mac_update_mib_stats()
119 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0)); in mt792x_mac_update_mib_stats()
[all …]
H A Dmt76x02_mac.c15 mt76_rr(dev, MT_RX_STAT_0); in mt76x02_mac_reset_counters()
16 mt76_rr(dev, MT_RX_STAT_1); in mt76x02_mac_reset_counters()
17 mt76_rr(dev, MT_RX_STAT_2); in mt76x02_mac_reset_counters()
18 mt76_rr(dev, MT_TX_STA_0); in mt76x02_mac_reset_counters()
19 mt76_rr(dev, MT_TX_STA_1); in mt76x02_mac_reset_counters()
20 mt76_rr(dev, MT_TX_STA_2); in mt76x02_mac_reset_counters()
23 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt76x02_mac_reset_counters()
26 mt76_rr(dev, MT_TX_STAT_FIFO); in mt76x02_mac_reset_counters()
69 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); in mt76x02_mac_shared_key_setup()
90 iv = mt76_rr(dev, MT_WCID_IV(idx)); in mt76x02_mac_wcid_sync_pn()
[all …]
H A Dmt76x02_dfs.c232 current_ts = mt76_rr(dev, MT_PBF_LIFE_TIMER); in mt76x02_dfs_check_chirp()
257 pulse->period = mt76_rr(dev, MT_BBP(DFS, 19)); in mt76x02_dfs_get_hw_pulse()
260 pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20)); in mt76x02_dfs_get_hw_pulse()
261 pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23)); in mt76x02_dfs_get_hw_pulse()
264 pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22)); in mt76x02_dfs_get_hw_pulse()
376 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
381 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
383 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
641 engine_mask = mt76_rr(dev, MT_BBP(DFS, 1)); in mt76x02_dfs_tasklet()
799 agc_r8 = mt76_rr(dev, MT_BBP(AGC, 8)); in mt76x02_phy_dfs_adjust_agc()
[all …]
H A Dmt76x02_eeprom.c18 val = mt76_rr(dev, MT_EFUSE_CTRL); in mt76x02_efuse_read()
31 val = mt76_rr(dev, MT_EFUSE_CTRL); in mt76x02_efuse_read()
38 val = mt76_rr(dev, MT_EFUSE_DATA(i)); in mt76x02_efuse_read()
H A Dmt76x02_phy.c16 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath()
30 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath()
176 mt76_rr(dev, MT_RX_STAT_1)); in mt76x02_phy_adjust_vga_gain()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Ddebugfs.c169 mt76_rr(dev, MT_SWDEF_SER_STATS)); in mt7996_sys_recovery_get()
172 mt76_rr(dev, MT_SWDEF_PLE_STATS)); in mt7996_sys_recovery_get()
175 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); in mt7996_sys_recovery_get()
178 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); in mt7996_sys_recovery_get()
181 mt76_rr(dev, MT_SWDEF_PSE_STATS)); in mt7996_sys_recovery_get()
184 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); in mt7996_sys_recovery_get()
187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); in mt7996_sys_recovery_get()
190 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); in mt7996_sys_recovery_get()
193 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS)); in mt7996_sys_recovery_get()
196 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); in mt7996_sys_recovery_get()
[all …]
H A Dmac.c145 msta->airtime_ac[i] = mt76_rr(dev, addr); in mt7996_mac_sta_poll()
146 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); in mt7996_mac_sta_poll()
206 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll()
209 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll()
225 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll()
1436 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); in mt7996_mac_reset_counters()
1504 val = mt76_rr(dev, reg); in mt7996_phy_get_nf()
2017 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); in mt7996_mac_update_stats()
2020 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); in mt7996_mac_update_stats()
2023 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); in mt7996_mac_update_stats()
[all …]
H A Dcoredump.c106 count = mt76_rr(dev, MT_FW_ASSERT_CNT); in mt7996_coredump_fw_state()
131 dump->pc_stack[0] = mt76_rr(dev, MT_CONN_DBG_CTL_PC_LOG); in mt7996_coredump_fw_stack()
144 mt76_rr(dev, MT_MCU_WM_EXCP_PC_LOG + idx * 4); in mt7996_coredump_fw_stack()
152 mt76_rr(dev, MT_MCU_WM_EXCP_LR_LOG + idx * 4); in mt7996_coredump_fw_stack()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Deeprom.c13 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7603_efuse_read()
25 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7603_efuse_read()
33 val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); in mt7603_efuse_read()
48 if (mt76_rr(dev, base + MT_EFUSE_BASE_CTRL) & MT_EFUSE_BASE_CTRL_EMPTY) in mt7603_efuse_init()
153 return mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4); in is_mt7688()
H A Dsoc.c34 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt76_wmac_probe()
35 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt76_wmac_probe()
H A Dmac.c40 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt7603_mac_reset_counters()
173 u32 val = mt76_rr(dev, addr + 3 * 4); in mt7603_wtbl_set_skip_tx()
221 WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY); in mt7603_filter_tx()
344 val = mt76_rr(dev, addr + 2 * 4); in mt7603_wtbl_update_cap()
360 val = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_update_cap()
441 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); in mt7603_mac_sta_poll()
742 u32 w9 = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_set_rates()
846 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; in mt7603_wtbl_set_rates()
1514 val = mt76_rr(dev, MT_WPDMA_DEBUG); in mt7603_dma_debug()
1528 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) in mt7603_rx_dma_busy()
[all …]
H A Dcore.c18 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7603_irq_handler()
29 u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3)); in mt7603_irq_handler()
H A Dpci.c43 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt76pci_probe()
44 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt76pci_probe()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmmio.c94 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7615_irq_tasklet()
118 mcu_int = mt76_rr(dev, MT_MCU2HOST_INT_STATUS); in mt7615_irq_tasklet()
122 mcu_int = mt76_rr(dev, MT_MCU_CMD); in mt7615_irq_tasklet()
206 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt7615_mmio_probe()
207 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt7615_mmio_probe()
H A Deeprom.c21 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7615_efuse_read()
32 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7615_efuse_read()
40 val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); in mt7615_efuse_read()
56 val = mt76_rr(dev, base + MT_EFUSE_BASE_CTRL); in mt7615_efuse_init()
166 val = mt76_rr(dev, MT_TOP_STRAP_STA); in mt7615_eeprom_parse_hw_cap()
H A Dmac.c119 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); in mt7615_mac_reset_counters()
120 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); in mt7615_mac_reset_counters()
127 mt76_rr(dev, MT_MIB_SDR9(0)); in mt7615_mac_reset_counters()
128 mt76_rr(dev, MT_MIB_SDR9(1)); in mt7615_mac_reset_counters()
130 mt76_rr(dev, MT_MIB_SDR36(0)); in mt7615_mac_reset_counters()
131 mt76_rr(dev, MT_MIB_SDR36(1)); in mt7615_mac_reset_counters()
133 mt76_rr(dev, MT_MIB_SDR37(0)); in mt7615_mac_reset_counters()
134 mt76_rr(dev, MT_MIB_SDR37(1)); in mt7615_mac_reset_counters()
932 msta->airtime_ac[i] = mt76_rr(dev, addr); in mt7615_mac_sta_poll()
933 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); in mt7615_mac_sta_poll()
[all …]
H A Ddebugfs.c23 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7615_reg_get()
286 range = mt76_rr(dev, reg); in mt7615_ampdu_stat_read_phy()
290 range = mt76_rr(dev, reg + 4); in mt7615_ampdu_stat_read_phy()
370 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, wmm_idx)); in mt7615_queues_acq()
461 put_unaligned_le32(mt76_rr(dev, MT_WF_RMAC_MAR0), addr); in mt7615_ext_mac_addr_read()
462 put_unaligned_le16((mt76_rr(dev, MT_WF_RMAC_MAR1) & in mt7615_ext_mac_addr_read()

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