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Searched refs:hw_params (Results 1 – 25 of 58) sorted by relevance

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/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal.h35 #define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr
47 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)
49 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
51 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
53 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
62 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb
63 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb
64 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id
65 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc
67 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb
[all …]
H A Ddp.c141 grp_mask = &ab->hw_params.ring_mask->rx_wbm_rel[0]; in ath11k_dp_srng_calculate_msi_group()
144 grp_mask = &ab->hw_params.ring_mask->tx[0]; in ath11k_dp_srng_calculate_msi_group()
148 grp_mask = &ab->hw_params.ring_mask->rx_err[0]; in ath11k_dp_srng_calculate_msi_group()
151 grp_mask = &ab->hw_params.ring_mask->rx[0]; in ath11k_dp_srng_calculate_msi_group()
154 grp_mask = &ab->hw_params.ring_mask->reo_status[0]; in ath11k_dp_srng_calculate_msi_group()
158 grp_mask = &ab->hw_params.ring_mask->rx_mon_status[0]; in ath11k_dp_srng_calculate_msi_group()
161 grp_mask = &ab->hw_params.ring_mask->rxdma2host[0]; in ath11k_dp_srng_calculate_msi_group()
164 grp_mask = &ab->hw_params.ring_mask->host2rxdma[0]; in ath11k_dp_srng_calculate_msi_group()
242 if (ab->hw_params.alloc_cacheable_memory) { in ath11k_dp_srng_setup()
344 if (!ab->hw_params.supports_shadow_regs) in ath11k_dp_stop_shadow_timers()
[all …]
H A Dahb.c212 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_ahb_kill_tasklets()
274 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr; in ath11k_ahb_ce_irq_enable()
281 ce_attr = &ab->hw_params.host_ce_config[ce_id]; in ath11k_ahb_ce_irq_enable()
295 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr; in ath11k_ahb_ce_irq_disable()
302 ce_attr = &ab->hw_params.host_ce_config[ce_id]; in ath11k_ahb_ce_irq_disable()
318 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_ahb_sync_ce_irqs()
346 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_ahb_ce_irqs_enable()
357 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_ahb_ce_irqs_disable()
426 cfg->tgt_ce_len = ab->hw_params.target_ce_count; in ath11k_ahb_init_qmi_ce_config()
427 cfg->tgt_ce = ab->hw_params.target_ce_config; in ath11k_ahb_init_qmi_ce_config()
[all …]
H A Dce.c263 if (!ab->hw_params.supports_shadow_regs) in ath11k_ce_stop_shadow_timers()
266 for (i = 0; i < ab->hw_params.ce_count; i++) in ath11k_ce_stop_shadow_timers()
514 if ((!pipe->send_cb) || ab->hw_params.credit_flow) { in ath11k_ce_tx_process_cb()
566 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags)) in ath11k_ce_init_ring()
571 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags)) in ath11k_ce_init_ring()
575 params.max_buffer_len = ab->hw_params.host_ce_config[ce_id].src_sz_max; in ath11k_ce_init_ring()
576 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { in ath11k_ce_init_ring()
583 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { in ath11k_ce_init_ring()
604 if (ab->hw_params.supports_shadow_regs && in ath11k_ce_init_ring()
653 const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id]; in ath11k_ce_alloc_pipe()
[all …]
H A Dpcic.c292 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_get_ce_msi_idx()
323 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_free_irq()
368 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_ce_irqs_disable()
380 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_sync_ce_irqs()
582 if (ab->hw_params.ring_mask->tx[i] || in ath11k_pcic_ext_irq_config()
583 ab->hw_params.ring_mask->rx[i] || in ath11k_pcic_ext_irq_config()
584 ab->hw_params.ring_mask->rx_err[i] || in ath11k_pcic_ext_irq_config()
585 ab->hw_params.ring_mask->rx_wbm_rel[i] || in ath11k_pcic_ext_irq_config()
586 ab->hw_params.ring_mask->reo_status[i] || in ath11k_pcic_ext_irq_config()
587 ab->hw_params.ring_mask->rxdma2host[i] || in ath11k_pcic_ext_irq_config()
[all …]
H A Dpci.h39 (ab->hw_params.regs->pcie_qserdes_sysclk_en_sel)
43 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base)
46 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)
49 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)
H A Ddp_rx.c26 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); in ath11k_dp_rx_h_80211_hdr()
33 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) in ath11k_dp_rx_h_mpdu_start_enctype()
36 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); in ath11k_dp_rx_h_mpdu_start_enctype()
42 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); in ath11k_dp_rx_h_msdu_start_decap_type()
49 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc); in ath11k_dp_rx_h_msdu_start_ldpc_support()
56 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); in ath11k_dp_rx_h_msdu_start_mesh_ctl_present()
63 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); in ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid()
69 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc); in ath11k_dp_rx_h_mpdu_start_fc_valid()
77 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); in ath11k_dp_rx_h_mpdu_start_more_frags()
86 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); in ath11k_dp_rx_h_mpdu_start_frag_no()
[all …]
H A Ddp_tx.c118 ring_selector = ab->hw_params.hw_ops->get_ring_selector(skb); in ath11k_dp_tx()
123 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; in ath11k_dp_tx()
124 ti.rbm_id = ab->hw_params.hal_params->tcl2wbm_rbm_map[ti.ring_id].rbm_id; in ath11k_dp_tx()
136 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1) || in ath11k_dp_tx()
137 !ab->hw_params.tcl_ring_retry) { in ath11k_dp_tx()
254 if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) && in ath11k_dp_tx()
255 ab->hw_params.tcl_ring_retry && ab->hw_params.max_tx_ring > 1) { in ath11k_dp_tx()
613 ab->hw_params.single_pdev_only) { in ath11k_dp_tx_complete_msdu()
838 if (!ab->hw_params.rx_mac_buf_ring) { in ath11k_dp_tx_get_ring_id_type()
1054 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { in ath11k_dp_tx_htt_h2t_ppdu_stats_req()
[all …]
H A Dspectral.c16 #define ATH11K_SPECTRAL_MAX_IB_BINS(x) ((x)->hw_params.spectral.max_fft_bins >> 1)
452 val > ar->ab->hw_params.spectral.max_fft_bins) in ath11k_write_file_spectral_bins()
595 if (!ab->hw_params.spectral.fft_sz) { in ath11k_spectral_process_fft()
605 bin_len = tlv_len - ab->hw_params.spectral.fft_hdr_len; in ath11k_spectral_process_fft()
613 bin_sz = ab->hw_params.spectral.fft_sz + ab->hw_params.spectral.fft_pad_sz; in ath11k_spectral_process_fft()
625 check_length = sizeof(*fft_report) + (num_bins * ab->hw_params.spectral.fft_sz); in ath11k_spectral_process_fft()
647 if (ab->hw_params.spectral.fragment_160mhz) { in ath11k_spectral_process_fft()
689 ab->hw_params.spectral.fft_sz); in ath11k_spectral_process_fft()
774 ab->hw_params.spectral.summary_pad_sz; in ath11k_spectral_process_data()
1002 if (!ab->hw_params.spectral.fft_sz) in ath11k_spectral_init()
H A Dqmi.c1738 if (ab->hw_params.m3_fw_support) { in ath11k_qmi_host_cap_send()
1753 if (ab->hw_params.internal_sleep_clock) { in ath11k_qmi_host_cap_send()
1767 if (ab->hw_params.global_reset) in ath11k_qmi_host_cap_send()
1838 if (!ab->hw_params.fixed_fw_mem) { in ath11k_qmi_fw_ind_register_send()
1902 if (!(ab->hw_params.fixed_mem_region || in ath11k_qmi_respond_fw_mem_request()
1972 if ((ab->hw_params.fixed_mem_region || in ath11k_qmi_free_target_mem_chunk()
2090 ab->qmi.target_mem[idx].paddr = ab->hw_params.bdf_addr; in ath11k_qmi_assign_target_mem_chunk()
2145 if (!ab->hw_params.hybrid_bus_type) in ath11k_qmi_request_device_info()
2336 if (ab->hw_params.fixed_bdf_addr) { in ath11k_qmi_load_file_target_mem()
2337 bdf_addr = ioremap(ab->hw_params.bdf_addr, ab->hw_params.fw.board_size); in ath11k_qmi_load_file_target_mem()
[all …]
H A Dcore.c718 WARN_ON(!ab->hw_params.single_pdev_only); in ath11k_core_get_single_pdev()
775 return ab->hw_params.coldboot_cal_ftm; in ath11k_core_coldboot_cal_support()
778 return ab->hw_params.coldboot_cal_mm; in ath11k_core_coldboot_cal_support()
787 if (!ab->hw_params.supports_suspend) in ath11k_core_suspend()
846 if (!ab->hw_params.supports_suspend) in ath11k_core_resume()
1371 ab->hw_params.fw.dir); in ath11k_core_fetch_bdf()
1417 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); in ath11k_core_fetch_regdb()
1623 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { in ath11k_core_start()
2009 const struct ath11k_hw_params *hw_params = NULL; in ath11k_init_hw_params() local
2013 hw_params = &ath11k_hw_params[i]; in ath11k_init_hw_params()
[all …]
H A Dhtc.c83 bool credit_flow_enabled = (ab->hw_params.credit_flow && in ath11k_htc_send()
210 if (ab->hw_params.credit_flow) { in ath11k_htc_process_trailer()
538 for (i = 0; i < ab->hw_params.ce_count; i++) in ath11k_htc_wait_target()
587 if (ab->hw_params.supports_shadow_regs) in ath11k_htc_wait_target()
653 if (!ab->hw_params.credit_flow) { in ath11k_htc_connect_service()
783 if (ab->hw_params.credit_flow) in ath11k_htc_start()
822 htc->wmi_ep_count = ab->hw_params.max_radios; in ath11k_htc_init()
H A Dpci.c62 if (!ab->hw_params.static_window_map) in ath11k_pci_get_window_start()
393 if (ab->hw_params.fix_l1ss) in ath11k_pci_sw_reset()
407 cfg->tgt_ce = ab->hw_params.target_ce_config; in ath11k_pci_init_qmi_ce_config()
408 cfg->tgt_ce_len = ab->hw_params.target_ce_count; in ath11k_pci_init_qmi_ce_config()
410 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; in ath11k_pci_init_qmi_ce_config()
411 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; in ath11k_pci_init_qmi_ce_config()
412 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; in ath11k_pci_init_qmi_ce_config()
652 if (ab->hw_params.static_window_map) in ath11k_pci_power_up()
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal.h62 #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id)
64 ((ab)->hw_params->regs->hal_tcl1_ring_misc)
66 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb)
68 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb)
70 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0)
72 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1)
74 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb)
76 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb)
78 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data)
81 ((ab)->hw_params->regs->hal_tcl_ring_base_lsb)
[all …]
H A Ddp.c134 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0]; in ath12k_dp_srng_calculate_msi_group()
137 grp_mask = &ab->hw_params->ring_mask->tx[0]; in ath12k_dp_srng_calculate_msi_group()
141 grp_mask = &ab->hw_params->ring_mask->rx_err[0]; in ath12k_dp_srng_calculate_msi_group()
144 grp_mask = &ab->hw_params->ring_mask->rx[0]; in ath12k_dp_srng_calculate_msi_group()
147 grp_mask = &ab->hw_params->ring_mask->reo_status[0]; in ath12k_dp_srng_calculate_msi_group()
151 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0]; in ath12k_dp_srng_calculate_msi_group()
154 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0]; in ath12k_dp_srng_calculate_msi_group()
157 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0]; in ath12k_dp_srng_calculate_msi_group()
269 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) { in ath12k_dp_srng_setup()
420 u32 num_tcl_banks = ab->hw_params->num_tcl_banks; in ath12k_dp_init_bank_profiles()
[all …]
H A Dce.c502 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags)) in ath12k_ce_init_ring()
507 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags)) in ath12k_ce_init_ring()
511 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max; in ath12k_ce_init_ring()
512 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { in ath12k_ce_init_ring()
519 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { in ath12k_ce_init_ring()
583 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id]; in ath12k_ce_alloc_pipe()
746 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) { in ath12k_ce_cleanup_pipes()
763 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_ce_rx_post_buf()
791 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_ce_shadow_config()
792 if (ab->hw_params->host_ce_config[i].src_nentries) in ath12k_ce_shadow_config()
[all …]
H A Ddp_rx.c26 if (!ab->hw_params->hal_ops->rx_desc_encrypt_valid(desc)) in ath12k_dp_rx_h_enctype()
29 return ab->hw_params->hal_ops->rx_desc_get_encrypt_type(desc); in ath12k_dp_rx_h_enctype()
35 return ab->hw_params->hal_ops->rx_desc_get_decap_type(desc); in ath12k_dp_rx_h_decap_type()
41 return ab->hw_params->hal_ops->rx_desc_get_mesh_ctl(desc); in ath12k_dp_rx_h_mesh_ctl_present()
47 return ab->hw_params->hal_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); in ath12k_dp_rx_h_seq_ctrl_valid()
53 return ab->hw_params->hal_ops->rx_desc_get_mpdu_fc_valid(desc); in ath12k_dp_rx_h_fc_valid()
61 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params->hal_desc_sz); in ath12k_dp_rx_h_more_frags()
70 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params->hal_desc_sz); in ath12k_dp_rx_h_frag_no()
77 return ab->hw_params->hal_ops->rx_desc_get_mpdu_start_seq_no(desc); in ath12k_dp_rx_h_seq_no()
83 return ab->hw_params->hal_ops->dp_rx_h_msdu_done(desc); in ath12k_dp_rx_h_msdu_done()
[all …]
H A Dpci.c358 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_free_irq()
388 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_disable()
400 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_sync_ce_irqs()
534 if (ab->hw_params->ring_mask->tx[i] || in ath12k_pci_ext_irq_config()
535 ab->hw_params->ring_mask->rx[i] || in ath12k_pci_ext_irq_config()
536 ab->hw_params->ring_mask->rx_err[i] || in ath12k_pci_ext_irq_config()
537 ab->hw_params->ring_mask->rx_wbm_rel[i] || in ath12k_pci_ext_irq_config()
538 ab->hw_params->ring_mask->reo_status[i] || in ath12k_pci_ext_irq_config()
539 ab->hw_params->ring_mask->host2rxdma[i] || in ath12k_pci_ext_irq_config()
540 ab->hw_params->ring_mask->rx_mon_dest[i]) { in ath12k_pci_ext_irq_config()
[all …]
H A Dpci.h39 ((ab)->hw_params->regs->pcie_qserdes_sysclk_en_sel)
43 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base)
46 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0x4)
49 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0xc)
H A Dhw.c1027 const struct ath12k_hw_params *hw_params = NULL; in ath12k_hw_init() local
1031 hw_params = &ath12k_hw_params[i]; in ath12k_hw_init()
1033 if (hw_params->hw_rev == ab->hw_rev) in ath12k_hw_init()
1042 ab->hw_params = hw_params; in ath12k_hw_init()
1044 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name); in ath12k_hw_init()
H A Ddp_tx.c170 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); in ath12k_dp_tx()
174 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; in ath12k_dp_tx()
177 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; in ath12k_dp_tx()
313 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && in ath12k_dp_tx()
314 ab->hw_params->tcl_ring_retry) { in ath12k_dp_tx()
354 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); in ath12k_dp_tx_free_txbuf()
617 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); in ath12k_dp_tx_completion_handler()
641 if (!ab->hw_params->rx_mac_buf_ring) { in ath12k_dp_tx_get_ring_id_type()
863 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { in ath12k_dp_tx_htt_h2t_ppdu_stats_req()
1076 if (ab->hw_params->rxdma1_enable) { in ath12k_dp_tx_htt_rx_monitor_mode_ring_config()
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dcore.c810 bool mtu_workaround = ar->hw_params.credit_size_workaround; in ath10k_init_sdio()
955 u32 board_data_size = ar->hw_params.fw.board_size; in ath10k_push_board_ext_data()
956 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; in ath10k_push_board_ext_data()
1006 address = ar->hw_params.patch_load_addr; in ath10k_core_get_board_id_from_otp()
1183 address = ar->hw_params.patch_load_addr; in ath10k_download_fw()
1203 if (ar->hw_params.fw_diag_ce_download) { in ath10k_download_fw()
1299 if (!ar->hw_params.fw.board) { in ath10k_core_fetch_board_data_api_1()
1308 ar->hw_params.fw.dir, in ath10k_core_fetch_board_data_api_1()
1312 ar->hw_params.fw.dir, in ath10k_core_fetch_board_data_api_1()
1313 ar->hw_params.fw.board); in ath10k_core_fetch_board_data_api_1()
[all …]
H A Dhtt_rx.c134 struct ath10k_hw_params *hw = &htt->ar->hw_params; in __ath10k_htt_rx_ring_fill_n()
354 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_amsdu_pop()
506 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_handle_amsdu_mon_32()
583 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_handle_amsdu_mon_64()
668 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_pop_paddr32_list()
733 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_pop_paddr64_list()
810 htt->rx_ring.fill_level = ar->hw_params.rx_ring_fill_level; in ath10k_htt_rx_alloc()
992 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_h_rates()
1123 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_h_peer_channel()
1239 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_rx_h_signal()
[all …]
H A Dhtt_tx.c176 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) in ath10k_htt_tx_mgmt_inc_pending()
180 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) in ath10k_htt_tx_mgmt_inc_pending()
192 if (!htt->ar->hw_params.max_probe_resp_desc_thres) in ath10k_htt_tx_mgmt_dec_pending()
313 if (!ar->hw_params.continuous_frag_desc) in ath10k_htt_tx_alloc_cont_frag_desc_32()
353 if (!ar->hw_params.continuous_frag_desc) in ath10k_htt_tx_alloc_cont_frag_desc_64()
684 if (!ar->hw_params.continuous_frag_desc) in ath10k_htt_send_frag_desc_bank_cfg_32()
746 if (!ar->hw_params.continuous_frag_desc) in ath10k_htt_send_frag_desc_bank_cfg_64()
818 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_send_rx_ring_cfg_32()
891 struct ath10k_hw_params *hw = &ar->hw_params; in ath10k_htt_send_rx_ring_cfg_64()
1456 if (ar->hw_params.continuous_frag_desc) { in ath10k_htt_tx_32()
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H A Dce.c147 if (ar->hw_params.rri_on_ddr && in ath10k_ce_src_ring_read_index_get()
260 if (ar->hw_params.rri_on_ddr && in ath10k_ce_dest_ring_read_index_get()
503 if (ar->hw_params.rri_on_ddr) in _ath10k_ce_send_nolock_64()
546 if (ar->hw_params.shadow_reg_support) in _ath10k_ce_send_nolock_64()
1030 if (ar->hw_params.rri_on_ddr) in _ath10k_ce_completed_send_next_nolock()
1083 if (ar->hw_params.rri_on_ddr) in _ath10k_ce_completed_send_next_nolock_64()
1366 if (ar->hw_params.target_64bit) in ath10k_ce_init_src_ring()
1407 if (ar->hw_params.target_64bit) in ath10k_ce_init_dest_ring()
1492 if (ar->hw_params.shadow_reg_support) { in ath10k_ce_alloc_src_ring()
1549 if (ar->hw_params.shadow_reg_support) { in ath10k_ce_alloc_src_ring_64()
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