1dd4f32aeSBjoern A. Zeeb // SPDX-License-Identifier: BSD-3-Clause-Clear
2dd4f32aeSBjoern A. Zeeb /*
3dd4f32aeSBjoern A. Zeeb * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*28348caeSBjoern A. Zeeb * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5dd4f32aeSBjoern A. Zeeb */
6dd4f32aeSBjoern A. Zeeb
7dd4f32aeSBjoern A. Zeeb #if defined(__FreeBSD__)
8dd4f32aeSBjoern A. Zeeb #define LINUXKPI_PARAM_PREFIX ath11k_core_
9dd4f32aeSBjoern A. Zeeb #endif
10dd4f32aeSBjoern A. Zeeb
11dd4f32aeSBjoern A. Zeeb #include <linux/module.h>
12dd4f32aeSBjoern A. Zeeb #include <linux/slab.h>
13dd4f32aeSBjoern A. Zeeb #include <linux/remoteproc.h>
14dd4f32aeSBjoern A. Zeeb #include <linux/firmware.h>
15dd4f32aeSBjoern A. Zeeb #if defined(CONFIG_OF)
16dd4f32aeSBjoern A. Zeeb #include <linux/of.h>
17dd4f32aeSBjoern A. Zeeb #endif
18dd4f32aeSBjoern A. Zeeb #if defined(__FreeBSD__)
19dd4f32aeSBjoern A. Zeeb #include <linux/delay.h>
20dd4f32aeSBjoern A. Zeeb #endif
21*28348caeSBjoern A. Zeeb
22dd4f32aeSBjoern A. Zeeb #include "core.h"
23dd4f32aeSBjoern A. Zeeb #include "dp_tx.h"
24dd4f32aeSBjoern A. Zeeb #include "dp_rx.h"
25dd4f32aeSBjoern A. Zeeb #include "debug.h"
26dd4f32aeSBjoern A. Zeeb #include "hif.h"
27dd4f32aeSBjoern A. Zeeb #include "wow.h"
28dd4f32aeSBjoern A. Zeeb
29dd4f32aeSBjoern A. Zeeb unsigned int ath11k_debug_mask;
30dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_debug_mask);
31dd4f32aeSBjoern A. Zeeb module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
32dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(debug_mask, "Debugging mask");
33dd4f32aeSBjoern A. Zeeb
34dd4f32aeSBjoern A. Zeeb static unsigned int ath11k_crypto_mode;
35dd4f32aeSBjoern A. Zeeb module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
36dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
37dd4f32aeSBjoern A. Zeeb
38dd4f32aeSBjoern A. Zeeb /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
39dd4f32aeSBjoern A. Zeeb unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
40dd4f32aeSBjoern A. Zeeb module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
41dd4f32aeSBjoern A. Zeeb MODULE_PARM_DESC(frame_mode,
42dd4f32aeSBjoern A. Zeeb "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
43dd4f32aeSBjoern A. Zeeb
44*28348caeSBjoern A. Zeeb bool ath11k_ftm_mode;
45*28348caeSBjoern A. Zeeb module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
46*28348caeSBjoern A. Zeeb MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
47*28348caeSBjoern A. Zeeb
48dd4f32aeSBjoern A. Zeeb static const struct ath11k_hw_params ath11k_hw_params[] = {
49dd4f32aeSBjoern A. Zeeb {
50dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_IPQ8074,
51dd4f32aeSBjoern A. Zeeb .name = "ipq8074 hw2.0",
52dd4f32aeSBjoern A. Zeeb .fw = {
53dd4f32aeSBjoern A. Zeeb .dir = "IPQ8074/hw2.0",
54dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
55dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
56dd4f32aeSBjoern A. Zeeb },
57dd4f32aeSBjoern A. Zeeb .max_radios = 3,
58dd4f32aeSBjoern A. Zeeb .bdf_addr = 0x4B0C0000,
59dd4f32aeSBjoern A. Zeeb .hw_ops = &ipq8074_ops,
60dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_ipq8074,
61dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = false,
62dd4f32aeSBjoern A. Zeeb .regs = &ipq8074_regs,
63dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
64dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_ipq8074,
65dd4f32aeSBjoern A. Zeeb .ce_count = 12,
66dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
67dd4f32aeSBjoern A. Zeeb .target_ce_count = 11,
68dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
69dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 21,
70*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
71dd4f32aeSBjoern A. Zeeb .single_pdev_only = false,
72dd4f32aeSBjoern A. Zeeb .rxdma1_enable = true,
73dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 1,
74dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = false,
75dd4f32aeSBjoern A. Zeeb .vdev_start_delay = false,
76dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = true,
77dd4f32aeSBjoern A. Zeeb
78dd4f32aeSBjoern A. Zeeb .spectral = {
79dd4f32aeSBjoern A. Zeeb .fft_sz = 2,
80dd4f32aeSBjoern A. Zeeb /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
81dd4f32aeSBjoern A. Zeeb * so added pad size as 2 bytes to compensate the BIN size
82dd4f32aeSBjoern A. Zeeb */
83dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 2,
84dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 0,
85dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 16,
86dd4f32aeSBjoern A. Zeeb .max_fft_bins = 512,
87*28348caeSBjoern A. Zeeb .fragment_160mhz = true,
88dd4f32aeSBjoern A. Zeeb },
89dd4f32aeSBjoern A. Zeeb
90dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
91dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP) |
92dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_MESH_POINT),
93dd4f32aeSBjoern A. Zeeb .supports_monitor = true,
94dd4f32aeSBjoern A. Zeeb .full_monitor_mode = false,
95dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = false,
96dd4f32aeSBjoern A. Zeeb .idle_ps = false,
97dd4f32aeSBjoern A. Zeeb .supports_sta_ps = false,
98*28348caeSBjoern A. Zeeb .coldboot_cal_mm = true,
99*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = true,
100*28348caeSBjoern A. Zeeb .cbcal_restart_fw = true,
101dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 0,
102dd4f32aeSBjoern A. Zeeb .num_vdevs = 16 + 1,
103dd4f32aeSBjoern A. Zeeb .num_peers = 512,
104dd4f32aeSBjoern A. Zeeb .supports_suspend = false,
105dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
106dd4f32aeSBjoern A. Zeeb .supports_regdb = false,
107dd4f32aeSBjoern A. Zeeb .fix_l1ss = true,
108dd4f32aeSBjoern A. Zeeb .credit_flow = false,
109dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX,
110dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_ipq8074,
111dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
112dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = true,
113dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = false,
114dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = false,
115*28348caeSBjoern A. Zeeb .current_cc_support = false,
116*28348caeSBjoern A. Zeeb .dbr_debug_support = true,
117*28348caeSBjoern A. Zeeb .global_reset = false,
118*28348caeSBjoern A. Zeeb .bios_sar_capa = NULL,
119*28348caeSBjoern A. Zeeb .m3_fw_support = false,
120*28348caeSBjoern A. Zeeb .fixed_bdf_addr = true,
121*28348caeSBjoern A. Zeeb .fixed_mem_region = true,
122*28348caeSBjoern A. Zeeb .static_window_map = false,
123*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
124*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
125*28348caeSBjoern A. Zeeb .support_off_channel_tx = false,
126*28348caeSBjoern A. Zeeb .supports_multi_bssid = false,
127*28348caeSBjoern A. Zeeb
128*28348caeSBjoern A. Zeeb .sram_dump = {},
129*28348caeSBjoern A. Zeeb
130*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
131*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
132*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
133dd4f32aeSBjoern A. Zeeb },
134dd4f32aeSBjoern A. Zeeb {
135dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_IPQ6018_HW10,
136dd4f32aeSBjoern A. Zeeb .name = "ipq6018 hw1.0",
137dd4f32aeSBjoern A. Zeeb .fw = {
138dd4f32aeSBjoern A. Zeeb .dir = "IPQ6018/hw1.0",
139dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
140dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
141dd4f32aeSBjoern A. Zeeb },
142dd4f32aeSBjoern A. Zeeb .max_radios = 2,
143dd4f32aeSBjoern A. Zeeb .bdf_addr = 0x4ABC0000,
144dd4f32aeSBjoern A. Zeeb .hw_ops = &ipq6018_ops,
145dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_ipq8074,
146dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = false,
147dd4f32aeSBjoern A. Zeeb .regs = &ipq8074_regs,
148dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
149dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_ipq8074,
150dd4f32aeSBjoern A. Zeeb .ce_count = 12,
151dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
152dd4f32aeSBjoern A. Zeeb .target_ce_count = 11,
153dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
154dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 19,
155*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
156dd4f32aeSBjoern A. Zeeb .single_pdev_only = false,
157dd4f32aeSBjoern A. Zeeb .rxdma1_enable = true,
158dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 1,
159dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = false,
160dd4f32aeSBjoern A. Zeeb .vdev_start_delay = false,
161dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = true,
162dd4f32aeSBjoern A. Zeeb
163dd4f32aeSBjoern A. Zeeb .spectral = {
164dd4f32aeSBjoern A. Zeeb .fft_sz = 4,
165dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 0,
166dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 0,
167dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 16,
168dd4f32aeSBjoern A. Zeeb .max_fft_bins = 512,
169*28348caeSBjoern A. Zeeb .fragment_160mhz = true,
170dd4f32aeSBjoern A. Zeeb },
171dd4f32aeSBjoern A. Zeeb
172dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
173dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP) |
174dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_MESH_POINT),
175dd4f32aeSBjoern A. Zeeb .supports_monitor = true,
176dd4f32aeSBjoern A. Zeeb .full_monitor_mode = false,
177dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = false,
178dd4f32aeSBjoern A. Zeeb .idle_ps = false,
179dd4f32aeSBjoern A. Zeeb .supports_sta_ps = false,
180*28348caeSBjoern A. Zeeb .coldboot_cal_mm = true,
181*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = true,
182*28348caeSBjoern A. Zeeb .cbcal_restart_fw = true,
183dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 0,
184dd4f32aeSBjoern A. Zeeb .num_vdevs = 16 + 1,
185dd4f32aeSBjoern A. Zeeb .num_peers = 512,
186dd4f32aeSBjoern A. Zeeb .supports_suspend = false,
187dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
188dd4f32aeSBjoern A. Zeeb .supports_regdb = false,
189dd4f32aeSBjoern A. Zeeb .fix_l1ss = true,
190dd4f32aeSBjoern A. Zeeb .credit_flow = false,
191dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX,
192dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_ipq8074,
193dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
194dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = true,
195dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = false,
196dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = false,
197*28348caeSBjoern A. Zeeb .current_cc_support = false,
198*28348caeSBjoern A. Zeeb .dbr_debug_support = true,
199*28348caeSBjoern A. Zeeb .global_reset = false,
200*28348caeSBjoern A. Zeeb .bios_sar_capa = NULL,
201*28348caeSBjoern A. Zeeb .m3_fw_support = false,
202*28348caeSBjoern A. Zeeb .fixed_bdf_addr = true,
203*28348caeSBjoern A. Zeeb .fixed_mem_region = true,
204*28348caeSBjoern A. Zeeb .static_window_map = false,
205*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
206*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
207*28348caeSBjoern A. Zeeb .support_off_channel_tx = false,
208*28348caeSBjoern A. Zeeb .supports_multi_bssid = false,
209*28348caeSBjoern A. Zeeb
210*28348caeSBjoern A. Zeeb .sram_dump = {},
211*28348caeSBjoern A. Zeeb
212*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
213*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
214*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
215*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = false,
216dd4f32aeSBjoern A. Zeeb },
217dd4f32aeSBjoern A. Zeeb {
218dd4f32aeSBjoern A. Zeeb .name = "qca6390 hw2.0",
219dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_QCA6390_HW20,
220dd4f32aeSBjoern A. Zeeb .fw = {
221dd4f32aeSBjoern A. Zeeb .dir = "QCA6390/hw2.0",
222dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
223dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
224dd4f32aeSBjoern A. Zeeb },
225dd4f32aeSBjoern A. Zeeb .max_radios = 3,
226dd4f32aeSBjoern A. Zeeb .bdf_addr = 0x4B0C0000,
227dd4f32aeSBjoern A. Zeeb .hw_ops = &qca6390_ops,
228dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_qca6390,
229dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = true,
230dd4f32aeSBjoern A. Zeeb .regs = &qca6390_regs,
231dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
232dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qca6390,
233dd4f32aeSBjoern A. Zeeb .ce_count = 9,
234dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
235dd4f32aeSBjoern A. Zeeb .target_ce_count = 9,
236dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
237dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 14,
238*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
239dd4f32aeSBjoern A. Zeeb .single_pdev_only = true,
240dd4f32aeSBjoern A. Zeeb .rxdma1_enable = false,
241dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 2,
242dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = true,
243dd4f32aeSBjoern A. Zeeb .vdev_start_delay = true,
244dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = false,
245dd4f32aeSBjoern A. Zeeb
246dd4f32aeSBjoern A. Zeeb .spectral = {
247dd4f32aeSBjoern A. Zeeb .fft_sz = 0,
248dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 0,
249dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 0,
250dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 0,
251dd4f32aeSBjoern A. Zeeb .max_fft_bins = 0,
252*28348caeSBjoern A. Zeeb .fragment_160mhz = false,
253dd4f32aeSBjoern A. Zeeb },
254dd4f32aeSBjoern A. Zeeb
255dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
256dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP),
257dd4f32aeSBjoern A. Zeeb .supports_monitor = false,
258dd4f32aeSBjoern A. Zeeb .full_monitor_mode = false,
259dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = true,
260dd4f32aeSBjoern A. Zeeb .idle_ps = true,
261dd4f32aeSBjoern A. Zeeb .supports_sta_ps = true,
262*28348caeSBjoern A. Zeeb .coldboot_cal_mm = false,
263*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = false,
264*28348caeSBjoern A. Zeeb .cbcal_restart_fw = false,
265dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 0,
266dd4f32aeSBjoern A. Zeeb .num_vdevs = 16 + 1,
267dd4f32aeSBjoern A. Zeeb .num_peers = 512,
268dd4f32aeSBjoern A. Zeeb .supports_suspend = true,
269dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
270*28348caeSBjoern A. Zeeb .supports_regdb = false,
271dd4f32aeSBjoern A. Zeeb .fix_l1ss = true,
272dd4f32aeSBjoern A. Zeeb .credit_flow = true,
273dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
274dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_qca6390,
275dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
276dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = false,
277dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = true,
278dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = true,
279*28348caeSBjoern A. Zeeb .current_cc_support = true,
280*28348caeSBjoern A. Zeeb .dbr_debug_support = false,
281*28348caeSBjoern A. Zeeb .global_reset = true,
282*28348caeSBjoern A. Zeeb .bios_sar_capa = NULL,
283*28348caeSBjoern A. Zeeb .m3_fw_support = true,
284*28348caeSBjoern A. Zeeb .fixed_bdf_addr = false,
285*28348caeSBjoern A. Zeeb .fixed_mem_region = false,
286*28348caeSBjoern A. Zeeb .static_window_map = false,
287*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
288*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
289*28348caeSBjoern A. Zeeb .support_off_channel_tx = true,
290*28348caeSBjoern A. Zeeb .supports_multi_bssid = true,
291*28348caeSBjoern A. Zeeb
292*28348caeSBjoern A. Zeeb .sram_dump = {
293*28348caeSBjoern A. Zeeb .start = 0x01400000,
294*28348caeSBjoern A. Zeeb .end = 0x0171ffff,
295*28348caeSBjoern A. Zeeb },
296*28348caeSBjoern A. Zeeb
297*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
298*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
299*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
300*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = true,
301dd4f32aeSBjoern A. Zeeb },
302dd4f32aeSBjoern A. Zeeb {
303dd4f32aeSBjoern A. Zeeb .name = "qcn9074 hw1.0",
304dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_QCN9074_HW10,
305dd4f32aeSBjoern A. Zeeb .fw = {
306dd4f32aeSBjoern A. Zeeb .dir = "QCN9074/hw1.0",
307dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
308dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
309dd4f32aeSBjoern A. Zeeb },
310dd4f32aeSBjoern A. Zeeb .max_radios = 1,
311dd4f32aeSBjoern A. Zeeb .single_pdev_only = false,
312dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
313dd4f32aeSBjoern A. Zeeb .hw_ops = &qcn9074_ops,
314dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_qcn9074,
315dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = false,
316dd4f32aeSBjoern A. Zeeb .regs = &qcn9074_regs,
317dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qcn9074,
318dd4f32aeSBjoern A. Zeeb .ce_count = 6,
319dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
320dd4f32aeSBjoern A. Zeeb .target_ce_count = 9,
321dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
322dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 18,
323*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
324dd4f32aeSBjoern A. Zeeb .rxdma1_enable = true,
325dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 1,
326dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = false,
327dd4f32aeSBjoern A. Zeeb .vdev_start_delay = false,
328dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = true,
329dd4f32aeSBjoern A. Zeeb
330dd4f32aeSBjoern A. Zeeb .spectral = {
331dd4f32aeSBjoern A. Zeeb .fft_sz = 2,
332dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 0,
333dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 16,
334dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 24,
335dd4f32aeSBjoern A. Zeeb .max_fft_bins = 1024,
336*28348caeSBjoern A. Zeeb .fragment_160mhz = false,
337dd4f32aeSBjoern A. Zeeb },
338dd4f32aeSBjoern A. Zeeb
339dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
340dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP) |
341dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_MESH_POINT),
342dd4f32aeSBjoern A. Zeeb .supports_monitor = true,
343dd4f32aeSBjoern A. Zeeb .full_monitor_mode = true,
344dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = false,
345dd4f32aeSBjoern A. Zeeb .idle_ps = false,
346dd4f32aeSBjoern A. Zeeb .supports_sta_ps = false,
347*28348caeSBjoern A. Zeeb .coldboot_cal_mm = false,
348*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = true,
349*28348caeSBjoern A. Zeeb .cbcal_restart_fw = true,
350dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 2,
351dd4f32aeSBjoern A. Zeeb .num_vdevs = 8,
352dd4f32aeSBjoern A. Zeeb .num_peers = 128,
353dd4f32aeSBjoern A. Zeeb .supports_suspend = false,
354dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
355dd4f32aeSBjoern A. Zeeb .supports_regdb = false,
356dd4f32aeSBjoern A. Zeeb .fix_l1ss = true,
357dd4f32aeSBjoern A. Zeeb .credit_flow = false,
358dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX,
359dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_ipq8074,
360dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = true,
361dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = true,
362dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = false,
363dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = false,
364*28348caeSBjoern A. Zeeb .current_cc_support = false,
365*28348caeSBjoern A. Zeeb .dbr_debug_support = true,
366*28348caeSBjoern A. Zeeb .global_reset = false,
367*28348caeSBjoern A. Zeeb .bios_sar_capa = NULL,
368*28348caeSBjoern A. Zeeb .m3_fw_support = true,
369*28348caeSBjoern A. Zeeb .fixed_bdf_addr = false,
370*28348caeSBjoern A. Zeeb .fixed_mem_region = false,
371*28348caeSBjoern A. Zeeb .static_window_map = true,
372*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
373*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
374*28348caeSBjoern A. Zeeb .support_off_channel_tx = false,
375*28348caeSBjoern A. Zeeb .supports_multi_bssid = false,
376*28348caeSBjoern A. Zeeb
377*28348caeSBjoern A. Zeeb .sram_dump = {},
378*28348caeSBjoern A. Zeeb
379*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
380*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
381*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
382*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = false,
383dd4f32aeSBjoern A. Zeeb },
384dd4f32aeSBjoern A. Zeeb {
385dd4f32aeSBjoern A. Zeeb .name = "wcn6855 hw2.0",
386dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_WCN6855_HW20,
387dd4f32aeSBjoern A. Zeeb .fw = {
388dd4f32aeSBjoern A. Zeeb .dir = "WCN6855/hw2.0",
389dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
390dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
391dd4f32aeSBjoern A. Zeeb },
392dd4f32aeSBjoern A. Zeeb .max_radios = 3,
393dd4f32aeSBjoern A. Zeeb .bdf_addr = 0x4B0C0000,
394dd4f32aeSBjoern A. Zeeb .hw_ops = &wcn6855_ops,
395dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_qca6390,
396dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = true,
397dd4f32aeSBjoern A. Zeeb .regs = &wcn6855_regs,
398dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
399dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qca6390,
400dd4f32aeSBjoern A. Zeeb .ce_count = 9,
401dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
402dd4f32aeSBjoern A. Zeeb .target_ce_count = 9,
403dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
404dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 14,
405*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
406dd4f32aeSBjoern A. Zeeb .single_pdev_only = true,
407dd4f32aeSBjoern A. Zeeb .rxdma1_enable = false,
408dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 2,
409dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = true,
410dd4f32aeSBjoern A. Zeeb .vdev_start_delay = true,
411dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = false,
412dd4f32aeSBjoern A. Zeeb
413dd4f32aeSBjoern A. Zeeb .spectral = {
414dd4f32aeSBjoern A. Zeeb .fft_sz = 0,
415dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 0,
416dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 0,
417dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 0,
418dd4f32aeSBjoern A. Zeeb .max_fft_bins = 0,
419*28348caeSBjoern A. Zeeb .fragment_160mhz = false,
420dd4f32aeSBjoern A. Zeeb },
421dd4f32aeSBjoern A. Zeeb
422dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
423dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP),
424dd4f32aeSBjoern A. Zeeb .supports_monitor = false,
425dd4f32aeSBjoern A. Zeeb .full_monitor_mode = false,
426dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = true,
427dd4f32aeSBjoern A. Zeeb .idle_ps = true,
428dd4f32aeSBjoern A. Zeeb .supports_sta_ps = true,
429*28348caeSBjoern A. Zeeb .coldboot_cal_mm = false,
430*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = false,
431*28348caeSBjoern A. Zeeb .cbcal_restart_fw = false,
432dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 0,
433dd4f32aeSBjoern A. Zeeb .num_vdevs = 16 + 1,
434dd4f32aeSBjoern A. Zeeb .num_peers = 512,
435dd4f32aeSBjoern A. Zeeb .supports_suspend = true,
436dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
437dd4f32aeSBjoern A. Zeeb .supports_regdb = true,
438dd4f32aeSBjoern A. Zeeb .fix_l1ss = false,
439dd4f32aeSBjoern A. Zeeb .credit_flow = true,
440dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
441dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_qca6390,
442dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
443dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = false,
444dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = true,
445dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = true,
446*28348caeSBjoern A. Zeeb .current_cc_support = true,
447*28348caeSBjoern A. Zeeb .dbr_debug_support = false,
448*28348caeSBjoern A. Zeeb .global_reset = true,
449*28348caeSBjoern A. Zeeb .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
450*28348caeSBjoern A. Zeeb .m3_fw_support = true,
451*28348caeSBjoern A. Zeeb .fixed_bdf_addr = false,
452*28348caeSBjoern A. Zeeb .fixed_mem_region = false,
453*28348caeSBjoern A. Zeeb .static_window_map = false,
454*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
455*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
456*28348caeSBjoern A. Zeeb .support_off_channel_tx = true,
457*28348caeSBjoern A. Zeeb .supports_multi_bssid = true,
458*28348caeSBjoern A. Zeeb
459*28348caeSBjoern A. Zeeb .sram_dump = {
460*28348caeSBjoern A. Zeeb .start = 0x01400000,
461*28348caeSBjoern A. Zeeb .end = 0x0177ffff,
462*28348caeSBjoern A. Zeeb },
463*28348caeSBjoern A. Zeeb
464*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
465*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
466*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
467*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = true,
468dd4f32aeSBjoern A. Zeeb },
469dd4f32aeSBjoern A. Zeeb {
470dd4f32aeSBjoern A. Zeeb .name = "wcn6855 hw2.1",
471dd4f32aeSBjoern A. Zeeb .hw_rev = ATH11K_HW_WCN6855_HW21,
472dd4f32aeSBjoern A. Zeeb .fw = {
473dd4f32aeSBjoern A. Zeeb .dir = "WCN6855/hw2.1",
474dd4f32aeSBjoern A. Zeeb .board_size = 256 * 1024,
475dd4f32aeSBjoern A. Zeeb .cal_offset = 128 * 1024,
476dd4f32aeSBjoern A. Zeeb },
477dd4f32aeSBjoern A. Zeeb .max_radios = 3,
478dd4f32aeSBjoern A. Zeeb .bdf_addr = 0x4B0C0000,
479dd4f32aeSBjoern A. Zeeb .hw_ops = &wcn6855_ops,
480dd4f32aeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_qca6390,
481dd4f32aeSBjoern A. Zeeb .internal_sleep_clock = true,
482dd4f32aeSBjoern A. Zeeb .regs = &wcn6855_regs,
483dd4f32aeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
484dd4f32aeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qca6390,
485dd4f32aeSBjoern A. Zeeb .ce_count = 9,
486dd4f32aeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
487dd4f32aeSBjoern A. Zeeb .target_ce_count = 9,
488dd4f32aeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
489dd4f32aeSBjoern A. Zeeb .svc_to_ce_map_len = 14,
490dd4f32aeSBjoern A. Zeeb .single_pdev_only = true,
491dd4f32aeSBjoern A. Zeeb .rxdma1_enable = false,
492dd4f32aeSBjoern A. Zeeb .num_rxmda_per_pdev = 2,
493dd4f32aeSBjoern A. Zeeb .rx_mac_buf_ring = true,
494dd4f32aeSBjoern A. Zeeb .vdev_start_delay = true,
495dd4f32aeSBjoern A. Zeeb .htt_peer_map_v2 = false,
496dd4f32aeSBjoern A. Zeeb
497dd4f32aeSBjoern A. Zeeb .spectral = {
498dd4f32aeSBjoern A. Zeeb .fft_sz = 0,
499dd4f32aeSBjoern A. Zeeb .fft_pad_sz = 0,
500dd4f32aeSBjoern A. Zeeb .summary_pad_sz = 0,
501dd4f32aeSBjoern A. Zeeb .fft_hdr_len = 0,
502dd4f32aeSBjoern A. Zeeb .max_fft_bins = 0,
503*28348caeSBjoern A. Zeeb .fragment_160mhz = false,
504dd4f32aeSBjoern A. Zeeb },
505dd4f32aeSBjoern A. Zeeb
506dd4f32aeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
507dd4f32aeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP),
508dd4f32aeSBjoern A. Zeeb .supports_monitor = false,
509dd4f32aeSBjoern A. Zeeb .supports_shadow_regs = true,
510dd4f32aeSBjoern A. Zeeb .idle_ps = true,
511dd4f32aeSBjoern A. Zeeb .supports_sta_ps = true,
512*28348caeSBjoern A. Zeeb .coldboot_cal_mm = false,
513*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = false,
514*28348caeSBjoern A. Zeeb .cbcal_restart_fw = false,
515dd4f32aeSBjoern A. Zeeb .fw_mem_mode = 0,
516dd4f32aeSBjoern A. Zeeb .num_vdevs = 16 + 1,
517dd4f32aeSBjoern A. Zeeb .num_peers = 512,
518dd4f32aeSBjoern A. Zeeb .supports_suspend = true,
519dd4f32aeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
520dd4f32aeSBjoern A. Zeeb .supports_regdb = true,
521dd4f32aeSBjoern A. Zeeb .fix_l1ss = false,
522dd4f32aeSBjoern A. Zeeb .credit_flow = true,
523dd4f32aeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
524dd4f32aeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_qca6390,
525dd4f32aeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
526dd4f32aeSBjoern A. Zeeb .alloc_cacheable_memory = false,
527dd4f32aeSBjoern A. Zeeb .supports_rssi_stats = true,
528dd4f32aeSBjoern A. Zeeb .fw_wmi_diag_event = true,
529*28348caeSBjoern A. Zeeb .current_cc_support = true,
530*28348caeSBjoern A. Zeeb .dbr_debug_support = false,
531*28348caeSBjoern A. Zeeb .global_reset = true,
532*28348caeSBjoern A. Zeeb .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
533*28348caeSBjoern A. Zeeb .m3_fw_support = true,
534*28348caeSBjoern A. Zeeb .fixed_bdf_addr = false,
535*28348caeSBjoern A. Zeeb .fixed_mem_region = false,
536*28348caeSBjoern A. Zeeb .static_window_map = false,
537*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
538*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
539*28348caeSBjoern A. Zeeb .support_off_channel_tx = true,
540*28348caeSBjoern A. Zeeb .supports_multi_bssid = true,
541*28348caeSBjoern A. Zeeb
542*28348caeSBjoern A. Zeeb .sram_dump = {
543*28348caeSBjoern A. Zeeb .start = 0x01400000,
544*28348caeSBjoern A. Zeeb .end = 0x0177ffff,
545*28348caeSBjoern A. Zeeb },
546*28348caeSBjoern A. Zeeb
547*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
548*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
549*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
550*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = true,
551*28348caeSBjoern A. Zeeb },
552*28348caeSBjoern A. Zeeb {
553*28348caeSBjoern A. Zeeb .name = "wcn6750 hw1.0",
554*28348caeSBjoern A. Zeeb .hw_rev = ATH11K_HW_WCN6750_HW10,
555*28348caeSBjoern A. Zeeb .fw = {
556*28348caeSBjoern A. Zeeb .dir = "WCN6750/hw1.0",
557*28348caeSBjoern A. Zeeb .board_size = 256 * 1024,
558*28348caeSBjoern A. Zeeb .cal_offset = 128 * 1024,
559*28348caeSBjoern A. Zeeb },
560*28348caeSBjoern A. Zeeb .max_radios = 1,
561*28348caeSBjoern A. Zeeb .bdf_addr = 0x4B0C0000,
562*28348caeSBjoern A. Zeeb .hw_ops = &wcn6750_ops,
563*28348caeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_wcn6750,
564*28348caeSBjoern A. Zeeb .internal_sleep_clock = false,
565*28348caeSBjoern A. Zeeb .regs = &wcn6750_regs,
566*28348caeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
567*28348caeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qca6390,
568*28348caeSBjoern A. Zeeb .ce_count = 9,
569*28348caeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
570*28348caeSBjoern A. Zeeb .target_ce_count = 9,
571*28348caeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
572*28348caeSBjoern A. Zeeb .svc_to_ce_map_len = 14,
573*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
574*28348caeSBjoern A. Zeeb .single_pdev_only = true,
575*28348caeSBjoern A. Zeeb .rxdma1_enable = false,
576*28348caeSBjoern A. Zeeb .num_rxmda_per_pdev = 1,
577*28348caeSBjoern A. Zeeb .rx_mac_buf_ring = true,
578*28348caeSBjoern A. Zeeb .vdev_start_delay = true,
579*28348caeSBjoern A. Zeeb .htt_peer_map_v2 = false,
580*28348caeSBjoern A. Zeeb
581*28348caeSBjoern A. Zeeb .spectral = {
582*28348caeSBjoern A. Zeeb .fft_sz = 0,
583*28348caeSBjoern A. Zeeb .fft_pad_sz = 0,
584*28348caeSBjoern A. Zeeb .summary_pad_sz = 0,
585*28348caeSBjoern A. Zeeb .fft_hdr_len = 0,
586*28348caeSBjoern A. Zeeb .max_fft_bins = 0,
587*28348caeSBjoern A. Zeeb .fragment_160mhz = false,
588*28348caeSBjoern A. Zeeb },
589*28348caeSBjoern A. Zeeb
590*28348caeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
591*28348caeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP),
592*28348caeSBjoern A. Zeeb .supports_monitor = false,
593*28348caeSBjoern A. Zeeb .supports_shadow_regs = true,
594*28348caeSBjoern A. Zeeb .idle_ps = true,
595*28348caeSBjoern A. Zeeb .supports_sta_ps = true,
596*28348caeSBjoern A. Zeeb .coldboot_cal_mm = true,
597*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = true,
598*28348caeSBjoern A. Zeeb .cbcal_restart_fw = false,
599*28348caeSBjoern A. Zeeb .fw_mem_mode = 0,
600*28348caeSBjoern A. Zeeb .num_vdevs = 16 + 1,
601*28348caeSBjoern A. Zeeb .num_peers = 512,
602*28348caeSBjoern A. Zeeb .supports_suspend = false,
603*28348caeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
604*28348caeSBjoern A. Zeeb .supports_regdb = true,
605*28348caeSBjoern A. Zeeb .fix_l1ss = false,
606*28348caeSBjoern A. Zeeb .credit_flow = true,
607*28348caeSBjoern A. Zeeb .max_tx_ring = DP_TCL_NUM_RING_MAX,
608*28348caeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_wcn6750,
609*28348caeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
610*28348caeSBjoern A. Zeeb .alloc_cacheable_memory = false,
611*28348caeSBjoern A. Zeeb .supports_rssi_stats = true,
612*28348caeSBjoern A. Zeeb .fw_wmi_diag_event = false,
613*28348caeSBjoern A. Zeeb .current_cc_support = true,
614*28348caeSBjoern A. Zeeb .dbr_debug_support = false,
615*28348caeSBjoern A. Zeeb .global_reset = false,
616*28348caeSBjoern A. Zeeb .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
617*28348caeSBjoern A. Zeeb .m3_fw_support = false,
618*28348caeSBjoern A. Zeeb .fixed_bdf_addr = false,
619*28348caeSBjoern A. Zeeb .fixed_mem_region = false,
620*28348caeSBjoern A. Zeeb .static_window_map = true,
621*28348caeSBjoern A. Zeeb .hybrid_bus_type = true,
622*28348caeSBjoern A. Zeeb .fixed_fw_mem = true,
623*28348caeSBjoern A. Zeeb .support_off_channel_tx = true,
624*28348caeSBjoern A. Zeeb .supports_multi_bssid = true,
625*28348caeSBjoern A. Zeeb
626*28348caeSBjoern A. Zeeb .sram_dump = {},
627*28348caeSBjoern A. Zeeb
628*28348caeSBjoern A. Zeeb .tcl_ring_retry = false,
629*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
630*28348caeSBjoern A. Zeeb .smp2p_wow_exit = true,
631*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = true,
632*28348caeSBjoern A. Zeeb },
633*28348caeSBjoern A. Zeeb {
634*28348caeSBjoern A. Zeeb .hw_rev = ATH11K_HW_IPQ5018_HW10,
635*28348caeSBjoern A. Zeeb .name = "ipq5018 hw1.0",
636*28348caeSBjoern A. Zeeb .fw = {
637*28348caeSBjoern A. Zeeb .dir = "IPQ5018/hw1.0",
638*28348caeSBjoern A. Zeeb .board_size = 256 * 1024,
639*28348caeSBjoern A. Zeeb .cal_offset = 128 * 1024,
640*28348caeSBjoern A. Zeeb },
641*28348caeSBjoern A. Zeeb .max_radios = MAX_RADIOS_5018,
642*28348caeSBjoern A. Zeeb .bdf_addr = 0x4BA00000,
643*28348caeSBjoern A. Zeeb /* hal_desc_sz and hw ops are similar to qcn9074 */
644*28348caeSBjoern A. Zeeb .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
645*28348caeSBjoern A. Zeeb .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
646*28348caeSBjoern A. Zeeb .ring_mask = &ath11k_hw_ring_mask_ipq8074,
647*28348caeSBjoern A. Zeeb .credit_flow = false,
648*28348caeSBjoern A. Zeeb .max_tx_ring = 1,
649*28348caeSBjoern A. Zeeb .spectral = {
650*28348caeSBjoern A. Zeeb .fft_sz = 2,
651*28348caeSBjoern A. Zeeb .fft_pad_sz = 0,
652*28348caeSBjoern A. Zeeb .summary_pad_sz = 16,
653*28348caeSBjoern A. Zeeb .fft_hdr_len = 24,
654*28348caeSBjoern A. Zeeb .max_fft_bins = 1024,
655*28348caeSBjoern A. Zeeb },
656*28348caeSBjoern A. Zeeb .internal_sleep_clock = false,
657*28348caeSBjoern A. Zeeb .regs = &ipq5018_regs,
658*28348caeSBjoern A. Zeeb .hw_ops = &ipq5018_ops,
659*28348caeSBjoern A. Zeeb .host_ce_config = ath11k_host_ce_config_qcn9074,
660*28348caeSBjoern A. Zeeb .ce_count = CE_CNT_5018,
661*28348caeSBjoern A. Zeeb .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
662*28348caeSBjoern A. Zeeb .target_ce_count = TARGET_CE_CNT_5018,
663*28348caeSBjoern A. Zeeb .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
664*28348caeSBjoern A. Zeeb .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
665*28348caeSBjoern A. Zeeb .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
666*28348caeSBjoern A. Zeeb .ce_remap = &ath11k_ce_remap_ipq5018,
667*28348caeSBjoern A. Zeeb .rxdma1_enable = true,
668*28348caeSBjoern A. Zeeb .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018,
669*28348caeSBjoern A. Zeeb .rx_mac_buf_ring = false,
670*28348caeSBjoern A. Zeeb .vdev_start_delay = false,
671*28348caeSBjoern A. Zeeb .htt_peer_map_v2 = true,
672*28348caeSBjoern A. Zeeb .interface_modes = BIT(NL80211_IFTYPE_STATION) |
673*28348caeSBjoern A. Zeeb BIT(NL80211_IFTYPE_AP) |
674*28348caeSBjoern A. Zeeb BIT(NL80211_IFTYPE_MESH_POINT),
675*28348caeSBjoern A. Zeeb .supports_monitor = false,
676*28348caeSBjoern A. Zeeb .supports_sta_ps = false,
677*28348caeSBjoern A. Zeeb .supports_shadow_regs = false,
678*28348caeSBjoern A. Zeeb .fw_mem_mode = 0,
679*28348caeSBjoern A. Zeeb .num_vdevs = 16 + 1,
680*28348caeSBjoern A. Zeeb .num_peers = 512,
681*28348caeSBjoern A. Zeeb .supports_regdb = false,
682*28348caeSBjoern A. Zeeb .idle_ps = false,
683*28348caeSBjoern A. Zeeb .supports_suspend = false,
684*28348caeSBjoern A. Zeeb .hal_params = &ath11k_hw_hal_params_ipq8074,
685*28348caeSBjoern A. Zeeb .single_pdev_only = false,
686*28348caeSBjoern A. Zeeb .coldboot_cal_mm = true,
687*28348caeSBjoern A. Zeeb .coldboot_cal_ftm = true,
688*28348caeSBjoern A. Zeeb .cbcal_restart_fw = true,
689*28348caeSBjoern A. Zeeb .fix_l1ss = true,
690*28348caeSBjoern A. Zeeb .supports_dynamic_smps_6ghz = false,
691*28348caeSBjoern A. Zeeb .alloc_cacheable_memory = true,
692*28348caeSBjoern A. Zeeb .supports_rssi_stats = false,
693*28348caeSBjoern A. Zeeb .fw_wmi_diag_event = false,
694*28348caeSBjoern A. Zeeb .current_cc_support = false,
695*28348caeSBjoern A. Zeeb .dbr_debug_support = true,
696*28348caeSBjoern A. Zeeb .global_reset = false,
697*28348caeSBjoern A. Zeeb .bios_sar_capa = NULL,
698*28348caeSBjoern A. Zeeb .m3_fw_support = false,
699*28348caeSBjoern A. Zeeb .fixed_bdf_addr = true,
700*28348caeSBjoern A. Zeeb .fixed_mem_region = true,
701*28348caeSBjoern A. Zeeb .static_window_map = false,
702*28348caeSBjoern A. Zeeb .hybrid_bus_type = false,
703*28348caeSBjoern A. Zeeb .fixed_fw_mem = false,
704*28348caeSBjoern A. Zeeb .support_off_channel_tx = false,
705*28348caeSBjoern A. Zeeb .supports_multi_bssid = false,
706*28348caeSBjoern A. Zeeb
707*28348caeSBjoern A. Zeeb .sram_dump = {},
708*28348caeSBjoern A. Zeeb
709*28348caeSBjoern A. Zeeb .tcl_ring_retry = true,
710*28348caeSBjoern A. Zeeb .tx_ring_size = DP_TCL_DATA_RING_SIZE,
711*28348caeSBjoern A. Zeeb .smp2p_wow_exit = false,
712*28348caeSBjoern A. Zeeb .support_fw_mac_sequence = false,
713dd4f32aeSBjoern A. Zeeb },
714dd4f32aeSBjoern A. Zeeb };
715dd4f32aeSBjoern A. Zeeb
ath11k_core_get_single_pdev(struct ath11k_base * ab)716*28348caeSBjoern A. Zeeb static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
717*28348caeSBjoern A. Zeeb {
718*28348caeSBjoern A. Zeeb WARN_ON(!ab->hw_params.single_pdev_only);
719*28348caeSBjoern A. Zeeb
720*28348caeSBjoern A. Zeeb return &ab->pdevs[0];
721*28348caeSBjoern A. Zeeb }
722*28348caeSBjoern A. Zeeb
ath11k_fw_stats_pdevs_free(struct list_head * head)723*28348caeSBjoern A. Zeeb void ath11k_fw_stats_pdevs_free(struct list_head *head)
724*28348caeSBjoern A. Zeeb {
725*28348caeSBjoern A. Zeeb struct ath11k_fw_stats_pdev *i, *tmp;
726*28348caeSBjoern A. Zeeb
727*28348caeSBjoern A. Zeeb list_for_each_entry_safe(i, tmp, head, list) {
728*28348caeSBjoern A. Zeeb list_del(&i->list);
729*28348caeSBjoern A. Zeeb kfree(i);
730*28348caeSBjoern A. Zeeb }
731*28348caeSBjoern A. Zeeb }
732*28348caeSBjoern A. Zeeb
ath11k_fw_stats_vdevs_free(struct list_head * head)733*28348caeSBjoern A. Zeeb void ath11k_fw_stats_vdevs_free(struct list_head *head)
734*28348caeSBjoern A. Zeeb {
735*28348caeSBjoern A. Zeeb struct ath11k_fw_stats_vdev *i, *tmp;
736*28348caeSBjoern A. Zeeb
737*28348caeSBjoern A. Zeeb list_for_each_entry_safe(i, tmp, head, list) {
738*28348caeSBjoern A. Zeeb list_del(&i->list);
739*28348caeSBjoern A. Zeeb kfree(i);
740*28348caeSBjoern A. Zeeb }
741*28348caeSBjoern A. Zeeb }
742*28348caeSBjoern A. Zeeb
ath11k_fw_stats_bcn_free(struct list_head * head)743*28348caeSBjoern A. Zeeb void ath11k_fw_stats_bcn_free(struct list_head *head)
744*28348caeSBjoern A. Zeeb {
745*28348caeSBjoern A. Zeeb struct ath11k_fw_stats_bcn *i, *tmp;
746*28348caeSBjoern A. Zeeb
747*28348caeSBjoern A. Zeeb list_for_each_entry_safe(i, tmp, head, list) {
748*28348caeSBjoern A. Zeeb list_del(&i->list);
749*28348caeSBjoern A. Zeeb kfree(i);
750*28348caeSBjoern A. Zeeb }
751*28348caeSBjoern A. Zeeb }
752*28348caeSBjoern A. Zeeb
ath11k_fw_stats_init(struct ath11k * ar)753*28348caeSBjoern A. Zeeb void ath11k_fw_stats_init(struct ath11k *ar)
754*28348caeSBjoern A. Zeeb {
755*28348caeSBjoern A. Zeeb INIT_LIST_HEAD(&ar->fw_stats.pdevs);
756*28348caeSBjoern A. Zeeb INIT_LIST_HEAD(&ar->fw_stats.vdevs);
757*28348caeSBjoern A. Zeeb INIT_LIST_HEAD(&ar->fw_stats.bcn);
758*28348caeSBjoern A. Zeeb
759*28348caeSBjoern A. Zeeb init_completion(&ar->fw_stats_complete);
760*28348caeSBjoern A. Zeeb }
761*28348caeSBjoern A. Zeeb
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)762*28348caeSBjoern A. Zeeb void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
763*28348caeSBjoern A. Zeeb {
764*28348caeSBjoern A. Zeeb ath11k_fw_stats_pdevs_free(&stats->pdevs);
765*28348caeSBjoern A. Zeeb ath11k_fw_stats_vdevs_free(&stats->vdevs);
766*28348caeSBjoern A. Zeeb ath11k_fw_stats_bcn_free(&stats->bcn);
767*28348caeSBjoern A. Zeeb }
768*28348caeSBjoern A. Zeeb
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)769*28348caeSBjoern A. Zeeb bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
770*28348caeSBjoern A. Zeeb {
771*28348caeSBjoern A. Zeeb if (!ath11k_cold_boot_cal)
772*28348caeSBjoern A. Zeeb return false;
773*28348caeSBjoern A. Zeeb
774*28348caeSBjoern A. Zeeb if (ath11k_ftm_mode)
775*28348caeSBjoern A. Zeeb return ab->hw_params.coldboot_cal_ftm;
776*28348caeSBjoern A. Zeeb
777*28348caeSBjoern A. Zeeb else
778*28348caeSBjoern A. Zeeb return ab->hw_params.coldboot_cal_mm;
779*28348caeSBjoern A. Zeeb }
780*28348caeSBjoern A. Zeeb
ath11k_core_suspend(struct ath11k_base * ab)781dd4f32aeSBjoern A. Zeeb int ath11k_core_suspend(struct ath11k_base *ab)
782dd4f32aeSBjoern A. Zeeb {
783dd4f32aeSBjoern A. Zeeb int ret;
784*28348caeSBjoern A. Zeeb struct ath11k_pdev *pdev;
785*28348caeSBjoern A. Zeeb struct ath11k *ar;
786dd4f32aeSBjoern A. Zeeb
787dd4f32aeSBjoern A. Zeeb if (!ab->hw_params.supports_suspend)
788dd4f32aeSBjoern A. Zeeb return -EOPNOTSUPP;
789dd4f32aeSBjoern A. Zeeb
790*28348caeSBjoern A. Zeeb /* so far single_pdev_only chips have supports_suspend as true
791*28348caeSBjoern A. Zeeb * and only the first pdev is valid.
792dd4f32aeSBjoern A. Zeeb */
793*28348caeSBjoern A. Zeeb pdev = ath11k_core_get_single_pdev(ab);
794*28348caeSBjoern A. Zeeb ar = pdev->ar;
795*28348caeSBjoern A. Zeeb if (!ar || ar->state != ATH11K_STATE_OFF)
796*28348caeSBjoern A. Zeeb return 0;
797dd4f32aeSBjoern A. Zeeb
798dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_rx_pktlog_stop(ab, true);
799dd4f32aeSBjoern A. Zeeb if (ret) {
800dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
801dd4f32aeSBjoern A. Zeeb ret);
802dd4f32aeSBjoern A. Zeeb return ret;
803dd4f32aeSBjoern A. Zeeb }
804dd4f32aeSBjoern A. Zeeb
805*28348caeSBjoern A. Zeeb ret = ath11k_mac_wait_tx_complete(ar);
806*28348caeSBjoern A. Zeeb if (ret) {
807*28348caeSBjoern A. Zeeb ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
808*28348caeSBjoern A. Zeeb return ret;
809*28348caeSBjoern A. Zeeb }
810*28348caeSBjoern A. Zeeb
811dd4f32aeSBjoern A. Zeeb ret = ath11k_wow_enable(ab);
812dd4f32aeSBjoern A. Zeeb if (ret) {
813dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
814dd4f32aeSBjoern A. Zeeb return ret;
815dd4f32aeSBjoern A. Zeeb }
816dd4f32aeSBjoern A. Zeeb
817dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_rx_pktlog_stop(ab, false);
818dd4f32aeSBjoern A. Zeeb if (ret) {
819dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
820dd4f32aeSBjoern A. Zeeb ret);
821dd4f32aeSBjoern A. Zeeb return ret;
822dd4f32aeSBjoern A. Zeeb }
823dd4f32aeSBjoern A. Zeeb
824dd4f32aeSBjoern A. Zeeb ath11k_ce_stop_shadow_timers(ab);
825dd4f32aeSBjoern A. Zeeb ath11k_dp_stop_shadow_timers(ab);
826dd4f32aeSBjoern A. Zeeb
827dd4f32aeSBjoern A. Zeeb ath11k_hif_irq_disable(ab);
828dd4f32aeSBjoern A. Zeeb ath11k_hif_ce_irq_disable(ab);
829dd4f32aeSBjoern A. Zeeb
830dd4f32aeSBjoern A. Zeeb ret = ath11k_hif_suspend(ab);
831dd4f32aeSBjoern A. Zeeb if (ret) {
832dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
833dd4f32aeSBjoern A. Zeeb return ret;
834dd4f32aeSBjoern A. Zeeb }
835dd4f32aeSBjoern A. Zeeb
836dd4f32aeSBjoern A. Zeeb return 0;
837dd4f32aeSBjoern A. Zeeb }
838dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_suspend);
839dd4f32aeSBjoern A. Zeeb
ath11k_core_resume(struct ath11k_base * ab)840dd4f32aeSBjoern A. Zeeb int ath11k_core_resume(struct ath11k_base *ab)
841dd4f32aeSBjoern A. Zeeb {
842dd4f32aeSBjoern A. Zeeb int ret;
843*28348caeSBjoern A. Zeeb struct ath11k_pdev *pdev;
844*28348caeSBjoern A. Zeeb struct ath11k *ar;
845dd4f32aeSBjoern A. Zeeb
846dd4f32aeSBjoern A. Zeeb if (!ab->hw_params.supports_suspend)
847dd4f32aeSBjoern A. Zeeb return -EOPNOTSUPP;
848dd4f32aeSBjoern A. Zeeb
849*28348caeSBjoern A. Zeeb /* so far signle_pdev_only chips have supports_suspend as true
850*28348caeSBjoern A. Zeeb * and only the first pdev is valid.
851*28348caeSBjoern A. Zeeb */
852*28348caeSBjoern A. Zeeb pdev = ath11k_core_get_single_pdev(ab);
853*28348caeSBjoern A. Zeeb ar = pdev->ar;
854*28348caeSBjoern A. Zeeb if (!ar || ar->state != ATH11K_STATE_OFF)
855*28348caeSBjoern A. Zeeb return 0;
856*28348caeSBjoern A. Zeeb
857dd4f32aeSBjoern A. Zeeb ret = ath11k_hif_resume(ab);
858dd4f32aeSBjoern A. Zeeb if (ret) {
859dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
860dd4f32aeSBjoern A. Zeeb return ret;
861dd4f32aeSBjoern A. Zeeb }
862dd4f32aeSBjoern A. Zeeb
863dd4f32aeSBjoern A. Zeeb ath11k_hif_ce_irq_enable(ab);
864dd4f32aeSBjoern A. Zeeb ath11k_hif_irq_enable(ab);
865dd4f32aeSBjoern A. Zeeb
866dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_rx_pktlog_start(ab);
867dd4f32aeSBjoern A. Zeeb if (ret) {
868dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
869dd4f32aeSBjoern A. Zeeb ret);
870dd4f32aeSBjoern A. Zeeb return ret;
871dd4f32aeSBjoern A. Zeeb }
872dd4f32aeSBjoern A. Zeeb
873dd4f32aeSBjoern A. Zeeb ret = ath11k_wow_wakeup(ab);
874dd4f32aeSBjoern A. Zeeb if (ret) {
875dd4f32aeSBjoern A. Zeeb ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
876dd4f32aeSBjoern A. Zeeb return ret;
877dd4f32aeSBjoern A. Zeeb }
878dd4f32aeSBjoern A. Zeeb
879dd4f32aeSBjoern A. Zeeb return 0;
880dd4f32aeSBjoern A. Zeeb }
881dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_resume);
882dd4f32aeSBjoern A. Zeeb
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)883*28348caeSBjoern A. Zeeb static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
884*28348caeSBjoern A. Zeeb {
885*28348caeSBjoern A. Zeeb struct ath11k_base *ab = data;
886*28348caeSBjoern A. Zeeb const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
887*28348caeSBjoern A. Zeeb #if defined(__linux__)
888*28348caeSBjoern A. Zeeb struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
889*28348caeSBjoern A. Zeeb #elif defined(__FreeBSD__)
890*28348caeSBjoern A. Zeeb const struct ath11k_smbios_bdf *smbios = (const struct ath11k_smbios_bdf *)hdr;
891*28348caeSBjoern A. Zeeb #endif
892*28348caeSBjoern A. Zeeb ssize_t copied;
893*28348caeSBjoern A. Zeeb size_t len;
894*28348caeSBjoern A. Zeeb int i;
895*28348caeSBjoern A. Zeeb
896*28348caeSBjoern A. Zeeb if (ab->qmi.target.bdf_ext[0] != '\0')
897*28348caeSBjoern A. Zeeb return;
898*28348caeSBjoern A. Zeeb
899*28348caeSBjoern A. Zeeb if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
900*28348caeSBjoern A. Zeeb return;
901*28348caeSBjoern A. Zeeb
902*28348caeSBjoern A. Zeeb if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
903*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
904*28348caeSBjoern A. Zeeb "wrong smbios bdf ext type length (%d).\n",
905*28348caeSBjoern A. Zeeb hdr->length);
906*28348caeSBjoern A. Zeeb return;
907*28348caeSBjoern A. Zeeb }
908*28348caeSBjoern A. Zeeb
909*28348caeSBjoern A. Zeeb spin_lock_bh(&ab->base_lock);
910*28348caeSBjoern A. Zeeb
911*28348caeSBjoern A. Zeeb switch (smbios->country_code_flag) {
912*28348caeSBjoern A. Zeeb case ATH11K_SMBIOS_CC_ISO:
913*28348caeSBjoern A. Zeeb ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
914*28348caeSBjoern A. Zeeb ab->new_alpha2[1] = smbios->cc_code & 0xff;
915*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
916*28348caeSBjoern A. Zeeb ab->new_alpha2[0], ab->new_alpha2[1]);
917*28348caeSBjoern A. Zeeb break;
918*28348caeSBjoern A. Zeeb case ATH11K_SMBIOS_CC_WW:
919*28348caeSBjoern A. Zeeb ab->new_alpha2[0] = '0';
920*28348caeSBjoern A. Zeeb ab->new_alpha2[1] = '0';
921*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
922*28348caeSBjoern A. Zeeb break;
923*28348caeSBjoern A. Zeeb default:
924*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
925*28348caeSBjoern A. Zeeb smbios->country_code_flag);
926*28348caeSBjoern A. Zeeb break;
927*28348caeSBjoern A. Zeeb }
928*28348caeSBjoern A. Zeeb
929*28348caeSBjoern A. Zeeb spin_unlock_bh(&ab->base_lock);
930*28348caeSBjoern A. Zeeb
931*28348caeSBjoern A. Zeeb if (!smbios->bdf_enabled) {
932*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
933*28348caeSBjoern A. Zeeb return;
934*28348caeSBjoern A. Zeeb }
935*28348caeSBjoern A. Zeeb
936*28348caeSBjoern A. Zeeb /* Only one string exists (per spec) */
937*28348caeSBjoern A. Zeeb if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
938*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
939*28348caeSBjoern A. Zeeb "bdf variant magic does not match.\n");
940*28348caeSBjoern A. Zeeb return;
941*28348caeSBjoern A. Zeeb }
942*28348caeSBjoern A. Zeeb
943*28348caeSBjoern A. Zeeb len = min_t(size_t,
944*28348caeSBjoern A. Zeeb strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
945*28348caeSBjoern A. Zeeb for (i = 0; i < len; i++) {
946*28348caeSBjoern A. Zeeb if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
947*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
948*28348caeSBjoern A. Zeeb "bdf variant name contains non ascii chars.\n");
949*28348caeSBjoern A. Zeeb return;
950*28348caeSBjoern A. Zeeb }
951*28348caeSBjoern A. Zeeb }
952*28348caeSBjoern A. Zeeb
953*28348caeSBjoern A. Zeeb /* Copy extension name without magic prefix */
954*28348caeSBjoern A. Zeeb copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
955*28348caeSBjoern A. Zeeb sizeof(ab->qmi.target.bdf_ext));
956*28348caeSBjoern A. Zeeb if (copied < 0) {
957*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
958*28348caeSBjoern A. Zeeb "bdf variant string is longer than the buffer can accommodate\n");
959*28348caeSBjoern A. Zeeb return;
960*28348caeSBjoern A. Zeeb }
961*28348caeSBjoern A. Zeeb
962*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
963*28348caeSBjoern A. Zeeb "found and validated bdf variant smbios_type 0x%x bdf %s\n",
964*28348caeSBjoern A. Zeeb ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
965*28348caeSBjoern A. Zeeb }
966*28348caeSBjoern A. Zeeb
ath11k_core_check_smbios(struct ath11k_base * ab)967*28348caeSBjoern A. Zeeb int ath11k_core_check_smbios(struct ath11k_base *ab)
968*28348caeSBjoern A. Zeeb {
969*28348caeSBjoern A. Zeeb ab->qmi.target.bdf_ext[0] = '\0';
970*28348caeSBjoern A. Zeeb dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
971*28348caeSBjoern A. Zeeb
972*28348caeSBjoern A. Zeeb if (ab->qmi.target.bdf_ext[0] == '\0')
973*28348caeSBjoern A. Zeeb return -ENODATA;
974*28348caeSBjoern A. Zeeb
975*28348caeSBjoern A. Zeeb return 0;
976*28348caeSBjoern A. Zeeb }
977*28348caeSBjoern A. Zeeb
ath11k_core_check_dt(struct ath11k_base * ab)978dd4f32aeSBjoern A. Zeeb int ath11k_core_check_dt(struct ath11k_base *ab)
979dd4f32aeSBjoern A. Zeeb {
980dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
981dd4f32aeSBjoern A. Zeeb size_t max_len = sizeof(ab->qmi.target.bdf_ext);
982dd4f32aeSBjoern A. Zeeb const char *variant = NULL;
983dd4f32aeSBjoern A. Zeeb struct device_node *node;
984dd4f32aeSBjoern A. Zeeb
985dd4f32aeSBjoern A. Zeeb node = ab->dev->of_node;
986dd4f32aeSBjoern A. Zeeb if (!node)
987dd4f32aeSBjoern A. Zeeb return -ENOENT;
988dd4f32aeSBjoern A. Zeeb
989dd4f32aeSBjoern A. Zeeb of_property_read_string(node, "qcom,ath11k-calibration-variant",
990dd4f32aeSBjoern A. Zeeb &variant);
991dd4f32aeSBjoern A. Zeeb if (!variant)
992dd4f32aeSBjoern A. Zeeb return -ENODATA;
993dd4f32aeSBjoern A. Zeeb
994dd4f32aeSBjoern A. Zeeb if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
995dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
996dd4f32aeSBjoern A. Zeeb "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
997dd4f32aeSBjoern A. Zeeb variant);
998dd4f32aeSBjoern A. Zeeb
999dd4f32aeSBjoern A. Zeeb return 0;
1000dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1001dd4f32aeSBjoern A. Zeeb return -ENOENT;
1002dd4f32aeSBjoern A. Zeeb #endif
1003dd4f32aeSBjoern A. Zeeb }
1004dd4f32aeSBjoern A. Zeeb
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,bool bus_type_mode)1005*28348caeSBjoern A. Zeeb static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1006*28348caeSBjoern A. Zeeb size_t name_len, bool with_variant,
1007*28348caeSBjoern A. Zeeb bool bus_type_mode)
1008dd4f32aeSBjoern A. Zeeb {
1009dd4f32aeSBjoern A. Zeeb /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1010dd4f32aeSBjoern A. Zeeb char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1011dd4f32aeSBjoern A. Zeeb
1012*28348caeSBjoern A. Zeeb if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1013dd4f32aeSBjoern A. Zeeb scnprintf(variant, sizeof(variant), ",variant=%s",
1014dd4f32aeSBjoern A. Zeeb ab->qmi.target.bdf_ext);
1015dd4f32aeSBjoern A. Zeeb
1016dd4f32aeSBjoern A. Zeeb switch (ab->id.bdf_search) {
1017dd4f32aeSBjoern A. Zeeb case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1018*28348caeSBjoern A. Zeeb if (bus_type_mode)
1019*28348caeSBjoern A. Zeeb scnprintf(name, name_len,
1020*28348caeSBjoern A. Zeeb "bus=%s",
1021*28348caeSBjoern A. Zeeb ath11k_bus_str(ab->hif.bus));
1022*28348caeSBjoern A. Zeeb else
1023dd4f32aeSBjoern A. Zeeb scnprintf(name, name_len,
1024dd4f32aeSBjoern A. Zeeb "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1025dd4f32aeSBjoern A. Zeeb ath11k_bus_str(ab->hif.bus),
1026dd4f32aeSBjoern A. Zeeb ab->id.vendor, ab->id.device,
1027dd4f32aeSBjoern A. Zeeb ab->id.subsystem_vendor,
1028dd4f32aeSBjoern A. Zeeb ab->id.subsystem_device,
1029dd4f32aeSBjoern A. Zeeb ab->qmi.target.chip_id,
1030dd4f32aeSBjoern A. Zeeb ab->qmi.target.board_id,
1031dd4f32aeSBjoern A. Zeeb variant);
1032dd4f32aeSBjoern A. Zeeb break;
1033dd4f32aeSBjoern A. Zeeb default:
1034dd4f32aeSBjoern A. Zeeb scnprintf(name, name_len,
1035dd4f32aeSBjoern A. Zeeb "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1036dd4f32aeSBjoern A. Zeeb ath11k_bus_str(ab->hif.bus),
1037dd4f32aeSBjoern A. Zeeb ab->qmi.target.chip_id,
1038dd4f32aeSBjoern A. Zeeb ab->qmi.target.board_id, variant);
1039dd4f32aeSBjoern A. Zeeb break;
1040dd4f32aeSBjoern A. Zeeb }
1041dd4f32aeSBjoern A. Zeeb
1042*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1043dd4f32aeSBjoern A. Zeeb
1044dd4f32aeSBjoern A. Zeeb return 0;
1045dd4f32aeSBjoern A. Zeeb }
1046dd4f32aeSBjoern A. Zeeb
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1047*28348caeSBjoern A. Zeeb static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1048*28348caeSBjoern A. Zeeb size_t name_len)
1049*28348caeSBjoern A. Zeeb {
1050*28348caeSBjoern A. Zeeb return __ath11k_core_create_board_name(ab, name, name_len, true, false);
1051*28348caeSBjoern A. Zeeb }
1052*28348caeSBjoern A. Zeeb
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1053*28348caeSBjoern A. Zeeb static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1054*28348caeSBjoern A. Zeeb size_t name_len)
1055*28348caeSBjoern A. Zeeb {
1056*28348caeSBjoern A. Zeeb return __ath11k_core_create_board_name(ab, name, name_len, false, false);
1057*28348caeSBjoern A. Zeeb }
1058*28348caeSBjoern A. Zeeb
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1059*28348caeSBjoern A. Zeeb static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1060*28348caeSBjoern A. Zeeb size_t name_len)
1061*28348caeSBjoern A. Zeeb {
1062*28348caeSBjoern A. Zeeb return __ath11k_core_create_board_name(ab, name, name_len, false, true);
1063*28348caeSBjoern A. Zeeb }
1064*28348caeSBjoern A. Zeeb
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1065dd4f32aeSBjoern A. Zeeb const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1066dd4f32aeSBjoern A. Zeeb const char *file)
1067dd4f32aeSBjoern A. Zeeb {
1068dd4f32aeSBjoern A. Zeeb const struct firmware *fw;
1069dd4f32aeSBjoern A. Zeeb char path[100];
1070dd4f32aeSBjoern A. Zeeb int ret;
1071dd4f32aeSBjoern A. Zeeb
1072dd4f32aeSBjoern A. Zeeb if (file == NULL)
1073dd4f32aeSBjoern A. Zeeb return ERR_PTR(-ENOENT);
1074dd4f32aeSBjoern A. Zeeb
1075dd4f32aeSBjoern A. Zeeb ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1076dd4f32aeSBjoern A. Zeeb
1077dd4f32aeSBjoern A. Zeeb ret = firmware_request_nowarn(&fw, path, ab->dev);
1078dd4f32aeSBjoern A. Zeeb if (ret)
1079dd4f32aeSBjoern A. Zeeb return ERR_PTR(ret);
1080dd4f32aeSBjoern A. Zeeb
1081*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1082dd4f32aeSBjoern A. Zeeb path, fw->size);
1083dd4f32aeSBjoern A. Zeeb
1084dd4f32aeSBjoern A. Zeeb return fw;
1085dd4f32aeSBjoern A. Zeeb }
1086dd4f32aeSBjoern A. Zeeb
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1087dd4f32aeSBjoern A. Zeeb void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1088dd4f32aeSBjoern A. Zeeb {
1089dd4f32aeSBjoern A. Zeeb if (!IS_ERR(bd->fw))
1090dd4f32aeSBjoern A. Zeeb release_firmware(bd->fw);
1091dd4f32aeSBjoern A. Zeeb
1092dd4f32aeSBjoern A. Zeeb memset(bd, 0, sizeof(*bd));
1093dd4f32aeSBjoern A. Zeeb }
1094dd4f32aeSBjoern A. Zeeb
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1095dd4f32aeSBjoern A. Zeeb static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1096dd4f32aeSBjoern A. Zeeb struct ath11k_board_data *bd,
1097dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1098dd4f32aeSBjoern A. Zeeb const void *buf, size_t buf_len,
1099dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1100dd4f32aeSBjoern A. Zeeb const u8 *buf, size_t buf_len,
1101dd4f32aeSBjoern A. Zeeb #endif
1102dd4f32aeSBjoern A. Zeeb const char *boardname,
1103*28348caeSBjoern A. Zeeb int ie_id,
1104*28348caeSBjoern A. Zeeb int name_id,
1105*28348caeSBjoern A. Zeeb int data_id)
1106dd4f32aeSBjoern A. Zeeb {
1107dd4f32aeSBjoern A. Zeeb const struct ath11k_fw_ie *hdr;
1108dd4f32aeSBjoern A. Zeeb bool name_match_found;
1109dd4f32aeSBjoern A. Zeeb int ret, board_ie_id;
1110dd4f32aeSBjoern A. Zeeb size_t board_ie_len;
1111dd4f32aeSBjoern A. Zeeb const void *board_ie_data;
1112dd4f32aeSBjoern A. Zeeb
1113dd4f32aeSBjoern A. Zeeb name_match_found = false;
1114dd4f32aeSBjoern A. Zeeb
1115*28348caeSBjoern A. Zeeb /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1116dd4f32aeSBjoern A. Zeeb while (buf_len > sizeof(struct ath11k_fw_ie)) {
1117dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1118dd4f32aeSBjoern A. Zeeb hdr = buf;
1119dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1120dd4f32aeSBjoern A. Zeeb hdr = (const struct ath11k_fw_ie *)buf;
1121dd4f32aeSBjoern A. Zeeb #endif
1122dd4f32aeSBjoern A. Zeeb board_ie_id = le32_to_cpu(hdr->id);
1123dd4f32aeSBjoern A. Zeeb board_ie_len = le32_to_cpu(hdr->len);
1124dd4f32aeSBjoern A. Zeeb board_ie_data = hdr->data;
1125dd4f32aeSBjoern A. Zeeb
1126dd4f32aeSBjoern A. Zeeb buf_len -= sizeof(*hdr);
1127dd4f32aeSBjoern A. Zeeb buf += sizeof(*hdr);
1128dd4f32aeSBjoern A. Zeeb
1129dd4f32aeSBjoern A. Zeeb if (buf_len < ALIGN(board_ie_len, 4)) {
1130*28348caeSBjoern A. Zeeb ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1131*28348caeSBjoern A. Zeeb ath11k_bd_ie_type_str(ie_id),
1132dd4f32aeSBjoern A. Zeeb buf_len, ALIGN(board_ie_len, 4));
1133dd4f32aeSBjoern A. Zeeb ret = -EINVAL;
1134dd4f32aeSBjoern A. Zeeb goto out;
1135dd4f32aeSBjoern A. Zeeb }
1136dd4f32aeSBjoern A. Zeeb
1137*28348caeSBjoern A. Zeeb if (board_ie_id == name_id) {
1138dd4f32aeSBjoern A. Zeeb ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1139dd4f32aeSBjoern A. Zeeb board_ie_data, board_ie_len);
1140dd4f32aeSBjoern A. Zeeb
1141dd4f32aeSBjoern A. Zeeb if (board_ie_len != strlen(boardname))
1142*28348caeSBjoern A. Zeeb goto next;
1143dd4f32aeSBjoern A. Zeeb
1144dd4f32aeSBjoern A. Zeeb ret = memcmp(board_ie_data, boardname, strlen(boardname));
1145dd4f32aeSBjoern A. Zeeb if (ret)
1146*28348caeSBjoern A. Zeeb goto next;
1147dd4f32aeSBjoern A. Zeeb
1148dd4f32aeSBjoern A. Zeeb name_match_found = true;
1149dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
1150*28348caeSBjoern A. Zeeb "found match %s for name '%s'",
1151*28348caeSBjoern A. Zeeb ath11k_bd_ie_type_str(ie_id),
1152dd4f32aeSBjoern A. Zeeb boardname);
1153*28348caeSBjoern A. Zeeb } else if (board_ie_id == data_id) {
1154dd4f32aeSBjoern A. Zeeb if (!name_match_found)
1155dd4f32aeSBjoern A. Zeeb /* no match found */
1156*28348caeSBjoern A. Zeeb goto next;
1157dd4f32aeSBjoern A. Zeeb
1158dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
1159*28348caeSBjoern A. Zeeb "found %s for '%s'",
1160*28348caeSBjoern A. Zeeb ath11k_bd_ie_type_str(ie_id),
1161*28348caeSBjoern A. Zeeb boardname);
1162dd4f32aeSBjoern A. Zeeb
1163dd4f32aeSBjoern A. Zeeb bd->data = board_ie_data;
1164dd4f32aeSBjoern A. Zeeb bd->len = board_ie_len;
1165dd4f32aeSBjoern A. Zeeb
1166dd4f32aeSBjoern A. Zeeb ret = 0;
1167dd4f32aeSBjoern A. Zeeb goto out;
1168*28348caeSBjoern A. Zeeb } else {
1169*28348caeSBjoern A. Zeeb ath11k_warn(ab, "unknown %s id found: %d\n",
1170*28348caeSBjoern A. Zeeb ath11k_bd_ie_type_str(ie_id),
1171dd4f32aeSBjoern A. Zeeb board_ie_id);
1172dd4f32aeSBjoern A. Zeeb }
1173*28348caeSBjoern A. Zeeb next:
1174dd4f32aeSBjoern A. Zeeb /* jump over the padding */
1175dd4f32aeSBjoern A. Zeeb board_ie_len = ALIGN(board_ie_len, 4);
1176dd4f32aeSBjoern A. Zeeb
1177dd4f32aeSBjoern A. Zeeb buf_len -= board_ie_len;
1178dd4f32aeSBjoern A. Zeeb buf += board_ie_len;
1179dd4f32aeSBjoern A. Zeeb }
1180dd4f32aeSBjoern A. Zeeb
1181dd4f32aeSBjoern A. Zeeb /* no match found */
1182dd4f32aeSBjoern A. Zeeb ret = -ENOENT;
1183dd4f32aeSBjoern A. Zeeb
1184dd4f32aeSBjoern A. Zeeb out:
1185dd4f32aeSBjoern A. Zeeb return ret;
1186dd4f32aeSBjoern A. Zeeb }
1187dd4f32aeSBjoern A. Zeeb
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1188dd4f32aeSBjoern A. Zeeb static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1189dd4f32aeSBjoern A. Zeeb struct ath11k_board_data *bd,
1190*28348caeSBjoern A. Zeeb const char *boardname,
1191*28348caeSBjoern A. Zeeb int ie_id_match,
1192*28348caeSBjoern A. Zeeb int name_id,
1193*28348caeSBjoern A. Zeeb int data_id)
1194dd4f32aeSBjoern A. Zeeb {
1195dd4f32aeSBjoern A. Zeeb size_t len, magic_len;
1196dd4f32aeSBjoern A. Zeeb const u8 *data;
1197dd4f32aeSBjoern A. Zeeb char *filename, filepath[100];
1198dd4f32aeSBjoern A. Zeeb size_t ie_len;
1199dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1200dd4f32aeSBjoern A. Zeeb struct ath11k_fw_ie *hdr;
1201dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1202dd4f32aeSBjoern A. Zeeb const struct ath11k_fw_ie *hdr;
1203dd4f32aeSBjoern A. Zeeb #endif
1204dd4f32aeSBjoern A. Zeeb int ret, ie_id;
1205dd4f32aeSBjoern A. Zeeb
1206dd4f32aeSBjoern A. Zeeb filename = ATH11K_BOARD_API2_FILE;
1207dd4f32aeSBjoern A. Zeeb
1208dd4f32aeSBjoern A. Zeeb if (!bd->fw)
1209dd4f32aeSBjoern A. Zeeb bd->fw = ath11k_core_firmware_request(ab, filename);
1210dd4f32aeSBjoern A. Zeeb
1211dd4f32aeSBjoern A. Zeeb if (IS_ERR(bd->fw))
1212dd4f32aeSBjoern A. Zeeb return PTR_ERR(bd->fw);
1213dd4f32aeSBjoern A. Zeeb
1214dd4f32aeSBjoern A. Zeeb data = bd->fw->data;
1215dd4f32aeSBjoern A. Zeeb len = bd->fw->size;
1216dd4f32aeSBjoern A. Zeeb
1217dd4f32aeSBjoern A. Zeeb ath11k_core_create_firmware_path(ab, filename,
1218dd4f32aeSBjoern A. Zeeb filepath, sizeof(filepath));
1219dd4f32aeSBjoern A. Zeeb
1220dd4f32aeSBjoern A. Zeeb /* magic has extra null byte padded */
1221dd4f32aeSBjoern A. Zeeb magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1222dd4f32aeSBjoern A. Zeeb if (len < magic_len) {
1223dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1224dd4f32aeSBjoern A. Zeeb filepath, len);
1225dd4f32aeSBjoern A. Zeeb ret = -EINVAL;
1226dd4f32aeSBjoern A. Zeeb goto err;
1227dd4f32aeSBjoern A. Zeeb }
1228dd4f32aeSBjoern A. Zeeb
1229dd4f32aeSBjoern A. Zeeb if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1230dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "found invalid board magic\n");
1231dd4f32aeSBjoern A. Zeeb ret = -EINVAL;
1232dd4f32aeSBjoern A. Zeeb goto err;
1233dd4f32aeSBjoern A. Zeeb }
1234dd4f32aeSBjoern A. Zeeb
1235dd4f32aeSBjoern A. Zeeb /* magic is padded to 4 bytes */
1236dd4f32aeSBjoern A. Zeeb magic_len = ALIGN(magic_len, 4);
1237dd4f32aeSBjoern A. Zeeb if (len < magic_len) {
1238dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1239dd4f32aeSBjoern A. Zeeb filepath, len);
1240dd4f32aeSBjoern A. Zeeb ret = -EINVAL;
1241dd4f32aeSBjoern A. Zeeb goto err;
1242dd4f32aeSBjoern A. Zeeb }
1243dd4f32aeSBjoern A. Zeeb
1244dd4f32aeSBjoern A. Zeeb data += magic_len;
1245dd4f32aeSBjoern A. Zeeb len -= magic_len;
1246dd4f32aeSBjoern A. Zeeb
1247dd4f32aeSBjoern A. Zeeb while (len > sizeof(struct ath11k_fw_ie)) {
1248dd4f32aeSBjoern A. Zeeb #if defined(__linux__)
1249dd4f32aeSBjoern A. Zeeb hdr = (struct ath11k_fw_ie *)data;
1250dd4f32aeSBjoern A. Zeeb #elif defined(__FreeBSD__)
1251dd4f32aeSBjoern A. Zeeb hdr = (const struct ath11k_fw_ie *)data;
1252dd4f32aeSBjoern A. Zeeb #endif
1253dd4f32aeSBjoern A. Zeeb ie_id = le32_to_cpu(hdr->id);
1254dd4f32aeSBjoern A. Zeeb ie_len = le32_to_cpu(hdr->len);
1255dd4f32aeSBjoern A. Zeeb
1256dd4f32aeSBjoern A. Zeeb len -= sizeof(*hdr);
1257dd4f32aeSBjoern A. Zeeb data = hdr->data;
1258dd4f32aeSBjoern A. Zeeb
1259dd4f32aeSBjoern A. Zeeb if (len < ALIGN(ie_len, 4)) {
1260dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1261dd4f32aeSBjoern A. Zeeb ie_id, ie_len, len);
1262dd4f32aeSBjoern A. Zeeb ret = -EINVAL;
1263dd4f32aeSBjoern A. Zeeb goto err;
1264dd4f32aeSBjoern A. Zeeb }
1265dd4f32aeSBjoern A. Zeeb
1266*28348caeSBjoern A. Zeeb if (ie_id == ie_id_match) {
1267dd4f32aeSBjoern A. Zeeb ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1268dd4f32aeSBjoern A. Zeeb ie_len,
1269dd4f32aeSBjoern A. Zeeb boardname,
1270*28348caeSBjoern A. Zeeb ie_id_match,
1271*28348caeSBjoern A. Zeeb name_id,
1272*28348caeSBjoern A. Zeeb data_id);
1273dd4f32aeSBjoern A. Zeeb if (ret == -ENOENT)
1274dd4f32aeSBjoern A. Zeeb /* no match found, continue */
1275*28348caeSBjoern A. Zeeb goto next;
1276dd4f32aeSBjoern A. Zeeb else if (ret)
1277dd4f32aeSBjoern A. Zeeb /* there was an error, bail out */
1278dd4f32aeSBjoern A. Zeeb goto err;
1279dd4f32aeSBjoern A. Zeeb /* either found or error, so stop searching */
1280dd4f32aeSBjoern A. Zeeb goto out;
1281dd4f32aeSBjoern A. Zeeb }
1282*28348caeSBjoern A. Zeeb next:
1283dd4f32aeSBjoern A. Zeeb /* jump over the padding */
1284dd4f32aeSBjoern A. Zeeb ie_len = ALIGN(ie_len, 4);
1285dd4f32aeSBjoern A. Zeeb
1286dd4f32aeSBjoern A. Zeeb len -= ie_len;
1287dd4f32aeSBjoern A. Zeeb data += ie_len;
1288dd4f32aeSBjoern A. Zeeb }
1289dd4f32aeSBjoern A. Zeeb
1290dd4f32aeSBjoern A. Zeeb out:
1291dd4f32aeSBjoern A. Zeeb if (!bd->data || !bd->len) {
1292*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
1293*28348caeSBjoern A. Zeeb "failed to fetch %s for %s from %s\n",
1294*28348caeSBjoern A. Zeeb ath11k_bd_ie_type_str(ie_id_match),
1295dd4f32aeSBjoern A. Zeeb boardname, filepath);
1296dd4f32aeSBjoern A. Zeeb ret = -ENODATA;
1297dd4f32aeSBjoern A. Zeeb goto err;
1298dd4f32aeSBjoern A. Zeeb }
1299dd4f32aeSBjoern A. Zeeb
1300dd4f32aeSBjoern A. Zeeb return 0;
1301dd4f32aeSBjoern A. Zeeb
1302dd4f32aeSBjoern A. Zeeb err:
1303dd4f32aeSBjoern A. Zeeb ath11k_core_free_bdf(ab, bd);
1304dd4f32aeSBjoern A. Zeeb return ret;
1305dd4f32aeSBjoern A. Zeeb }
1306dd4f32aeSBjoern A. Zeeb
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1307dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1308dd4f32aeSBjoern A. Zeeb struct ath11k_board_data *bd,
1309dd4f32aeSBjoern A. Zeeb const char *name)
1310dd4f32aeSBjoern A. Zeeb {
1311dd4f32aeSBjoern A. Zeeb bd->fw = ath11k_core_firmware_request(ab, name);
1312dd4f32aeSBjoern A. Zeeb
1313dd4f32aeSBjoern A. Zeeb if (IS_ERR(bd->fw))
1314dd4f32aeSBjoern A. Zeeb return PTR_ERR(bd->fw);
1315dd4f32aeSBjoern A. Zeeb
1316dd4f32aeSBjoern A. Zeeb bd->data = bd->fw->data;
1317dd4f32aeSBjoern A. Zeeb bd->len = bd->fw->size;
1318dd4f32aeSBjoern A. Zeeb
1319dd4f32aeSBjoern A. Zeeb return 0;
1320dd4f32aeSBjoern A. Zeeb }
1321dd4f32aeSBjoern A. Zeeb
1322dd4f32aeSBjoern A. Zeeb #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1323dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1324dd4f32aeSBjoern A. Zeeb {
1325*28348caeSBjoern A. Zeeb char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
1326*28348caeSBjoern A. Zeeb char *filename, filepath[100];
1327dd4f32aeSBjoern A. Zeeb int ret;
1328dd4f32aeSBjoern A. Zeeb
1329*28348caeSBjoern A. Zeeb filename = ATH11K_BOARD_API2_FILE;
1330*28348caeSBjoern A. Zeeb
1331*28348caeSBjoern A. Zeeb ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1332dd4f32aeSBjoern A. Zeeb if (ret) {
1333dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create board name: %d", ret);
1334dd4f32aeSBjoern A. Zeeb return ret;
1335dd4f32aeSBjoern A. Zeeb }
1336dd4f32aeSBjoern A. Zeeb
1337dd4f32aeSBjoern A. Zeeb ab->bd_api = 2;
1338*28348caeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1339*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD,
1340*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD_NAME,
1341*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD_DATA);
1342*28348caeSBjoern A. Zeeb if (!ret)
1343*28348caeSBjoern A. Zeeb goto success;
1344*28348caeSBjoern A. Zeeb
1345*28348caeSBjoern A. Zeeb ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1346*28348caeSBjoern A. Zeeb sizeof(fallback_boardname));
1347*28348caeSBjoern A. Zeeb if (ret) {
1348*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to create fallback board name: %d", ret);
1349*28348caeSBjoern A. Zeeb return ret;
1350*28348caeSBjoern A. Zeeb }
1351*28348caeSBjoern A. Zeeb
1352*28348caeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1353*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD,
1354*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD_NAME,
1355*28348caeSBjoern A. Zeeb ATH11K_BD_IE_BOARD_DATA);
1356dd4f32aeSBjoern A. Zeeb if (!ret)
1357dd4f32aeSBjoern A. Zeeb goto success;
1358dd4f32aeSBjoern A. Zeeb
1359dd4f32aeSBjoern A. Zeeb ab->bd_api = 1;
1360dd4f32aeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1361dd4f32aeSBjoern A. Zeeb if (ret) {
1362*28348caeSBjoern A. Zeeb ath11k_core_create_firmware_path(ab, filename,
1363*28348caeSBjoern A. Zeeb filepath, sizeof(filepath));
1364*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1365*28348caeSBjoern A. Zeeb boardname, filepath);
1366*28348caeSBjoern A. Zeeb if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1367*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1368*28348caeSBjoern A. Zeeb fallback_boardname, filepath);
1369*28348caeSBjoern A. Zeeb
1370*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to fetch board.bin from %s\n",
1371dd4f32aeSBjoern A. Zeeb ab->hw_params.fw.dir);
1372dd4f32aeSBjoern A. Zeeb return ret;
1373dd4f32aeSBjoern A. Zeeb }
1374dd4f32aeSBjoern A. Zeeb
1375dd4f32aeSBjoern A. Zeeb success:
1376dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1377dd4f32aeSBjoern A. Zeeb return 0;
1378dd4f32aeSBjoern A. Zeeb }
1379dd4f32aeSBjoern A. Zeeb
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1380dd4f32aeSBjoern A. Zeeb int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1381dd4f32aeSBjoern A. Zeeb {
1382*28348caeSBjoern A. Zeeb char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1383dd4f32aeSBjoern A. Zeeb int ret;
1384dd4f32aeSBjoern A. Zeeb
1385*28348caeSBjoern A. Zeeb ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1386*28348caeSBjoern A. Zeeb if (ret) {
1387*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
1388*28348caeSBjoern A. Zeeb "failed to create board name for regdb: %d", ret);
1389*28348caeSBjoern A. Zeeb goto exit;
1390*28348caeSBjoern A. Zeeb }
1391*28348caeSBjoern A. Zeeb
1392*28348caeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1393*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB,
1394*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB_NAME,
1395*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB_DATA);
1396*28348caeSBjoern A. Zeeb if (!ret)
1397*28348caeSBjoern A. Zeeb goto exit;
1398*28348caeSBjoern A. Zeeb
1399*28348caeSBjoern A. Zeeb ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1400*28348caeSBjoern A. Zeeb BOARD_NAME_SIZE);
1401*28348caeSBjoern A. Zeeb if (ret) {
1402*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT,
1403*28348caeSBjoern A. Zeeb "failed to create default board name for regdb: %d", ret);
1404*28348caeSBjoern A. Zeeb goto exit;
1405*28348caeSBjoern A. Zeeb }
1406*28348caeSBjoern A. Zeeb
1407*28348caeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1408*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB,
1409*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB_NAME,
1410*28348caeSBjoern A. Zeeb ATH11K_BD_IE_REGDB_DATA);
1411*28348caeSBjoern A. Zeeb if (!ret)
1412*28348caeSBjoern A. Zeeb goto exit;
1413*28348caeSBjoern A. Zeeb
1414dd4f32aeSBjoern A. Zeeb ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1415dd4f32aeSBjoern A. Zeeb if (ret)
1416dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1417dd4f32aeSBjoern A. Zeeb ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1418dd4f32aeSBjoern A. Zeeb
1419*28348caeSBjoern A. Zeeb exit:
1420*28348caeSBjoern A. Zeeb if (!ret)
1421*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1422*28348caeSBjoern A. Zeeb
1423dd4f32aeSBjoern A. Zeeb return ret;
1424dd4f32aeSBjoern A. Zeeb }
1425dd4f32aeSBjoern A. Zeeb
ath11k_core_stop(struct ath11k_base * ab)1426dd4f32aeSBjoern A. Zeeb static void ath11k_core_stop(struct ath11k_base *ab)
1427dd4f32aeSBjoern A. Zeeb {
1428dd4f32aeSBjoern A. Zeeb if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1429dd4f32aeSBjoern A. Zeeb ath11k_qmi_firmware_stop(ab);
1430dd4f32aeSBjoern A. Zeeb
1431dd4f32aeSBjoern A. Zeeb ath11k_hif_stop(ab);
1432dd4f32aeSBjoern A. Zeeb ath11k_wmi_detach(ab);
1433dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_reo_cleanup(ab);
1434dd4f32aeSBjoern A. Zeeb
1435dd4f32aeSBjoern A. Zeeb /* De-Init of components as needed */
1436dd4f32aeSBjoern A. Zeeb }
1437dd4f32aeSBjoern A. Zeeb
ath11k_core_soc_create(struct ath11k_base * ab)1438dd4f32aeSBjoern A. Zeeb static int ath11k_core_soc_create(struct ath11k_base *ab)
1439dd4f32aeSBjoern A. Zeeb {
1440dd4f32aeSBjoern A. Zeeb int ret;
1441dd4f32aeSBjoern A. Zeeb
1442*28348caeSBjoern A. Zeeb if (ath11k_ftm_mode) {
1443*28348caeSBjoern A. Zeeb ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1444*28348caeSBjoern A. Zeeb ath11k_info(ab, "Booting in factory test mode\n");
1445*28348caeSBjoern A. Zeeb }
1446*28348caeSBjoern A. Zeeb
1447dd4f32aeSBjoern A. Zeeb ret = ath11k_qmi_init_service(ab);
1448dd4f32aeSBjoern A. Zeeb if (ret) {
1449dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1450dd4f32aeSBjoern A. Zeeb return ret;
1451dd4f32aeSBjoern A. Zeeb }
1452dd4f32aeSBjoern A. Zeeb
1453dd4f32aeSBjoern A. Zeeb ret = ath11k_debugfs_soc_create(ab);
1454dd4f32aeSBjoern A. Zeeb if (ret) {
1455dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create ath11k debugfs\n");
1456dd4f32aeSBjoern A. Zeeb goto err_qmi_deinit;
1457dd4f32aeSBjoern A. Zeeb }
1458dd4f32aeSBjoern A. Zeeb
1459dd4f32aeSBjoern A. Zeeb ret = ath11k_hif_power_up(ab);
1460dd4f32aeSBjoern A. Zeeb if (ret) {
1461dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to power up :%d\n", ret);
1462dd4f32aeSBjoern A. Zeeb goto err_debugfs_reg;
1463dd4f32aeSBjoern A. Zeeb }
1464dd4f32aeSBjoern A. Zeeb
1465dd4f32aeSBjoern A. Zeeb return 0;
1466dd4f32aeSBjoern A. Zeeb
1467dd4f32aeSBjoern A. Zeeb err_debugfs_reg:
1468dd4f32aeSBjoern A. Zeeb ath11k_debugfs_soc_destroy(ab);
1469dd4f32aeSBjoern A. Zeeb err_qmi_deinit:
1470dd4f32aeSBjoern A. Zeeb ath11k_qmi_deinit_service(ab);
1471dd4f32aeSBjoern A. Zeeb return ret;
1472dd4f32aeSBjoern A. Zeeb }
1473dd4f32aeSBjoern A. Zeeb
ath11k_core_soc_destroy(struct ath11k_base * ab)1474dd4f32aeSBjoern A. Zeeb static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1475dd4f32aeSBjoern A. Zeeb {
1476dd4f32aeSBjoern A. Zeeb ath11k_debugfs_soc_destroy(ab);
1477dd4f32aeSBjoern A. Zeeb ath11k_dp_free(ab);
1478dd4f32aeSBjoern A. Zeeb ath11k_reg_free(ab);
1479dd4f32aeSBjoern A. Zeeb ath11k_qmi_deinit_service(ab);
1480dd4f32aeSBjoern A. Zeeb }
1481dd4f32aeSBjoern A. Zeeb
ath11k_core_pdev_create(struct ath11k_base * ab)1482dd4f32aeSBjoern A. Zeeb static int ath11k_core_pdev_create(struct ath11k_base *ab)
1483dd4f32aeSBjoern A. Zeeb {
1484dd4f32aeSBjoern A. Zeeb int ret;
1485dd4f32aeSBjoern A. Zeeb
1486dd4f32aeSBjoern A. Zeeb ret = ath11k_debugfs_pdev_create(ab);
1487dd4f32aeSBjoern A. Zeeb if (ret) {
1488dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1489dd4f32aeSBjoern A. Zeeb return ret;
1490dd4f32aeSBjoern A. Zeeb }
1491dd4f32aeSBjoern A. Zeeb
1492dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_pdev_alloc(ab);
1493dd4f32aeSBjoern A. Zeeb if (ret) {
1494dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1495*28348caeSBjoern A. Zeeb goto err_pdev_debug;
1496*28348caeSBjoern A. Zeeb }
1497*28348caeSBjoern A. Zeeb
1498*28348caeSBjoern A. Zeeb ret = ath11k_mac_register(ab);
1499*28348caeSBjoern A. Zeeb if (ret) {
1500*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1501*28348caeSBjoern A. Zeeb goto err_dp_pdev_free;
1502dd4f32aeSBjoern A. Zeeb }
1503dd4f32aeSBjoern A. Zeeb
1504dd4f32aeSBjoern A. Zeeb ret = ath11k_thermal_register(ab);
1505dd4f32aeSBjoern A. Zeeb if (ret) {
1506dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "could not register thermal device: %d\n",
1507dd4f32aeSBjoern A. Zeeb ret);
1508*28348caeSBjoern A. Zeeb goto err_mac_unregister;
1509dd4f32aeSBjoern A. Zeeb }
1510dd4f32aeSBjoern A. Zeeb
1511dd4f32aeSBjoern A. Zeeb ret = ath11k_spectral_init(ab);
1512dd4f32aeSBjoern A. Zeeb if (ret) {
1513dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to init spectral %d\n", ret);
1514dd4f32aeSBjoern A. Zeeb goto err_thermal_unregister;
1515dd4f32aeSBjoern A. Zeeb }
1516dd4f32aeSBjoern A. Zeeb
1517dd4f32aeSBjoern A. Zeeb return 0;
1518dd4f32aeSBjoern A. Zeeb
1519dd4f32aeSBjoern A. Zeeb err_thermal_unregister:
1520dd4f32aeSBjoern A. Zeeb ath11k_thermal_unregister(ab);
1521dd4f32aeSBjoern A. Zeeb err_mac_unregister:
1522dd4f32aeSBjoern A. Zeeb ath11k_mac_unregister(ab);
1523*28348caeSBjoern A. Zeeb err_dp_pdev_free:
1524*28348caeSBjoern A. Zeeb ath11k_dp_pdev_free(ab);
1525dd4f32aeSBjoern A. Zeeb err_pdev_debug:
1526dd4f32aeSBjoern A. Zeeb ath11k_debugfs_pdev_destroy(ab);
1527dd4f32aeSBjoern A. Zeeb
1528dd4f32aeSBjoern A. Zeeb return ret;
1529dd4f32aeSBjoern A. Zeeb }
1530dd4f32aeSBjoern A. Zeeb
ath11k_core_pdev_destroy(struct ath11k_base * ab)1531dd4f32aeSBjoern A. Zeeb static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1532dd4f32aeSBjoern A. Zeeb {
1533dd4f32aeSBjoern A. Zeeb ath11k_spectral_deinit(ab);
1534dd4f32aeSBjoern A. Zeeb ath11k_thermal_unregister(ab);
1535dd4f32aeSBjoern A. Zeeb ath11k_mac_unregister(ab);
1536dd4f32aeSBjoern A. Zeeb ath11k_hif_irq_disable(ab);
1537dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_free(ab);
1538dd4f32aeSBjoern A. Zeeb ath11k_debugfs_pdev_destroy(ab);
1539dd4f32aeSBjoern A. Zeeb }
1540dd4f32aeSBjoern A. Zeeb
ath11k_core_start(struct ath11k_base * ab)1541*28348caeSBjoern A. Zeeb static int ath11k_core_start(struct ath11k_base *ab)
1542dd4f32aeSBjoern A. Zeeb {
1543dd4f32aeSBjoern A. Zeeb int ret;
1544dd4f32aeSBjoern A. Zeeb
1545dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_attach(ab);
1546dd4f32aeSBjoern A. Zeeb if (ret) {
1547dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1548*28348caeSBjoern A. Zeeb return ret;
1549dd4f32aeSBjoern A. Zeeb }
1550dd4f32aeSBjoern A. Zeeb
1551dd4f32aeSBjoern A. Zeeb ret = ath11k_htc_init(ab);
1552dd4f32aeSBjoern A. Zeeb if (ret) {
1553dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to init htc: %d\n", ret);
1554dd4f32aeSBjoern A. Zeeb goto err_wmi_detach;
1555dd4f32aeSBjoern A. Zeeb }
1556dd4f32aeSBjoern A. Zeeb
1557dd4f32aeSBjoern A. Zeeb ret = ath11k_hif_start(ab);
1558dd4f32aeSBjoern A. Zeeb if (ret) {
1559dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to start HIF: %d\n", ret);
1560dd4f32aeSBjoern A. Zeeb goto err_wmi_detach;
1561dd4f32aeSBjoern A. Zeeb }
1562dd4f32aeSBjoern A. Zeeb
1563dd4f32aeSBjoern A. Zeeb ret = ath11k_htc_wait_target(&ab->htc);
1564dd4f32aeSBjoern A. Zeeb if (ret) {
1565dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1566dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1567dd4f32aeSBjoern A. Zeeb }
1568dd4f32aeSBjoern A. Zeeb
1569dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_htt_connect(&ab->dp);
1570dd4f32aeSBjoern A. Zeeb if (ret) {
1571dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1572dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1573dd4f32aeSBjoern A. Zeeb }
1574dd4f32aeSBjoern A. Zeeb
1575dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_connect(ab);
1576dd4f32aeSBjoern A. Zeeb if (ret) {
1577dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1578dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1579dd4f32aeSBjoern A. Zeeb }
1580dd4f32aeSBjoern A. Zeeb
1581dd4f32aeSBjoern A. Zeeb ret = ath11k_htc_start(&ab->htc);
1582dd4f32aeSBjoern A. Zeeb if (ret) {
1583dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to start HTC: %d\n", ret);
1584dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1585dd4f32aeSBjoern A. Zeeb }
1586dd4f32aeSBjoern A. Zeeb
1587dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_wait_for_service_ready(ab);
1588dd4f32aeSBjoern A. Zeeb if (ret) {
1589dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1590dd4f32aeSBjoern A. Zeeb ret);
1591dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1592dd4f32aeSBjoern A. Zeeb }
1593dd4f32aeSBjoern A. Zeeb
1594dd4f32aeSBjoern A. Zeeb ret = ath11k_mac_allocate(ab);
1595dd4f32aeSBjoern A. Zeeb if (ret) {
1596dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1597dd4f32aeSBjoern A. Zeeb ret);
1598dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1599dd4f32aeSBjoern A. Zeeb }
1600dd4f32aeSBjoern A. Zeeb
1601dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_pre_alloc(ab);
1602dd4f32aeSBjoern A. Zeeb
1603dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_pdev_reo_setup(ab);
1604dd4f32aeSBjoern A. Zeeb if (ret) {
1605dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1606dd4f32aeSBjoern A. Zeeb goto err_mac_destroy;
1607dd4f32aeSBjoern A. Zeeb }
1608dd4f32aeSBjoern A. Zeeb
1609dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_cmd_init(ab);
1610dd4f32aeSBjoern A. Zeeb if (ret) {
1611dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1612dd4f32aeSBjoern A. Zeeb goto err_reo_cleanup;
1613dd4f32aeSBjoern A. Zeeb }
1614dd4f32aeSBjoern A. Zeeb
1615dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_wait_for_unified_ready(ab);
1616dd4f32aeSBjoern A. Zeeb if (ret) {
1617dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1618dd4f32aeSBjoern A. Zeeb ret);
1619dd4f32aeSBjoern A. Zeeb goto err_reo_cleanup;
1620dd4f32aeSBjoern A. Zeeb }
1621dd4f32aeSBjoern A. Zeeb
1622dd4f32aeSBjoern A. Zeeb /* put hardware to DBS mode */
1623*28348caeSBjoern A. Zeeb if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1624dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1625dd4f32aeSBjoern A. Zeeb if (ret) {
1626dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1627dd4f32aeSBjoern A. Zeeb goto err_hif_stop;
1628dd4f32aeSBjoern A. Zeeb }
1629dd4f32aeSBjoern A. Zeeb }
1630dd4f32aeSBjoern A. Zeeb
1631dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1632dd4f32aeSBjoern A. Zeeb if (ret) {
1633dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to send htt version request message: %d\n",
1634dd4f32aeSBjoern A. Zeeb ret);
1635dd4f32aeSBjoern A. Zeeb goto err_reo_cleanup;
1636dd4f32aeSBjoern A. Zeeb }
1637dd4f32aeSBjoern A. Zeeb
1638dd4f32aeSBjoern A. Zeeb return 0;
1639dd4f32aeSBjoern A. Zeeb
1640dd4f32aeSBjoern A. Zeeb err_reo_cleanup:
1641dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_reo_cleanup(ab);
1642dd4f32aeSBjoern A. Zeeb err_mac_destroy:
1643dd4f32aeSBjoern A. Zeeb ath11k_mac_destroy(ab);
1644dd4f32aeSBjoern A. Zeeb err_hif_stop:
1645dd4f32aeSBjoern A. Zeeb ath11k_hif_stop(ab);
1646dd4f32aeSBjoern A. Zeeb err_wmi_detach:
1647dd4f32aeSBjoern A. Zeeb ath11k_wmi_detach(ab);
1648dd4f32aeSBjoern A. Zeeb
1649dd4f32aeSBjoern A. Zeeb return ret;
1650dd4f32aeSBjoern A. Zeeb }
1651dd4f32aeSBjoern A. Zeeb
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1652*28348caeSBjoern A. Zeeb static int ath11k_core_start_firmware(struct ath11k_base *ab,
1653*28348caeSBjoern A. Zeeb enum ath11k_firmware_mode mode)
1654dd4f32aeSBjoern A. Zeeb {
1655*28348caeSBjoern A. Zeeb int ret;
1656dd4f32aeSBjoern A. Zeeb
1657*28348caeSBjoern A. Zeeb ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1658*28348caeSBjoern A. Zeeb &ab->qmi.ce_cfg.shadow_reg_v2_len);
1659dd4f32aeSBjoern A. Zeeb
1660*28348caeSBjoern A. Zeeb ret = ath11k_qmi_firmware_start(ab, mode);
1661*28348caeSBjoern A. Zeeb if (ret) {
1662*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1663dd4f32aeSBjoern A. Zeeb return ret;
1664dd4f32aeSBjoern A. Zeeb }
1665dd4f32aeSBjoern A. Zeeb
1666dd4f32aeSBjoern A. Zeeb return ret;
1667dd4f32aeSBjoern A. Zeeb }
1668dd4f32aeSBjoern A. Zeeb
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1669dd4f32aeSBjoern A. Zeeb int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1670dd4f32aeSBjoern A. Zeeb {
1671dd4f32aeSBjoern A. Zeeb int ret;
1672dd4f32aeSBjoern A. Zeeb
1673*28348caeSBjoern A. Zeeb ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1674*28348caeSBjoern A. Zeeb if (ret) {
1675*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to start firmware: %d\n", ret);
1676*28348caeSBjoern A. Zeeb return ret;
1677*28348caeSBjoern A. Zeeb }
1678*28348caeSBjoern A. Zeeb
1679dd4f32aeSBjoern A. Zeeb ret = ath11k_ce_init_pipes(ab);
1680dd4f32aeSBjoern A. Zeeb if (ret) {
1681dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1682*28348caeSBjoern A. Zeeb goto err_firmware_stop;
1683dd4f32aeSBjoern A. Zeeb }
1684dd4f32aeSBjoern A. Zeeb
1685dd4f32aeSBjoern A. Zeeb ret = ath11k_dp_alloc(ab);
1686dd4f32aeSBjoern A. Zeeb if (ret) {
1687dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to init DP: %d\n", ret);
1688*28348caeSBjoern A. Zeeb goto err_firmware_stop;
1689dd4f32aeSBjoern A. Zeeb }
1690dd4f32aeSBjoern A. Zeeb
1691dd4f32aeSBjoern A. Zeeb switch (ath11k_crypto_mode) {
1692dd4f32aeSBjoern A. Zeeb case ATH11K_CRYPT_MODE_SW:
1693dd4f32aeSBjoern A. Zeeb set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1694dd4f32aeSBjoern A. Zeeb set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1695dd4f32aeSBjoern A. Zeeb break;
1696dd4f32aeSBjoern A. Zeeb case ATH11K_CRYPT_MODE_HW:
1697dd4f32aeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1698dd4f32aeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1699dd4f32aeSBjoern A. Zeeb break;
1700dd4f32aeSBjoern A. Zeeb default:
1701dd4f32aeSBjoern A. Zeeb ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1702dd4f32aeSBjoern A. Zeeb return -EINVAL;
1703dd4f32aeSBjoern A. Zeeb }
1704dd4f32aeSBjoern A. Zeeb
1705dd4f32aeSBjoern A. Zeeb if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1706dd4f32aeSBjoern A. Zeeb set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1707dd4f32aeSBjoern A. Zeeb
1708dd4f32aeSBjoern A. Zeeb mutex_lock(&ab->core_lock);
1709*28348caeSBjoern A. Zeeb ret = ath11k_core_start(ab);
1710dd4f32aeSBjoern A. Zeeb if (ret) {
1711dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to start core: %d\n", ret);
1712dd4f32aeSBjoern A. Zeeb goto err_dp_free;
1713dd4f32aeSBjoern A. Zeeb }
1714dd4f32aeSBjoern A. Zeeb
1715dd4f32aeSBjoern A. Zeeb ret = ath11k_core_pdev_create(ab);
1716dd4f32aeSBjoern A. Zeeb if (ret) {
1717dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1718dd4f32aeSBjoern A. Zeeb goto err_core_stop;
1719dd4f32aeSBjoern A. Zeeb }
1720dd4f32aeSBjoern A. Zeeb ath11k_hif_irq_enable(ab);
1721dd4f32aeSBjoern A. Zeeb mutex_unlock(&ab->core_lock);
1722dd4f32aeSBjoern A. Zeeb
1723dd4f32aeSBjoern A. Zeeb return 0;
1724dd4f32aeSBjoern A. Zeeb
1725dd4f32aeSBjoern A. Zeeb err_core_stop:
1726dd4f32aeSBjoern A. Zeeb ath11k_core_stop(ab);
1727dd4f32aeSBjoern A. Zeeb ath11k_mac_destroy(ab);
1728dd4f32aeSBjoern A. Zeeb err_dp_free:
1729dd4f32aeSBjoern A. Zeeb ath11k_dp_free(ab);
1730dd4f32aeSBjoern A. Zeeb mutex_unlock(&ab->core_lock);
1731*28348caeSBjoern A. Zeeb err_firmware_stop:
1732*28348caeSBjoern A. Zeeb ath11k_qmi_firmware_stop(ab);
1733*28348caeSBjoern A. Zeeb
1734dd4f32aeSBjoern A. Zeeb return ret;
1735dd4f32aeSBjoern A. Zeeb }
1736dd4f32aeSBjoern A. Zeeb
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1737dd4f32aeSBjoern A. Zeeb static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1738dd4f32aeSBjoern A. Zeeb {
1739dd4f32aeSBjoern A. Zeeb int ret;
1740dd4f32aeSBjoern A. Zeeb
1741dd4f32aeSBjoern A. Zeeb mutex_lock(&ab->core_lock);
1742dd4f32aeSBjoern A. Zeeb ath11k_thermal_unregister(ab);
1743dd4f32aeSBjoern A. Zeeb ath11k_hif_irq_disable(ab);
1744dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_free(ab);
1745dd4f32aeSBjoern A. Zeeb ath11k_spectral_deinit(ab);
1746dd4f32aeSBjoern A. Zeeb ath11k_hif_stop(ab);
1747dd4f32aeSBjoern A. Zeeb ath11k_wmi_detach(ab);
1748dd4f32aeSBjoern A. Zeeb ath11k_dp_pdev_reo_cleanup(ab);
1749dd4f32aeSBjoern A. Zeeb mutex_unlock(&ab->core_lock);
1750dd4f32aeSBjoern A. Zeeb
1751dd4f32aeSBjoern A. Zeeb ath11k_dp_free(ab);
1752dd4f32aeSBjoern A. Zeeb ath11k_hal_srng_deinit(ab);
1753dd4f32aeSBjoern A. Zeeb
1754dd4f32aeSBjoern A. Zeeb ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1755dd4f32aeSBjoern A. Zeeb
1756dd4f32aeSBjoern A. Zeeb ret = ath11k_hal_srng_init(ab);
1757dd4f32aeSBjoern A. Zeeb if (ret)
1758dd4f32aeSBjoern A. Zeeb return ret;
1759dd4f32aeSBjoern A. Zeeb
1760dd4f32aeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1761dd4f32aeSBjoern A. Zeeb
1762dd4f32aeSBjoern A. Zeeb ret = ath11k_core_qmi_firmware_ready(ab);
1763dd4f32aeSBjoern A. Zeeb if (ret)
1764dd4f32aeSBjoern A. Zeeb goto err_hal_srng_deinit;
1765dd4f32aeSBjoern A. Zeeb
1766dd4f32aeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1767dd4f32aeSBjoern A. Zeeb
1768dd4f32aeSBjoern A. Zeeb return 0;
1769dd4f32aeSBjoern A. Zeeb
1770dd4f32aeSBjoern A. Zeeb err_hal_srng_deinit:
1771dd4f32aeSBjoern A. Zeeb ath11k_hal_srng_deinit(ab);
1772dd4f32aeSBjoern A. Zeeb return ret;
1773dd4f32aeSBjoern A. Zeeb }
1774dd4f32aeSBjoern A. Zeeb
ath11k_core_halt(struct ath11k * ar)1775dd4f32aeSBjoern A. Zeeb void ath11k_core_halt(struct ath11k *ar)
1776dd4f32aeSBjoern A. Zeeb {
1777dd4f32aeSBjoern A. Zeeb struct ath11k_base *ab = ar->ab;
1778dd4f32aeSBjoern A. Zeeb
1779dd4f32aeSBjoern A. Zeeb lockdep_assert_held(&ar->conf_mutex);
1780dd4f32aeSBjoern A. Zeeb
1781dd4f32aeSBjoern A. Zeeb ar->num_created_vdevs = 0;
1782dd4f32aeSBjoern A. Zeeb ar->allocated_vdev_map = 0;
1783dd4f32aeSBjoern A. Zeeb
1784dd4f32aeSBjoern A. Zeeb ath11k_mac_scan_finish(ar);
1785dd4f32aeSBjoern A. Zeeb ath11k_mac_peer_cleanup_all(ar);
1786dd4f32aeSBjoern A. Zeeb cancel_delayed_work_sync(&ar->scan.timeout);
1787dd4f32aeSBjoern A. Zeeb cancel_work_sync(&ar->regd_update_work);
1788dd4f32aeSBjoern A. Zeeb cancel_work_sync(&ab->update_11d_work);
1789dd4f32aeSBjoern A. Zeeb
1790dd4f32aeSBjoern A. Zeeb rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1791dd4f32aeSBjoern A. Zeeb synchronize_rcu();
1792dd4f32aeSBjoern A. Zeeb INIT_LIST_HEAD(&ar->arvifs);
1793dd4f32aeSBjoern A. Zeeb idr_init(&ar->txmgmt_idr);
1794dd4f32aeSBjoern A. Zeeb }
1795dd4f32aeSBjoern A. Zeeb
ath11k_update_11d(struct work_struct * work)1796dd4f32aeSBjoern A. Zeeb static void ath11k_update_11d(struct work_struct *work)
1797dd4f32aeSBjoern A. Zeeb {
1798dd4f32aeSBjoern A. Zeeb struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1799dd4f32aeSBjoern A. Zeeb struct ath11k *ar;
1800dd4f32aeSBjoern A. Zeeb struct ath11k_pdev *pdev;
1801dd4f32aeSBjoern A. Zeeb struct wmi_set_current_country_params set_current_param = {};
1802dd4f32aeSBjoern A. Zeeb int ret, i;
1803dd4f32aeSBjoern A. Zeeb
1804dd4f32aeSBjoern A. Zeeb spin_lock_bh(&ab->base_lock);
1805dd4f32aeSBjoern A. Zeeb memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1806dd4f32aeSBjoern A. Zeeb spin_unlock_bh(&ab->base_lock);
1807dd4f32aeSBjoern A. Zeeb
1808dd4f32aeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1809dd4f32aeSBjoern A. Zeeb set_current_param.alpha2[0],
1810dd4f32aeSBjoern A. Zeeb set_current_param.alpha2[1]);
1811dd4f32aeSBjoern A. Zeeb
1812dd4f32aeSBjoern A. Zeeb for (i = 0; i < ab->num_radios; i++) {
1813dd4f32aeSBjoern A. Zeeb pdev = &ab->pdevs[i];
1814dd4f32aeSBjoern A. Zeeb ar = pdev->ar;
1815dd4f32aeSBjoern A. Zeeb
1816*28348caeSBjoern A. Zeeb memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1817dd4f32aeSBjoern A. Zeeb ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1818dd4f32aeSBjoern A. Zeeb if (ret)
1819dd4f32aeSBjoern A. Zeeb ath11k_warn(ar->ab,
1820dd4f32aeSBjoern A. Zeeb "pdev id %d failed set current country code: %d\n",
1821dd4f32aeSBjoern A. Zeeb i, ret);
1822dd4f32aeSBjoern A. Zeeb }
1823dd4f32aeSBjoern A. Zeeb }
1824dd4f32aeSBjoern A. Zeeb
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)1825*28348caeSBjoern A. Zeeb void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1826dd4f32aeSBjoern A. Zeeb {
1827dd4f32aeSBjoern A. Zeeb struct ath11k *ar;
1828dd4f32aeSBjoern A. Zeeb struct ath11k_pdev *pdev;
1829*28348caeSBjoern A. Zeeb int i;
1830dd4f32aeSBjoern A. Zeeb
1831dd4f32aeSBjoern A. Zeeb spin_lock_bh(&ab->base_lock);
1832dd4f32aeSBjoern A. Zeeb ab->stats.fw_crash_counter++;
1833dd4f32aeSBjoern A. Zeeb spin_unlock_bh(&ab->base_lock);
1834dd4f32aeSBjoern A. Zeeb
1835dd4f32aeSBjoern A. Zeeb for (i = 0; i < ab->num_radios; i++) {
1836dd4f32aeSBjoern A. Zeeb pdev = &ab->pdevs[i];
1837dd4f32aeSBjoern A. Zeeb ar = pdev->ar;
1838*28348caeSBjoern A. Zeeb if (!ar || ar->state == ATH11K_STATE_OFF ||
1839*28348caeSBjoern A. Zeeb ar->state == ATH11K_STATE_FTM)
1840dd4f32aeSBjoern A. Zeeb continue;
1841dd4f32aeSBjoern A. Zeeb
1842dd4f32aeSBjoern A. Zeeb ieee80211_stop_queues(ar->hw);
1843dd4f32aeSBjoern A. Zeeb ath11k_mac_drain_tx(ar);
1844*28348caeSBjoern A. Zeeb ar->state_11d = ATH11K_11D_IDLE;
1845*28348caeSBjoern A. Zeeb complete(&ar->completed_11d_scan);
1846dd4f32aeSBjoern A. Zeeb complete(&ar->scan.started);
1847*28348caeSBjoern A. Zeeb complete_all(&ar->scan.completed);
1848*28348caeSBjoern A. Zeeb complete(&ar->scan.on_channel);
1849dd4f32aeSBjoern A. Zeeb complete(&ar->peer_assoc_done);
1850dd4f32aeSBjoern A. Zeeb complete(&ar->peer_delete_done);
1851dd4f32aeSBjoern A. Zeeb complete(&ar->install_key_done);
1852dd4f32aeSBjoern A. Zeeb complete(&ar->vdev_setup_done);
1853dd4f32aeSBjoern A. Zeeb complete(&ar->vdev_delete_done);
1854dd4f32aeSBjoern A. Zeeb complete(&ar->bss_survey_done);
1855dd4f32aeSBjoern A. Zeeb complete(&ar->thermal.wmi_sync);
1856dd4f32aeSBjoern A. Zeeb
1857dd4f32aeSBjoern A. Zeeb wake_up(&ar->dp.tx_empty_waitq);
1858dd4f32aeSBjoern A. Zeeb idr_for_each(&ar->txmgmt_idr,
1859dd4f32aeSBjoern A. Zeeb ath11k_mac_tx_mgmt_pending_free, ar);
1860dd4f32aeSBjoern A. Zeeb idr_destroy(&ar->txmgmt_idr);
1861dd4f32aeSBjoern A. Zeeb wake_up(&ar->txmgmt_empty_waitq);
1862*28348caeSBjoern A. Zeeb
1863*28348caeSBjoern A. Zeeb ar->monitor_vdev_id = -1;
1864*28348caeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
1865*28348caeSBjoern A. Zeeb clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
1866dd4f32aeSBjoern A. Zeeb }
1867dd4f32aeSBjoern A. Zeeb
1868dd4f32aeSBjoern A. Zeeb wake_up(&ab->wmi_ab.tx_credits_wq);
1869dd4f32aeSBjoern A. Zeeb wake_up(&ab->peer_mapping_wq);
1870dd4f32aeSBjoern A. Zeeb
1871*28348caeSBjoern A. Zeeb reinit_completion(&ab->driver_recovery);
1872dd4f32aeSBjoern A. Zeeb }
1873dd4f32aeSBjoern A. Zeeb
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)1874*28348caeSBjoern A. Zeeb static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
1875*28348caeSBjoern A. Zeeb {
1876*28348caeSBjoern A. Zeeb struct ath11k *ar;
1877*28348caeSBjoern A. Zeeb struct ath11k_pdev *pdev;
1878*28348caeSBjoern A. Zeeb int i;
1879*28348caeSBjoern A. Zeeb
1880dd4f32aeSBjoern A. Zeeb for (i = 0; i < ab->num_radios; i++) {
1881dd4f32aeSBjoern A. Zeeb pdev = &ab->pdevs[i];
1882dd4f32aeSBjoern A. Zeeb ar = pdev->ar;
1883dd4f32aeSBjoern A. Zeeb if (!ar || ar->state == ATH11K_STATE_OFF)
1884dd4f32aeSBjoern A. Zeeb continue;
1885dd4f32aeSBjoern A. Zeeb
1886dd4f32aeSBjoern A. Zeeb mutex_lock(&ar->conf_mutex);
1887dd4f32aeSBjoern A. Zeeb
1888dd4f32aeSBjoern A. Zeeb switch (ar->state) {
1889dd4f32aeSBjoern A. Zeeb case ATH11K_STATE_ON:
1890dd4f32aeSBjoern A. Zeeb ar->state = ATH11K_STATE_RESTARTING;
1891dd4f32aeSBjoern A. Zeeb ath11k_core_halt(ar);
1892dd4f32aeSBjoern A. Zeeb ieee80211_restart_hw(ar->hw);
1893dd4f32aeSBjoern A. Zeeb break;
1894dd4f32aeSBjoern A. Zeeb case ATH11K_STATE_OFF:
1895dd4f32aeSBjoern A. Zeeb ath11k_warn(ab,
1896dd4f32aeSBjoern A. Zeeb "cannot restart radio %d that hasn't been started\n",
1897dd4f32aeSBjoern A. Zeeb i);
1898dd4f32aeSBjoern A. Zeeb break;
1899dd4f32aeSBjoern A. Zeeb case ATH11K_STATE_RESTARTING:
1900dd4f32aeSBjoern A. Zeeb break;
1901dd4f32aeSBjoern A. Zeeb case ATH11K_STATE_RESTARTED:
1902dd4f32aeSBjoern A. Zeeb ar->state = ATH11K_STATE_WEDGED;
1903dd4f32aeSBjoern A. Zeeb fallthrough;
1904dd4f32aeSBjoern A. Zeeb case ATH11K_STATE_WEDGED:
1905dd4f32aeSBjoern A. Zeeb ath11k_warn(ab,
1906dd4f32aeSBjoern A. Zeeb "device is wedged, will not restart radio %d\n", i);
1907dd4f32aeSBjoern A. Zeeb break;
1908*28348caeSBjoern A. Zeeb case ATH11K_STATE_FTM:
1909*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
1910*28348caeSBjoern A. Zeeb "fw mode reset done radio %d\n", i);
1911*28348caeSBjoern A. Zeeb break;
1912dd4f32aeSBjoern A. Zeeb }
1913*28348caeSBjoern A. Zeeb
1914dd4f32aeSBjoern A. Zeeb mutex_unlock(&ar->conf_mutex);
1915dd4f32aeSBjoern A. Zeeb }
1916dd4f32aeSBjoern A. Zeeb complete(&ab->driver_recovery);
1917dd4f32aeSBjoern A. Zeeb }
1918dd4f32aeSBjoern A. Zeeb
ath11k_core_restart(struct work_struct * work)1919*28348caeSBjoern A. Zeeb static void ath11k_core_restart(struct work_struct *work)
1920*28348caeSBjoern A. Zeeb {
1921*28348caeSBjoern A. Zeeb struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
1922*28348caeSBjoern A. Zeeb int ret;
1923*28348caeSBjoern A. Zeeb
1924*28348caeSBjoern A. Zeeb ret = ath11k_core_reconfigure_on_crash(ab);
1925*28348caeSBjoern A. Zeeb if (ret) {
1926*28348caeSBjoern A. Zeeb ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
1927*28348caeSBjoern A. Zeeb return;
1928*28348caeSBjoern A. Zeeb }
1929*28348caeSBjoern A. Zeeb
1930*28348caeSBjoern A. Zeeb if (ab->is_reset)
1931*28348caeSBjoern A. Zeeb complete_all(&ab->reconfigure_complete);
1932*28348caeSBjoern A. Zeeb
1933*28348caeSBjoern A. Zeeb if (!ab->is_reset)
1934*28348caeSBjoern A. Zeeb ath11k_core_post_reconfigure_recovery(ab);
1935*28348caeSBjoern A. Zeeb }
1936*28348caeSBjoern A. Zeeb
ath11k_core_reset(struct work_struct * work)1937*28348caeSBjoern A. Zeeb static void ath11k_core_reset(struct work_struct *work)
1938*28348caeSBjoern A. Zeeb {
1939*28348caeSBjoern A. Zeeb struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
1940*28348caeSBjoern A. Zeeb int reset_count, fail_cont_count;
1941*28348caeSBjoern A. Zeeb long time_left;
1942*28348caeSBjoern A. Zeeb
1943*28348caeSBjoern A. Zeeb if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
1944*28348caeSBjoern A. Zeeb ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
1945*28348caeSBjoern A. Zeeb return;
1946*28348caeSBjoern A. Zeeb }
1947*28348caeSBjoern A. Zeeb
1948*28348caeSBjoern A. Zeeb /* Sometimes the recovery will fail and then the next all recovery fail,
1949*28348caeSBjoern A. Zeeb * this is to avoid infinite recovery since it can not recovery success.
1950*28348caeSBjoern A. Zeeb */
1951*28348caeSBjoern A. Zeeb fail_cont_count = atomic_read(&ab->fail_cont_count);
1952*28348caeSBjoern A. Zeeb
1953*28348caeSBjoern A. Zeeb if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
1954*28348caeSBjoern A. Zeeb return;
1955*28348caeSBjoern A. Zeeb
1956*28348caeSBjoern A. Zeeb if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
1957*28348caeSBjoern A. Zeeb time_before(jiffies, ab->reset_fail_timeout))
1958*28348caeSBjoern A. Zeeb return;
1959*28348caeSBjoern A. Zeeb
1960*28348caeSBjoern A. Zeeb reset_count = atomic_inc_return(&ab->reset_count);
1961*28348caeSBjoern A. Zeeb
1962*28348caeSBjoern A. Zeeb if (reset_count > 1) {
1963*28348caeSBjoern A. Zeeb /* Sometimes it happened another reset worker before the previous one
1964*28348caeSBjoern A. Zeeb * completed, then the second reset worker will destroy the previous one,
1965*28348caeSBjoern A. Zeeb * thus below is to avoid that.
1966*28348caeSBjoern A. Zeeb */
1967*28348caeSBjoern A. Zeeb ath11k_warn(ab, "already resetting count %d\n", reset_count);
1968*28348caeSBjoern A. Zeeb
1969*28348caeSBjoern A. Zeeb reinit_completion(&ab->reset_complete);
1970*28348caeSBjoern A. Zeeb time_left = wait_for_completion_timeout(&ab->reset_complete,
1971*28348caeSBjoern A. Zeeb ATH11K_RESET_TIMEOUT_HZ);
1972*28348caeSBjoern A. Zeeb
1973*28348caeSBjoern A. Zeeb if (time_left) {
1974*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
1975*28348caeSBjoern A. Zeeb atomic_dec(&ab->reset_count);
1976*28348caeSBjoern A. Zeeb return;
1977*28348caeSBjoern A. Zeeb }
1978*28348caeSBjoern A. Zeeb
1979*28348caeSBjoern A. Zeeb ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
1980*28348caeSBjoern A. Zeeb /* Record the continuous recovery fail count when recovery failed*/
1981*28348caeSBjoern A. Zeeb atomic_inc(&ab->fail_cont_count);
1982*28348caeSBjoern A. Zeeb }
1983*28348caeSBjoern A. Zeeb
1984*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
1985*28348caeSBjoern A. Zeeb
1986*28348caeSBjoern A. Zeeb ab->is_reset = true;
1987*28348caeSBjoern A. Zeeb atomic_set(&ab->recovery_count, 0);
1988*28348caeSBjoern A. Zeeb reinit_completion(&ab->recovery_start);
1989*28348caeSBjoern A. Zeeb atomic_set(&ab->recovery_start_count, 0);
1990*28348caeSBjoern A. Zeeb
1991*28348caeSBjoern A. Zeeb ath11k_core_pre_reconfigure_recovery(ab);
1992*28348caeSBjoern A. Zeeb
1993*28348caeSBjoern A. Zeeb reinit_completion(&ab->reconfigure_complete);
1994*28348caeSBjoern A. Zeeb ath11k_core_post_reconfigure_recovery(ab);
1995*28348caeSBjoern A. Zeeb
1996*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
1997*28348caeSBjoern A. Zeeb
1998*28348caeSBjoern A. Zeeb time_left = wait_for_completion_timeout(&ab->recovery_start,
1999*28348caeSBjoern A. Zeeb ATH11K_RECOVER_START_TIMEOUT_HZ);
2000*28348caeSBjoern A. Zeeb
2001*28348caeSBjoern A. Zeeb ath11k_hif_power_down(ab);
2002*28348caeSBjoern A. Zeeb ath11k_hif_power_up(ab);
2003*28348caeSBjoern A. Zeeb
2004*28348caeSBjoern A. Zeeb ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2005*28348caeSBjoern A. Zeeb }
2006*28348caeSBjoern A. Zeeb
ath11k_init_hw_params(struct ath11k_base * ab)2007dd4f32aeSBjoern A. Zeeb static int ath11k_init_hw_params(struct ath11k_base *ab)
2008dd4f32aeSBjoern A. Zeeb {
2009dd4f32aeSBjoern A. Zeeb const struct ath11k_hw_params *hw_params = NULL;
2010dd4f32aeSBjoern A. Zeeb int i;
2011dd4f32aeSBjoern A. Zeeb
2012dd4f32aeSBjoern A. Zeeb for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2013dd4f32aeSBjoern A. Zeeb hw_params = &ath11k_hw_params[i];
2014dd4f32aeSBjoern A. Zeeb
2015dd4f32aeSBjoern A. Zeeb if (hw_params->hw_rev == ab->hw_rev)
2016dd4f32aeSBjoern A. Zeeb break;
2017dd4f32aeSBjoern A. Zeeb }
2018dd4f32aeSBjoern A. Zeeb
2019dd4f32aeSBjoern A. Zeeb if (i == ARRAY_SIZE(ath11k_hw_params)) {
2020dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2021dd4f32aeSBjoern A. Zeeb return -EINVAL;
2022dd4f32aeSBjoern A. Zeeb }
2023dd4f32aeSBjoern A. Zeeb
2024dd4f32aeSBjoern A. Zeeb ab->hw_params = *hw_params;
2025dd4f32aeSBjoern A. Zeeb
2026dd4f32aeSBjoern A. Zeeb ath11k_info(ab, "%s\n", ab->hw_params.name);
2027dd4f32aeSBjoern A. Zeeb
2028dd4f32aeSBjoern A. Zeeb return 0;
2029dd4f32aeSBjoern A. Zeeb }
2030dd4f32aeSBjoern A. Zeeb
ath11k_core_pre_init(struct ath11k_base * ab)2031dd4f32aeSBjoern A. Zeeb int ath11k_core_pre_init(struct ath11k_base *ab)
2032dd4f32aeSBjoern A. Zeeb {
2033dd4f32aeSBjoern A. Zeeb int ret;
2034dd4f32aeSBjoern A. Zeeb
2035dd4f32aeSBjoern A. Zeeb ret = ath11k_init_hw_params(ab);
2036dd4f32aeSBjoern A. Zeeb if (ret) {
2037dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to get hw params: %d\n", ret);
2038dd4f32aeSBjoern A. Zeeb return ret;
2039dd4f32aeSBjoern A. Zeeb }
2040dd4f32aeSBjoern A. Zeeb
2041dd4f32aeSBjoern A. Zeeb return 0;
2042dd4f32aeSBjoern A. Zeeb }
2043dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_pre_init);
2044dd4f32aeSBjoern A. Zeeb
ath11k_core_init(struct ath11k_base * ab)2045dd4f32aeSBjoern A. Zeeb int ath11k_core_init(struct ath11k_base *ab)
2046dd4f32aeSBjoern A. Zeeb {
2047dd4f32aeSBjoern A. Zeeb int ret;
2048dd4f32aeSBjoern A. Zeeb
2049dd4f32aeSBjoern A. Zeeb ret = ath11k_core_soc_create(ab);
2050dd4f32aeSBjoern A. Zeeb if (ret) {
2051dd4f32aeSBjoern A. Zeeb ath11k_err(ab, "failed to create soc core: %d\n", ret);
2052dd4f32aeSBjoern A. Zeeb return ret;
2053dd4f32aeSBjoern A. Zeeb }
2054dd4f32aeSBjoern A. Zeeb
2055dd4f32aeSBjoern A. Zeeb return 0;
2056dd4f32aeSBjoern A. Zeeb }
2057dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_init);
2058dd4f32aeSBjoern A. Zeeb
ath11k_core_deinit(struct ath11k_base * ab)2059dd4f32aeSBjoern A. Zeeb void ath11k_core_deinit(struct ath11k_base *ab)
2060dd4f32aeSBjoern A. Zeeb {
2061dd4f32aeSBjoern A. Zeeb mutex_lock(&ab->core_lock);
2062dd4f32aeSBjoern A. Zeeb
2063dd4f32aeSBjoern A. Zeeb ath11k_core_pdev_destroy(ab);
2064dd4f32aeSBjoern A. Zeeb ath11k_core_stop(ab);
2065dd4f32aeSBjoern A. Zeeb
2066dd4f32aeSBjoern A. Zeeb mutex_unlock(&ab->core_lock);
2067dd4f32aeSBjoern A. Zeeb
2068dd4f32aeSBjoern A. Zeeb ath11k_hif_power_down(ab);
2069dd4f32aeSBjoern A. Zeeb ath11k_mac_destroy(ab);
2070dd4f32aeSBjoern A. Zeeb ath11k_core_soc_destroy(ab);
2071dd4f32aeSBjoern A. Zeeb }
2072dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_deinit);
2073dd4f32aeSBjoern A. Zeeb
ath11k_core_free(struct ath11k_base * ab)2074dd4f32aeSBjoern A. Zeeb void ath11k_core_free(struct ath11k_base *ab)
2075dd4f32aeSBjoern A. Zeeb {
2076*28348caeSBjoern A. Zeeb destroy_workqueue(ab->workqueue_aux);
2077dd4f32aeSBjoern A. Zeeb destroy_workqueue(ab->workqueue);
2078dd4f32aeSBjoern A. Zeeb
2079dd4f32aeSBjoern A. Zeeb kfree(ab);
2080dd4f32aeSBjoern A. Zeeb }
2081dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_free);
2082dd4f32aeSBjoern A. Zeeb
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2083dd4f32aeSBjoern A. Zeeb struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2084*28348caeSBjoern A. Zeeb enum ath11k_bus bus)
2085dd4f32aeSBjoern A. Zeeb {
2086dd4f32aeSBjoern A. Zeeb struct ath11k_base *ab;
2087dd4f32aeSBjoern A. Zeeb
2088dd4f32aeSBjoern A. Zeeb ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2089dd4f32aeSBjoern A. Zeeb if (!ab)
2090dd4f32aeSBjoern A. Zeeb return NULL;
2091dd4f32aeSBjoern A. Zeeb
2092dd4f32aeSBjoern A. Zeeb init_completion(&ab->driver_recovery);
2093dd4f32aeSBjoern A. Zeeb
2094dd4f32aeSBjoern A. Zeeb ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2095dd4f32aeSBjoern A. Zeeb if (!ab->workqueue)
2096dd4f32aeSBjoern A. Zeeb goto err_sc_free;
2097dd4f32aeSBjoern A. Zeeb
2098*28348caeSBjoern A. Zeeb ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2099*28348caeSBjoern A. Zeeb if (!ab->workqueue_aux)
2100*28348caeSBjoern A. Zeeb goto err_free_wq;
2101*28348caeSBjoern A. Zeeb
2102dd4f32aeSBjoern A. Zeeb mutex_init(&ab->core_lock);
2103*28348caeSBjoern A. Zeeb mutex_init(&ab->tbl_mtx_lock);
2104dd4f32aeSBjoern A. Zeeb spin_lock_init(&ab->base_lock);
2105dd4f32aeSBjoern A. Zeeb mutex_init(&ab->vdev_id_11d_lock);
2106*28348caeSBjoern A. Zeeb init_completion(&ab->reset_complete);
2107*28348caeSBjoern A. Zeeb init_completion(&ab->reconfigure_complete);
2108*28348caeSBjoern A. Zeeb init_completion(&ab->recovery_start);
2109dd4f32aeSBjoern A. Zeeb
2110dd4f32aeSBjoern A. Zeeb INIT_LIST_HEAD(&ab->peers);
2111dd4f32aeSBjoern A. Zeeb init_waitqueue_head(&ab->peer_mapping_wq);
2112dd4f32aeSBjoern A. Zeeb init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2113dd4f32aeSBjoern A. Zeeb init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2114dd4f32aeSBjoern A. Zeeb INIT_WORK(&ab->restart_work, ath11k_core_restart);
2115dd4f32aeSBjoern A. Zeeb INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2116*28348caeSBjoern A. Zeeb INIT_WORK(&ab->reset_work, ath11k_core_reset);
2117dd4f32aeSBjoern A. Zeeb timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2118dd4f32aeSBjoern A. Zeeb init_completion(&ab->htc_suspend);
2119dd4f32aeSBjoern A. Zeeb init_completion(&ab->wow.wakeup_completed);
2120dd4f32aeSBjoern A. Zeeb
2121dd4f32aeSBjoern A. Zeeb ab->dev = dev;
2122dd4f32aeSBjoern A. Zeeb ab->hif.bus = bus;
2123dd4f32aeSBjoern A. Zeeb
2124dd4f32aeSBjoern A. Zeeb return ab;
2125dd4f32aeSBjoern A. Zeeb
2126*28348caeSBjoern A. Zeeb err_free_wq:
2127*28348caeSBjoern A. Zeeb destroy_workqueue(ab->workqueue);
2128dd4f32aeSBjoern A. Zeeb err_sc_free:
2129dd4f32aeSBjoern A. Zeeb kfree(ab);
2130dd4f32aeSBjoern A. Zeeb return NULL;
2131dd4f32aeSBjoern A. Zeeb }
2132dd4f32aeSBjoern A. Zeeb EXPORT_SYMBOL(ath11k_core_alloc);
2133dd4f32aeSBjoern A. Zeeb
2134dd4f32aeSBjoern A. Zeeb MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2135dd4f32aeSBjoern A. Zeeb MODULE_LICENSE("Dual BSD/GPL");
2136