| /freebsd/sys/dev/ata/chipsets/ |
| H A D | ata-nvidia.c | 178 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
195 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
206 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
216 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
285 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
286 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
290 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
300 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
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| H A D | ata-amd.c | 96 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
121 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
151 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
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| H A D | ata-serverworks.c | 130 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
145 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
164 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); in ata_serverworks_chipinit()
357 if (ctlr->chip->cfg1 != SWKS_33) { in ata_serverworks_setmode()
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| H A D | ata-intel.c | 267 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_chipinit()
289 (ctlr->chip->cfg1 & INTEL_ICH5)) in ata_intel_chipinit()
336 if (ctlr->chip->cfg1 & INTEL_ICH5) { in ata_intel_ch_attach()
352 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { in ata_intel_ch_attach()
374 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { in ata_intel_ch_attach()
378 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_ch_attach()
431 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) in ata_intel_reset()
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| H A D | ata-ati.c | 103 switch (ctlr->chip->cfg1) { in ata_ati_probe()
134 if (ctlr->chip->cfg1 == ATI_AHCI) { in ata_ati_chipinit()
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| H A D | ata-via.c | 248 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
250 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
252 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
362 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
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| H A D | ata-jmicron.c | 112 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
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| H A D | ata-marvell.c | 127 if (ctlr->chip->cfg1) { in ata_marvell_chipinit()
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| H A D | ata-acard.c | 98 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
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| H A D | ata-acerlabs.c | 113 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
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| H A D | ata-siliconimage.c | 110 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
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| /freebsd/sys/arm64/freescale/imx/clk/ |
| H A D | imx_clk_frac_pll.c | 116 uint32_t cfg0, cfg1; in imx_clk_frac_pll_recalc() local
123 READ4(clk, sc->offset + CFG1, &cfg1); in imx_clk_frac_pll_recalc()
128 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; in imx_clk_frac_pll_recalc()
129 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; in imx_clk_frac_pll_recalc()
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| /freebsd/sys/dev/bhnd/nvram/ |
| H A D | bhnd_nvram_data_bcmreg.h | 58 #define BCM_NVRAM_CFG1_SDRAM_CFG_FIELD cfg1
64 #define BCM_NVRAM_CFG1_SDRAM_REFRESH_FIELD cfg1
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| H A D | bhnd_nvram_data_bcmvar.h | 66 uint32_t cfg1; /**< sdram_config:16, sdram_refresh:16 */ member
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| H A D | bhnd_nvram_data_bcm.c | 431 .cfg1 = 0, in bhnd_nvram_bcm_serialize()
440 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_CFG, in bhnd_nvram_bcm_serialize()
442 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_REFRESH, in bhnd_nvram_bcm_serialize()
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/ |
| H A D | phy.c | 187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
191 cfg1 = 0x00011414; in mt76x2_configure_tx_delay()
194 cfg1 = 0x00021414; in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | spad_layout.h | 205 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
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| H A D | nvm_cfg.h | 2028 struct nvm_cfg1 cfg1; member
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| /freebsd/sys/netpfil/ipfw/nat64/ |
| H A D | nat64lsn_control.c | 815 #define NAT64LSN_ARE_EQUAL(v) (cfg0->v == cfg1->v)
817 nat64lsn_cmp_configs(struct nat64lsn_cfg *cfg0, struct nat64lsn_cfg *cfg1) in nat64lsn_cmp_configs() argument
820 if ((cfg0->base.flags & cfg1->base.flags & NAT64LSN_ALLOW_SWAPCONF) && in nat64lsn_cmp_configs()
826 &cfg1->base.plat_prefix)) in nat64lsn_cmp_configs()
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| /freebsd/sys/dev/et/ |
| H A D | if_et.c | 498 uint32_t cfg1, cfg2, ctrl; in et_miibus_statchg() local
531 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
532 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | in et_miibus_statchg()
563 cfg1 |= ET_MAC_CFG1_TXFLOW; in et_miibus_statchg()
566 cfg1 |= ET_MAC_CFG1_RXFLOW; in et_miibus_statchg()
572 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; in et_miibus_statchg()
573 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
578 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
579 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == in et_miibus_statchg()
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| /freebsd/sys/dev/ata/ |
| H A D | ata-pci.h | 33 int cfg1; member
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | dp.h | 1573 u32 cfg1; member
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| H A D | debugfs_htt_stats.c | 4672 cfg_params->cfg1 = HTT_STAT_DEFAULT_PEER_REQ_TYPE; in ath11k_prep_htt_stats_cfg_params()
4695 cfg_params->cfg1 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]); in ath11k_prep_htt_stats_cfg_params()
4696 cfg_params->cfg1 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]); in ath11k_prep_htt_stats_cfg_params()
4697 cfg_params->cfg1 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]); in ath11k_prep_htt_stats_cfg_params()
4698 cfg_params->cfg1 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]); in ath11k_prep_htt_stats_cfg_params()
4868 cfg_params.cfg1 = 1 << (cfg_params.cfg0 + type); in ath11k_write_htt_stats_reset()
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| /freebsd/sys/contrib/dev/athk/ath12k/ |
| H A D | dp.h | 1773 u32 cfg1; member
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| H A D | dp_tx.c | 1011 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); in ath12k_dp_tx_htt_h2t_ext_stats_req()
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