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Searched refs:bus_read_4 (Results 1 – 25 of 277) sorted by relevance

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/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.c66 if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) in tmc_start()
71 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) in tmc_start()
75 reg = bus_read_4(sc->res, TMC_STS); in tmc_start()
78 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) in tmc_start()
92 reg = bus_read_4(sc->res, TMC_CTL); in tmc_stop()
97 reg = bus_read_4(sc->res, TMC_STS); in tmc_stop()
112 reg = bus_read_4(sc->res, TMC_STS); in tmc_configure_etf()
122 bus_read_4(sc->res, TMC_STS), in tmc_configure_etf()
123 bus_read_4(sc->res, TMC_CTL), in tmc_configure_etf()
124 bus_read_4(sc->res, TMC_RSZ), in tmc_configure_etf()
[all …]
H A Dcoresight_etm4x.c141 reg = bus_read_4(sc->res, TRCVIIECTLR); in etm_prepare()
183 reg = bus_read_4(sc->res, TRCIDR(1)); in etm_init()
207 reg = bus_read_4(sc->res, TRCSTATR); in etm_enable()
210 if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0) in etm_enable()
230 reg = bus_read_4(sc->res, TRCSTATR); in etm_disable()
H A Dcoresight_funnel.c70 dprintf("Device ID: %x\n", bus_read_4(sc->res, FUNNEL_DEVICEID)); in funnel_init()
86 reg = bus_read_4(sc->res, FUNNEL_FUNCTL); in funnel_enable()
106 reg = bus_read_4(sc->res, FUNNEL_FUNCTL); in funnel_disable()
H A Dcoresight_cpu_debug.c89 reg = bus_read_4(sc->res, EDPRCR); in debug_init()
98 reg = bus_read_4(sc->res, EDPRSR); in debug_init()
/freebsd/sys/powerpc/powermac/
H A Datibl.c170 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
171 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_rreg()
173 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
176 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_rreg()
179 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
192 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
193 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_wreg()
199 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_wreg()
202 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
220 lvds_gen_cntl = bus_read_4(s in atibl_setlevel()
[all...]
/freebsd/sys/dev/sdhci/
H A Dsdhci_xenon.c107 return bus_read_4(sc->mem_res, off); in sdhci_xenon_read_4()
198 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); in sdhci_xenon_phy_init()
215 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); in sdhci_xenon_phy_init()
223 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); in sdhci_xenon_phy_init()
244 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); in sdhci_xenon_phy_set()
252 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); in sdhci_xenon_phy_set()
261 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); in sdhci_xenon_phy_set()
270 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); in sdhci_xenon_phy_set()
276 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); in sdhci_xenon_phy_set()
280 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); in sdhci_xenon_phy_set()
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk3568_combphy.c184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
208 (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) | in rk3568_combphy_enable()
227 (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) | in rk3568_combphy_enable()
232 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
236 (bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) | in rk3568_combphy_enable()
244 (bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) | in rk3568_combphy_enable()
279 (bus_read_4(sc->mem, PHYREG15) & in rk3568_combphy_enable()
299 (bus_read_4(sc->mem, PHYREG33) & in rk3568_combphy_enable()
308 (bus_read_4(sc->mem, PHYREG6) & in rk3568_combphy_enable()
320 (bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) | in rk3568_combphy_enable()
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dlx2160a_clkgen.c188 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x00080, bus_read_4(sc->res, 0x00080)); in lx2160a_clkgen_attach()
189 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x000A0, bus_read_4(sc->res, 0x000A0)); in lx2160a_clkgen_attach()
190 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x10080, bus_read_4(sc->res, 0x10080)); in lx2160a_clkgen_attach()
191 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x100A0, bus_read_4(sc->res, 0x100A0)); in lx2160a_clkgen_attach()
192 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x60080, bus_read_4(sc->res, 0x60080)); in lx2160a_clkgen_attach()
193 printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x600A0, bus_read_4(sc->res, 0x600A0)); in lx2160a_clkgen_attach()
H A Dqoriq_clkgen.c111 *val = le32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
113 *val = be32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
127 reg = le32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_modify_4()
129 reg = be32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_modify_4()
/freebsd/sys/arm/ti/omap4/
H A Domap4_prcm_clks.c528 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_activate()
539 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_activate()
594 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_deactivate()
660 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_accessible()
781 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_gptimer_get_source_freq()
837 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_hsmmc_set_source()
893 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_hsmmc_get_source_freq()
938 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); in omap4_clk_get_sysclk_freq()
999 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); in omap4_clk_get_arm_fclk_freq()
1093 clksel = bus_read_4(clk_mem_res, clksel_reg_off); in omap4_clk_hsusbhost_activate()
[all …]
/freebsd/sys/dev/gpio/
H A Dqoriq_gpio.c114 reg = bus_read_4(sc->sc_mem, GPIO_GPDIR); in qoriq_gpio_pin_configure()
119 reg = bus_read_4(sc->sc_mem, GPIO_GPDIR); in qoriq_gpio_pin_configure()
122 reg = bus_read_4(sc->sc_mem, GPIO_GPODR); in qoriq_gpio_pin_configure()
185 outvals = bus_read_4(sc->sc_mem, GPIO_GPDAT); in qoriq_gpio_pin_set()
204 *value = (bus_read_4(sc->sc_mem, GPIO_GPDAT) >> (31 - pin)) & 1; in qoriq_gpio_pin_get()
221 val = bus_read_4(sc->sc_mem, GPIO_GPDAT); in qoriq_gpio_pin_toggle()
262 hwstate = bus_read_4(sc->sc_mem, GPIO_GPDAT); in qoriq_gpio_pin_access_32()
312 reg = (bus_read_4(sc->sc_mem, GPIO_GPDIR) & ~mask) | dir; in qoriq_gpio_pin_config_32()
315 reg = (bus_read_4(sc->sc_mem, GPIO_GPODR) & ~mask) | odr; in qoriq_gpio_pin_config_32()
/freebsd/sys/dev/qcom_rnd/
H A Dqcom_rnd.c142 reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG); in qcom_rnd_attach()
149 reg = bus_read_4(sc->reg, QCOM_RND_PRNG_LFSR_CFG); in qcom_rnd_attach()
155 reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG); in qcom_rnd_attach()
200 reg = bus_read_4(sc->reg, QCOM_RND_PRNG_STATUS); in qcom_rnd_harvest()
203 reg = bus_read_4(sc->reg, QCOM_RND_PRNG_DATA_OUT); in qcom_rnd_harvest()
/freebsd/sys/dev/acpica/
H A Dacpi_hpet.c143 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); in hpet_get_timecount()
185 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_enable()
199 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_disable()
227 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
245 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
292 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + in hpet_intr_single()
302 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_intr_single()
322 val = bus_read_4(sc->mem_res, HPET_ISR); in hpet_intr()
507 val = bus_read_4(sc->mem_res, HPET_PERIOD); in hpet_attach()
516 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); in hpet_attach()
[all …]
/freebsd/sys/powerpc/powerpc/
H A Dopenpic.c404 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); in openpic_suspend()
406 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i)); in openpic_suspend()
410 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i)); in openpic_suspend()
414 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i)); in openpic_suspend()
415 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i)); in openpic_suspend()
416 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i)); in openpic_suspend()
417 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i)); in openpic_suspend()
422 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY; in openpic_suspend()
435 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); in openpic_resume()
/freebsd/sys/dev/qlxgb/
H A Dqla_reg.h228 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
234 bus_read_4((ha->pci_reg), reg);\
246 bus_read_4((ha->pci_reg), off);\
/freebsd/sys/arm64/broadcom/brcmmdio/
H A Dmdio_mux_iproc.c173 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in iproc_mdio_wait_for_idle()
203 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in brcm_iproc_mdio_op()
208 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); in brcm_iproc_mdio_op()
225 ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; in brcm_iproc_mdio_op()
237 val = bus_read_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET); in brcm_iproc_config()
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipc_slicer.c160 val = bus_read_4(res, ofs); in chipc_slicer_walk()
172 fs_ofs = bus_read_4(res, ofs + 24); in chipc_slicer_walk()
188 fw_len = bus_read_4(res, ofs + 4); in chipc_slicer_walk()
/freebsd/sys/dev/sound/macio/
H A Ddavbus.c181 bus_read_4(d->reg, DAVBUS_CODEC_STATUS))); in burgundy_init()
219 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & in burgundy_write_locked()
348 bus_read_4(d->reg, DAVBUS_CODEC_STATUS))); in screamer_init()
381 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY) in screamer_write_locked()
389 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY) in screamer_write_locked()
582 reg = bus_read_4(d->reg, DAVBUS_SOUND_CTRL); in davbus_cint()
585 status = bus_read_4(d->reg, DAVBUS_CODEC_STATUS); in davbus_cint()
/freebsd/sys/arm/mv/armada38x/
H A Darmada38x_rtc.c316 return (bus_read_4(sc->res[RTC_RES], off)); in mv_rtc_reg_read()
339 val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL); in mv_rtc_configure_bus_a38x()
351 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); in mv_rtc_configure_bus_a8k()
357 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); in mv_rtc_configure_bus_a8k()
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_plx.c121 bus_read_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg))
127 bus_read_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg))
133 bus_read_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \
349 val = bus_read_4(sc->conf_res, 0x360); in ntb_plx_attach()
444 if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678) in ntb_plx_attach()
457 if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678) in ntb_plx_attach()
566 val = bus_read_4(sc->conf_res, reg); in ntb_plx_link_enable()
588 val = bus_read_4(sc->conf_res, reg); in ntb_plx_link_disable()
605 val = bus_read_4(sc->conf_res, reg); in ntb_plx_link_enabled()
900 if (bus_read_4(sc->conf_res, off) == val) in ntb_plx_spad_write()
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_dma.c183 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
191 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
240 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); in bcm_dma_init()
243 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); in bcm_dma_init()
545 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); in bcm_dma_reg_dump()
631 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); in bcm_dma_intr()
647 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); in bcm_dma_intr()
/freebsd/sys/dev/xilinx/
H A Dxlnx_pcib.c113 reg = bus_read_4(sc->res, XLNX_PCIE_RPERRFRR); in xlnx_pcib_clear_err_interrupts()
134 val = bus_read_4(sc->res, XLNX_PCIE_IDR); in xlnx_pcib_intr()
135 mask = bus_read_4(sc->res, XLNX_PCIE_IMR); in xlnx_pcib_intr()
215 reg = bus_read_4(sc->res, msireg); in xlnx_pcib_handle_msi_intr()
293 reg = bus_read_4(sc->res[0], XLNX_PCIE_IDR); in xlnx_pcib_init()
304 reg = bus_read_4(sc->res[0], XLNX_PCIE_RPSCR); in xlnx_pcib_init()
693 reg = bus_read_4(sc->res, msireg); in xlnx_pcib_msi_mask()
/freebsd/sys/powerpc/mpc85xx/
H A Dmpc85xx_gpio.c129 outvals = bus_read_4(sc->out_res, 0); in mpc85xx_gpio_pin_set()
148 *value = (bus_read_4(sc->in_res, 0) >> (31 - pin)) & 1; in mpc85xx_gpio_pin_get()
165 val = bus_read_4(sc->out_res, 0); in mpc85xx_gpio_pin_toggle()
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_reset.c144 reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); in qcom_gcc_ipq4018_hwreset_assert()
167 reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); in qcom_gcc_ipq4018_hwreset_is_asserted()
/freebsd/sys/dev/agp/
H A Dagp_i810.c796 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i810_dump_regs()
807 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i830_dump_regs()
818 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i855_dump_regs()
829 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i915_dump_regs()
842 bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2)); in agp_i965_dump_regs()
913 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & in agp_i915_get_stolen_size()
1098 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); in agp_i965_get_gtt_total_entries()
1135 pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2); in agp_gen5_adjust_pgtbl_size()
1140 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); in agp_gen5_adjust_pgtbl_size()
1214 pgtblctl = bus_read_4(s in agp_i830_install_gatt_init()
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