1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/ktr.h>
34 #include <sys/proc.h>
35 #include <sys/rman.h>
36 #include <sys/sched.h>
37 #include <sys/smp.h>
38
39 #include <machine/bus.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/md_var.h>
42 #include <machine/pio.h>
43 #include <machine/resource.h>
44
45 #include <vm/vm.h>
46 #include <vm/pmap.h>
47
48 #include <machine/openpicreg.h>
49 #include <machine/openpicvar.h>
50
51 #include "pic_if.h"
52
53 #define OPENPIC_NIPIS 4
54
55 /*
56 * Local routines
57 */
58 static int openpic_intr(void *arg);
59
60 static __inline uint32_t
openpic_read(struct openpic_softc * sc,u_int reg)61 openpic_read(struct openpic_softc *sc, u_int reg)
62 {
63 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
64 }
65
66 static __inline void
openpic_write(struct openpic_softc * sc,u_int reg,uint32_t val)67 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
68 {
69 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
70 }
71
72 int
openpic_common_attach(device_t dev,uint32_t node)73 openpic_common_attach(device_t dev, uint32_t node)
74 {
75 struct openpic_softc *sc;
76 u_int cpu, ipi, irq;
77 u_int32_t x;
78
79 sc = device_get_softc(dev);
80 sc->sc_dev = dev;
81
82 sc->sc_rid = 0;
83 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
84 RF_ACTIVE);
85
86 if (sc->sc_memr == NULL) {
87 device_printf(dev, "Could not alloc mem resource!\n");
88 return (ENXIO);
89 }
90
91 sc->sc_bt = rman_get_bustag(sc->sc_memr);
92 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
93
94 /* Reset the PIC */
95 x = openpic_read(sc, OPENPIC_CONFIG);
96 x |= OPENPIC_CONFIG_RESET;
97 openpic_write(sc, OPENPIC_CONFIG, x);
98
99 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
100 powerpc_sync();
101 DELAY(100);
102 }
103
104 /* Check if this is a cascaded PIC */
105 sc->sc_irq = 0;
106 sc->sc_intr = NULL;
107 do {
108 struct resource_list *rl;
109
110 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
111 if (rl == NULL)
112 break;
113 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
114 break;
115
116 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
117 &sc->sc_irq, RF_ACTIVE);
118
119 /* XXX Cascaded PICs pass NULL trapframes! */
120 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
121 openpic_intr, NULL, dev, &sc->sc_icookie);
122 } while (0);
123
124 /* Reset the PIC */
125 x = openpic_read(sc, OPENPIC_CONFIG);
126 x |= OPENPIC_CONFIG_RESET;
127 openpic_write(sc, OPENPIC_CONFIG, x);
128
129 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
130 powerpc_sync();
131 DELAY(100);
132 }
133
134 x = openpic_read(sc, OPENPIC_FEATURE);
135 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
136 case 1:
137 sc->sc_version = "1.0";
138 break;
139 case 2:
140 sc->sc_version = "1.2";
141 break;
142 case 3:
143 sc->sc_version = "1.3";
144 break;
145 default:
146 sc->sc_version = "unknown";
147 break;
148 }
149
150 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
151 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
152 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
153 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
154
155 /*
156 * PSIM seems to report 1 too many IRQs and CPUs
157 */
158 if (sc->sc_psim) {
159 sc->sc_nirq--;
160 sc->sc_ncpu--;
161 }
162
163 if (bootverbose)
164 device_printf(dev,
165 "Version %s, supports %d CPUs and %d irqs\n",
166 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
167
168 /*
169 * Allow more IRQs than what the PIC says it handles. Some Freescale PICs
170 * have MSIs that show up above the PIC's self-described 196 IRQs
171 * (P5020 starts MSI IRQs at 224).
172 */
173 if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
174 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
175
176 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
177 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
178
179 /* Reset and disable all interrupts. */
180 for (irq = 0; irq < sc->sc_nirq; irq++) {
181 x = irq; /* irq == vector. */
182 x |= OPENPIC_IMASK;
183 x |= OPENPIC_POLARITY_NEGATIVE;
184 x |= OPENPIC_SENSE_LEVEL;
185 x |= 8 << OPENPIC_PRIORITY_SHIFT;
186 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
187 }
188
189 /* Reset and disable all IPIs. */
190 for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
191 x = sc->sc_nirq + ipi;
192 x |= OPENPIC_IMASK;
193 x |= 15 << OPENPIC_PRIORITY_SHIFT;
194 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
195 }
196
197 /* we don't need 8259 passthrough mode */
198 x = openpic_read(sc, OPENPIC_CONFIG);
199 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
200 openpic_write(sc, OPENPIC_CONFIG, x);
201
202 /* send all interrupts to cpu 0 */
203 for (irq = 0; irq < sc->sc_nirq; irq++)
204 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
205
206 /* clear all pending interrupts from cpu 0 */
207 for (irq = 0; irq < sc->sc_nirq; irq++) {
208 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
209 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
210 }
211
212 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
213 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
214
215 powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
216
217 /* If this is not a cascaded PIC, it must be the root PIC */
218 if (sc->sc_intr == NULL)
219 root_pic = dev;
220
221 return (0);
222 }
223
224 /*
225 * PIC I/F methods
226 */
227
228 void
openpic_bind(device_t dev,u_int irq,cpuset_t cpumask,void ** priv __unused)229 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
230 {
231 struct openpic_softc *sc;
232 uint32_t mask;
233
234 /* If we aren't directly connected to the CPU, this won't work */
235 if (dev != root_pic)
236 return;
237
238 sc = device_get_softc(dev);
239
240 /*
241 * XXX: openpic_write() is very special and just needs a 32 bits mask.
242 * For the moment, just play dirty and get the first half word.
243 */
244 mask = cpumask.__bits[0] & 0xffffffff;
245 if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
246 int i = mftb() % CPU_COUNT(&cpumask);
247 int cpu, ncpu;
248
249 ncpu = 0;
250 CPU_FOREACH(cpu) {
251 if (!(mask & (1 << cpu)))
252 continue;
253 if (ncpu == i)
254 break;
255 ncpu++;
256 }
257 mask &= (1 << cpu);
258 }
259
260 openpic_write(sc, OPENPIC_IDEST(irq), mask);
261 }
262
263 void
openpic_config(device_t dev,u_int irq,enum intr_trigger trig,enum intr_polarity pol)264 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
265 enum intr_polarity pol)
266 {
267 struct openpic_softc *sc;
268 uint32_t x;
269
270 sc = device_get_softc(dev);
271 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
272 if (pol == INTR_POLARITY_LOW)
273 x &= ~OPENPIC_POLARITY_POSITIVE;
274 else
275 x |= OPENPIC_POLARITY_POSITIVE;
276 if (trig == INTR_TRIGGER_EDGE)
277 x &= ~OPENPIC_SENSE_LEVEL;
278 else
279 x |= OPENPIC_SENSE_LEVEL;
280 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
281 }
282
283 static int
openpic_intr(void * arg)284 openpic_intr(void *arg)
285 {
286 device_t dev = (device_t)(arg);
287
288 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
289 openpic_dispatch(dev, NULL);
290
291 return (FILTER_HANDLED);
292 }
293
294 void
openpic_dispatch(device_t dev,struct trapframe * tf)295 openpic_dispatch(device_t dev, struct trapframe *tf)
296 {
297 struct openpic_softc *sc;
298 u_int cpuid, vector;
299
300 CTR1(KTR_INTR, "%s: got interrupt", __func__);
301
302 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
303
304 sc = device_get_softc(dev);
305 while (1) {
306 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
307 vector &= OPENPIC_VECTOR_MASK;
308 if (vector == 255)
309 break;
310 powerpc_dispatch_intr(vector, tf);
311 }
312 }
313
314 void
openpic_enable(device_t dev,u_int irq,u_int vector,void ** priv __unused)315 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
316 {
317 struct openpic_softc *sc;
318 uint32_t x;
319
320 sc = device_get_softc(dev);
321 if (irq < sc->sc_nirq) {
322 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
323 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
324 x |= vector;
325 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
326 } else {
327 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
328 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
329 x |= vector;
330 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
331 }
332 }
333
334 void
openpic_eoi(device_t dev,u_int irq __unused,void * priv __unused)335 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
336 {
337 struct openpic_softc *sc;
338 u_int cpuid;
339
340 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
341
342 sc = device_get_softc(dev);
343 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
344 }
345
346 void
openpic_ipi(device_t dev,u_int cpu)347 openpic_ipi(device_t dev, u_int cpu)
348 {
349 struct openpic_softc *sc;
350
351 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
352
353 sc = device_get_softc(dev);
354 sched_pin();
355 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
356 1u << cpu);
357 sched_unpin();
358 }
359
360 void
openpic_mask(device_t dev,u_int irq,void * priv __unused)361 openpic_mask(device_t dev, u_int irq, void *priv __unused)
362 {
363 struct openpic_softc *sc;
364 uint32_t x;
365
366 sc = device_get_softc(dev);
367 if (irq < sc->sc_nirq) {
368 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
369 x |= OPENPIC_IMASK;
370 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
371 } else {
372 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
373 x |= OPENPIC_IMASK;
374 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
375 }
376 }
377
378 void
openpic_unmask(device_t dev,u_int irq,void * priv __unused)379 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
380 {
381 struct openpic_softc *sc;
382 uint32_t x;
383
384 sc = device_get_softc(dev);
385 if (irq < sc->sc_nirq) {
386 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
387 x &= ~OPENPIC_IMASK;
388 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
389 } else {
390 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
391 x &= ~OPENPIC_IMASK;
392 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
393 }
394 }
395
396 int
openpic_suspend(device_t dev)397 openpic_suspend(device_t dev)
398 {
399 struct openpic_softc *sc;
400 int i;
401
402 sc = device_get_softc(dev);
403
404 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
405 for (i = 0; i < OPENPIC_NIPIS; i++) {
406 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
407 }
408
409 for (i = 0; i < 4; i++) {
410 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
411 }
412
413 for (i = 0; i < OPENPIC_TIMERS; i++) {
414 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
415 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
416 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
417 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
418 }
419
420 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
421 sc->sc_saved_vectors[i] =
422 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
423
424 return (0);
425 }
426
427 int
openpic_resume(device_t dev)428 openpic_resume(device_t dev)
429 {
430 struct openpic_softc *sc;
431 int i;
432
433 sc = device_get_softc(dev);
434
435 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
436 for (i = 0; i < OPENPIC_NIPIS; i++) {
437 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
438 }
439
440 for (i = 0; i < 4; i++) {
441 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
442 }
443
444 for (i = 0; i < OPENPIC_TIMERS; i++) {
445 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
446 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
447 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
448 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
449 }
450
451 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
452 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
453
454 return (0);
455 }
456