Lines Matching refs:bus_read_4
170 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
171 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_rreg()
173 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
176 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_rreg()
179 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
192 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
193 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_wreg()
199 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_wreg()
202 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
220 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); in atibl_setlevel()
224 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN); in atibl_setlevel()
227 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL); in atibl_setlevel()
267 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); in atibl_getlevel()