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Searched refs:ZERO_EXTEND (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2185 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } }, in getCastInstrCost()
2207 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2208 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2209 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2210 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2211 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2212 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2213 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2214 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
2215 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 2, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp1012 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); in X86TargetLowering()
1508 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1509 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1521 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in X86TargetLowering()
1735 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in X86TargetLowering()
1860 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
1861 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1862 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1873 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
2153 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom); in X86TargetLowering()
[all …]
H A DX86ISelLoweringCall.cpp774 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2174 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
2413 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee); in LowerCall()
2640 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST || in MatchingStackOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp524 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
526 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
528 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
530 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
532 {ISD::ZERO_EXTEND, MVT::i64, MVT::i16, 1}, in getCastInstrCost()
534 {ISD::ZERO_EXTEND, MVT::i64, MVT::i8, 1}, in getCastInstrCost()
542 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
544 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
546 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
551 {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
[all …]
H A DARMSelectionDAGInfo.cpp107 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitSpecializedLibcall()
H A DARMISelLowering.cpp165 DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in handleCMSEValue()
489 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in addMVEVectorTypes()
490 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in addMVEVectorTypes()
491 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in addMVEVectorTypes()
1035 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, in ARMTargetLowering()
2195 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, in MoveFromHPR()
2518 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
3251 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) { in LowerReturn()
6008 CastOpc = ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
6263 DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), MVT::i32, Op)); in ExpandBITCAST()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h808 ZERO_EXTEND, enumerator
1646 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || in isExtOpcode()
H A DSelectionDAG.h925 case ISD::ZERO_EXTEND:
927 return ISD::ZERO_EXTEND;
941 case ISD::ZERO_EXTEND:
971 case ISD::ZERO_EXTEND:
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1455 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1908 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
2040 case ISD::ZERO_EXTEND: in combine()
2540 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2695 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADDLike()
2698 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not); in visitADDLike()
3065 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
3113 if (N1.getOpcode() == ISD::ZERO_EXTEND) in foldAddSubMasked1()
3194 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADDLikeCommutative()
3773 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
[all …]
H A DLegalizeDAG.cpp1669 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
2905 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
2914 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3194 case ISD::ZERO_EXTEND: in ExpandNode()
3822 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]); in ExpandNode()
3864 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) && in ExpandNode()
3870 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); in ExpandNode()
4000 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); in ExpandNode()
4835 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ConvertNodeToLibcall()
5123 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
H A DLegalizeIntegerTypes.cpp157 case ISD::ZERO_EXTEND: in PromoteIntegerResult()
380 case ISD::ZERO_EXTEND: in PromoteIntRes_Atomic0()
441 case ISD::ZERO_EXTEND: in PromoteIntRes_AtomicCmpSwap()
641 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
926 if (N->getOpcode() == ISD::ZERO_EXTEND) in PromoteIntRes_INT_EXTEND()
1689 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc); in PromoteIntRes_TRUNCATE()
1877 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); in PromoteIntRes_VAARG()
1879 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); in PromoteIntRes_VAARG()
1968 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; in PromoteIntegerOperand()
2584 return ISD::ZERO_EXTEND; in getExtendForIntVecReduction()
[all …]
H A DTargetLowering.cpp1888 TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift); in SimplifyDemandedBits()
1985 Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift)); in SimplifyDemandedBits()
2423 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits()
2512 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
2702 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); in SimplifyDemandedBits()
3686 case ISD::ZERO_EXTEND: in SimplifyDemandedVectorElts()
3691 if (Op.getOpcode() == ISD::ZERO_EXTEND) { in SimplifyDemandedVectorElts()
4564 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
4624 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && in SimplifySetCC()
4717 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
[all …]
H A DSelectionDAG.cpp313 if (N->getOpcode() == ISD::ZERO_EXTEND) { in isVectorShrinkable()
572 return ISD::ZERO_EXTEND; in getExtForLoadExtType()
1468 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc()
2783 case ISD::ZERO_EXTEND: in isSplatValue()
3813 case ISD::ZERO_EXTEND: { in computeKnownBits()
4186 if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) in computeKnownBits()
4422 if (Val.getOpcode() == ISD::ZERO_EXTEND) in isKnownToBeAPowerOfTwo()
5031 if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) in ComputeNumSignBits()
5307 case ISD::ZERO_EXTEND: in canCreateUndefOrPoison()
5651 case ISD::ZERO_EXTEND: in isKnownNeverZero()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2564 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
2566 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
2568 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
2570 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
2572 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
2574 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
2576 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
2578 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
2777 { ISD::ZERO_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2}, in getCastInstrCost()
2778 { ISD::ZERO_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6}, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp1100 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
2124 setOperationAction(ISD::ZERO_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
4009 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in getAArch64XALUOOp()
4658 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
4707 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
5062 return N.getOpcode() == ISD::ZERO_EXTEND || in isZeroExtended()
5135 RMValue = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, RMValue); in LowerSET_ROUNDING()
6248 unsigned ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerMGATHER()
6338 unsigned ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerMSCATTER()
6575 ExtType = ISD::ZERO_EXTEND; in LowerLOAD()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp238 setOperationAction(ISD::ZERO_EXTEND, T, Custom); in initializeHVXLowering()
281 setOperationAction(ISD::ZERO_EXTEND, T, Custom); in initializeHVXLowering()
424 setOperationAction(ISD::ZERO_EXTEND, VecTy, Custom); in initializeHVXLowering()
1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth()
1844 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), ResTy, InpV); in LowerHvxAnyExt()
2903 case ISD::ZERO_EXTEND: in CreateTLWrapper()
3191 case ISD::ZERO_EXTEND: in LowerHvxOperation()
3213 case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG); in LowerHvxOperation()
3267 case ISD::ZERO_EXTEND: in ExpandHvxResizeIntoSteps()
3369 case ISD::ZERO_EXTEND in LowerHvxOperationWrapper()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp86 SDValue Op = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), MVT::i64, V); in ReplaceNodeResults()
315 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp306 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1102 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1595 PromoteMULO(ISD::ZERO_EXTEND); in lowerOverflowArithmetic()
2118 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
3543 Carry.getOpcode() == ISD::ZERO_EXTEND || in combineCarryThroughADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp376 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
394 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
917 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
1285 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1342 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
3147 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3148 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp835 setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, in RISCVTargetLowering()
1256 {ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, VT, Custom); in RISCVTargetLowering()
1491 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
5098 V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1); in lowerVECTOR_SHUFFLE()
5100 : DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2); in lowerVECTOR_SHUFFLE()
5484 Exp = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Exp); in lowerCTLZ_CTTZ_ZERO_UNDEF()
6399 case ISD::ZERO_EXTEND: in LowerOperation()
6596 ? ISD::ZERO_EXTEND in LowerOperation()
8458 Vec = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, Vec); in lowerINSERT_VECTOR_ELT()
8681 Vec = DAG.getNode(ISD::ZERO_EXTEND, D in lowerEXTRACT_VECTOR_ELT()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp735 if (Index.getOpcode() == ISD::ZERO_EXTEND) in selectBDVAddr12Only()
878 case ISD::ZERO_EXTEND: in expandRxSBG()
1642 case ISD::ZERO_EXTEND: in Select()
H A DSystemZISelLowering.h644 return ISD::ZERO_EXTEND; in getExtendForAtomicCmpSwapArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1400 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND}); in PPCTargetLowering()
6138 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in LowerCall_32SVR4()
6454 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
7656 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_AIX()
7851 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
8065 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()), in LowerSTORE()
8897 SINT.getOpcode() == ISD::ZERO_EXTEND)) && in LowerINT_TO_FP()
8923 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ? in LowerINT_TO_FP()
9094 DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), in LowerGET_ROUNDING()
11275 SDValue ValLo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal); in LowerATOMIC_LOAD_STORE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp734 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
738 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
741 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
919 ISD::ZERO_EXTEND, in SITargetLowering()
3211 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3767 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6030 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in lowerICMPIntrinsic()
7537 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi); in lowerBUILD_VECTOR()
7545 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
9423 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData); in handleD16VData()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp400 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
698 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
2967 case ISD::ZERO_EXTEND: { in isI32InsnAllUses()
3186 Idx = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Idx); in lowerINSERT_VECTOR_ELT()
3190 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in lowerINSERT_VECTOR_ELT()

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