734     setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},  in SITargetLowering()
738     setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},  in SITargetLowering()
741     setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},  in SITargetLowering()
919                        ISD::ZERO_EXTEND,  in SITargetLowering()
3211       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);  in LowerReturn()
3767       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);  in LowerCall()
6030       ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in lowerICMPIntrinsic()
7537   Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);  in lowerBUILD_VECTOR()
7545   Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);  in lowerBUILD_VECTOR()
9423     SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData);  in handleD16VData()
9474     SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenedIntVT, IntVData);  in handleD16VData()
9826       if (!LHS->isDivergent() && RHS.getOpcode() == ISD::ZERO_EXTEND &&  in LowerINTRINSIC_VOID()
10162     return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op);  in getLoadExtOrTrunc()
11750   case ISD::ZERO_EXTEND:  in calculateSrcByte()
11938   case ISD::ZERO_EXTEND:  in calculateByteProvider()
11958       return Op.getOpcode() == ISD::ZERO_EXTEND  in calculateByteProvider()
12066   case ISD::ZERO_EXTEND: {  in isExtendedFrom16Bits()
12400   if (LHS.getOpcode() == ISD::ZERO_EXTEND &&  in performOrCombine()
12401       RHS.getOpcode() != ISD::ZERO_EXTEND)  in performOrCombine()
12404   if (RHS.getOpcode() == ISD::ZERO_EXTEND) {  in performOrCombine()
14207   if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||  in performAddCombine()
14214   case ISD::ZERO_EXTEND:  in performAddCombine()
14255   case ISD::ZERO_EXTEND:  in performSubCombine()
14609   if (Shift.getOpcode() == ISD::ZERO_EXTEND)  in performCvtF32UByteNCombine()
14724   case ISD::ZERO_EXTEND:  in PerformDAGCombine()