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Searched refs:XLenVT (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td19 def simm12Plus1 : ImmLeaf<XLenVT, [{
26 def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
29 def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
41 def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;
44 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
46 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
48 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
50 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
55 foreach Ty = [PtrVT, XLenVT] in {
56 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty 0))), (SLTIU GPR:$rs1, 1)>;
[all …]
H A DRISCVInstrInfoZb.td47 // XLenVT.
74 def BCLRMask : ImmLeaf<XLenVT, [{
81 def SingleBitSetMask : ImmLeaf<XLenVT, [{
217 def Shifted32OnesMask : IntImmLeaf<XLenVT, [{
226 def sh1add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<1>", [], [], 6>;
227 def sh2add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<2>", [], [], 6>;
228 def sh3add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<3>", [], [], 6>;
237 def sh1add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<1>", [], [], 6>;
238 def sh2add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<2>", [], [], 6>;
239 def sh3add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<3>", [], [], 6>;
[all …]
H A DRISCVInstrInfoXVentana.td32 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
34 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
37 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
39 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
41 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
43 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
H A DRISCVInstrInfoZicond.td39 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
41 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
44 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
46 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
48 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
50 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
H A DRISCVInstrInfoXTHead.td20 SDTCisVT<3, XLenVT>]>;
24 SDTCisVT<3, XLenVT>]>;
556 def : Pat<(add_like_non_imm12 (shl GPR:$rs2, uimm2:$uimm2), (XLenVT GPR:$rs1)),
558 def : Pat<(XLenVT (riscv_shl_add GPR:$rs2, uimm2:$uimm2, GPR:$rs1)),
562 def : Pat<(add_like_non_imm12 sh1add_op:$rs2, (XLenVT GPR:$rs1)),
564 def : Pat<(add_like_non_imm12 sh2add_op:$rs2, (XLenVT GPR:$rs1)),
566 def : Pat<(add_like_non_imm12 sh3add_op:$rs2, (XLenVT GPR:$rs1)),
569 def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy4:$i),
570 (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), CSImm12MulBy4:$i)), 2)>;
571 def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy8:$i),
[all …]
H A DRISCVInstrInfoZa.td71 multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
191 defm : AMOPat<"atomic_swap_i8", "AMOSWAP_B", XLenVT, [HasStdExtZabha]>;
192 defm : AMOPat<"atomic_load_add_i8", "AMOADD_B", XLenVT, [HasStdExtZabha]>;
193 defm : AMOPat<"atomic_load_and_i8", "AMOAND_B", XLenVT, [HasStdExtZabha]>;
194 defm : AMOPat<"atomic_load_or_i8", "AMOOR_B", XLenVT, [HasStdExtZabha]>;
195 defm : AMOPat<"atomic_load_xor_i8", "AMOXOR_B", XLenVT, [HasStdExtZabha]>;
196 defm : AMOPat<"atomic_load_max_i8", "AMOMAX_B", XLenVT, [HasStdExtZabha]>;
197 defm : AMOPat<"atomic_load_min_i8", "AMOMIN_B", XLenVT, [HasStdExtZabha]>;
198 defm : AMOPat<"atomic_load_umax_i8", "AMOMAXU_B", XLenVT, [HasStdExtZabha]>;
199 defm : AMOPat<"atomic_load_umin_i8", "AMOMINU_B", XLenVT, [HasStdExtZabha]>;
[all …]
H A DRISCVInstrInfoXMips.td19 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
139 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
143 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
157 def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),
158 (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
160 def : Pat<(select (riscv_seteq (XLenVT GPR:$rs2)),
161 (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
164 def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
H A DRISCVInstrInfo.td33 def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
84 // condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
85 // The lhs and rhs are XLenVT integers. The true and false values can be
164 SDTCisVT<1, XLenVT>,
165 SDTCisVT<2, XLenVT>]>>;
172 SDTypeProfile<2, 1, [SDTCisVT<0, XLenVT>,
173 SDTCisVT<1, XLenVT>,
235 class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
253 RISCVUImmOp<bitsNum>, ImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);">;
269 RISCVSImmOp<bitsNum>, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);">;
[all …]
H A DRISCVInstrInfoSFB.td21 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
23 (XLenVT GPR:$truev),
40 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
41 (XLenVT GPR:$rhs),
42 cond, (XLenVT GPRNoX0:$truev),
43 (XLenVT GPRNoX0:$falsev)))]>,
197 def : Pat<(XLenVT (abs GPR:$rs1)),
198 (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,
199 (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>;
H A DRISCVInstrInfoXSf.td32 class PayloadOp<int bitsNum> : RISCVOp, TImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);"> {
40 def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
485 SDTCisVT<1, XLenVT>,
493 SDTCisVT<0, XLenVT>]>;
496 SDTCisVT<1, XLenVT>,
500 def SDT_SF_VC_XVV : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>,
506 SDTCisVT<1, XLenVT>,
511 def SDT_SF_VC_XVW : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>,
516 SDTCisVT<1, XLenVT>,
559 (XLenVT op1_kind:$op1),
[all …]
H A DRISCVInstrInfoXRivos.td135 // XLenVT sign extended from the vector element size. VEXTRACT does *not*
146 SDTCisVT<2, XLenVT>,
147 SDTCisVT<3, XLenVT>,
148 SDTCisVT<4, XLenVT>]>>;
176 def : Pat<(XLenVT (ri_vextract (vti.Vector vti.RegClass:$vs2), uimm5:$imm)),
184 (XLenVT timm:$policy))),
187 GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
H A DRISCVISelLowering.cpp124 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering() local
127 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
286 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, XLenVT, in RISCVTargetLowering()
293 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Custom); in RISCVTargetLowering()
296 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
298 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
300 setCondCodeAction(ISD::SETGT, XLenVT, Custom); in RISCVTargetLowering()
301 setCondCodeAction(ISD::SETGE, XLenVT, Expand); in RISCVTargetLowering()
302 setCondCodeAction(ISD::SETUGT, XLenVT, Custom); in RISCVTargetLowering()
303 setCondCodeAction(ISD::SETUGE, XLenVT, Expand); in RISCVTargetLowering()
[all …]
H A DRISCVInstrInfoVVLPatterns.td34 SDTCisVT<4, XLenVT>]>>;
55 SDTCisVT<4, XLenVT>]>;
63 SDTCisVT<5, XLenVT>]>;
74 SDTCisVT<5, XLenVT>,
75 SDTCisVT<6, XLenVT>]>;
81 SDTCisVT<3, XLenVT>]>;
88 SDTCisVT<5, XLenVT>]>;
96 SDTCisVT<5, XLenVT>]>;
105 SDTCisVT<3, XLenVT>]>>;
113 SDTCisVT<2, XLenVT>,
[all …]
H A DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
73 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
76 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
79 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
H A DRISCVInstrInfoZimop.td71 def : Pat<(XLenVT (riscv_mopr GPR:$rs1, (XLenVT i))),
76 def : Pat<(XLenVT (riscv_moprr GPR:$rs1, GPR:$rs2, (XLenVT i))),
H A DRISCVInstrInfoD.td423 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
424 (AND (XLenVT (FLE_D $rs1, $rs2)),
425 (XLenVT (FLE_D $rs2, $rs1)))>;
426 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
427 (AND (XLenVT (FLE_D $rs1, $rs2)),
428 (XLenVT (FLE_D $rs2, $rs1)))>;
430 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
432 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)),
443 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
444 (AND (XLenVT (FLE_D_INX $rs1, $rs2)),
[all …]
H A DRISCVInstrInfoVSDPatterns.td25 (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
37 def : Pat<(type (load (XLenVT GPR:$rs1))),
41 def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)),
116 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))),
301 (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))), cc)),
303 def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))),
466 (wti.Vector (extop2 (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
487 (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
524 (mul_oneuse (wti.Vector (extop1 (vti.Vector (SplatPat (XLenVT GPR:$rs1))))),
541 (vti.Mask true_mask), (XLenVT srcvalue))),
[all …]
H A DRISCVInstrInfoZk.td24 def SDT_RISCVZkByteSelect : SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
25 SDTCisVT<1, XLenVT>,
26 SDTCisVT<2, XLenVT>,
147 : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), byteselect:$imm)),
H A DRISCVInstrInfoZfh.td19 : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, XLenVT>]>;
21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
402 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)),
403 (AND (XLenVT (FLE_H $rs1, $rs2)),
404 (XLenVT (FLE_H $rs2, $rs1)))>;
405 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETOEQ)),
406 (AND (XLenVT (FLE_H $rs1, $rs2)),
407 (XLenVT (FLE_H $rs2, $rs1)))>;
409 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)),
411 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETOEQ)),
[all …]
H A DRISCVInstrInfoF.td26 : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>,
27 SDTCisVT<2, XLenVT>]>;
31 SDTCisVT<3, XLenVT>]>;
33 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
161 def frmarg : Operand<XLenVT> {
183 def frmarglegacy : Operand<XLenVT> {
533 : Pat<(XLenVT (OpNode (vt Ty:$rs1), Ty:$rs2, Cond)), (Inst $rs1, $rs2)>;
677 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
678 (AND (XLenVT (FLE_S $rs1, $rs2)),
679 (XLenVT (FLE_S $rs2, $rs1)))>;
[all …]
H A DRISCVInstrInfoZfbfmin.td32 def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,
39 def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 0, cond,
42 (Select_FPR16_Using_CC_GPR GPR:$lhs, (XLenVT X0),
H A DRISCVCallingConv.cpp334 MVT XLenVT = Subtarget.getXLenVT(); in CC_RISCV() local
440 LocVT = XLenVT; in CC_RISCV()
450 LocVT = XLenVT; in CC_RISCV()
517 LocVT = XLenVT; in CC_RISCV()
568 LocVT = XLenVT; in CC_RISCV()
571 LocVT = XLenVT; in CC_RISCV()
605 assert(((ValVT.isFloatingPoint() && !ValVT.isVector()) || LocVT == XLenVT || in CC_RISCV()
667 MVT XLenVT = Subtarget.getXLenVT(); in CC_RISCV_FastCC() local
689 LocVT = XLenVT; in CC_RISCV_FastCC()
720 LocVT = XLenVT; in CC_RISCV_FastCC()
[all …]
H A DRISCVInstrInfoA.td173 def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
174 def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
175 def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
191 multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
296 def : Pat<(XLenVT (atomic_load_nand_i32_monotonic GPR:$addr, GPR:$incr)),
298 def : Pat<(XLenVT (atomic_load_nand_i32_acquire GPR:$addr, GPR:$incr)),
300 def : Pat<(XLenVT (atomic_load_nand_i32_release GPR:$addr, GPR:$incr)),
302 def : Pat<(XLenVT (atomic_load_nand_i32_acq_rel GPR:$addr, GPR:$incr)),
304 def : Pat<(XLenVT (atomic_load_nand_i32_seq_cst GPR:$addr, GPR:$incr)),
392 ValueType vt = XLenVT> {
H A DRISCVInstrInfoZvk.td18 def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
606 def allonessew8 : ImmLeaf<XLenVT, "return SignExtend64<8>(Imm) == -1LL;">;
607 def allonessew16 : ImmLeaf<XLenVT, "return SignExtend64<16>(Imm) == -1LL;">;
608 def allonessew32 : ImmLeaf<XLenVT, "return SignExtend64<32>(Imm) == -1LL;">;
609 def allonessew64 : ImmLeaf<XLenVT, "return Imm == -1LL;">;
696 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1)))),
843 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),
854 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),
892 (vti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),
926 VLOpFrag, (XLenVT timm:$policy))),
[all …]
H A DRISCVInstrInfoXAndes.td32 def simm18 : Operand<XLenVT> {
38 def simm18_lsb0 : Operand<XLenVT> {
44 def simm19_lsb00 : Operand<XLenVT> {
50 def simm20_lsb000 : Operand<XLenVT> {
704 : Pat<(riscv_brcc (and(XLenVT GPR:$rs1), PowerOf2:$mask), 0, Cond,
709 : Pat<(riscv_brcc (XLenVT GPR:$rs1), uimm7:$cimm, Cond, bb:$imm10),
716 : Pat<(riscv_selectcc_frag:$cc (and(XLenVT GPR:$lhs), PowerOf2:$mask), 0,
717 Cond, (XLenVT GPR:$truev), GPR:$falsev),
722 : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), uimm7:$cimm, Cond,
723 (XLenVT GPR:$truev), GPR:$falsev),
[all …]

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