1//===-- RISCVInstrInfoXsf.td - SiFive custom instructions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the vendor extensions defined by SiFive. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// XSFVCP extension instructions. 15//===----------------------------------------------------------------------===// 16 17def VCIXVS2 : RISCVVConstraint<VS2Constraint.Value>; 18def VCIXVS2VS1 : RISCVVConstraint<!or(VS2Constraint.Value, 19 VS1Constraint.Value)>; 20 21class VCIXType<bits<4> val> { 22 bits<4> Val = val; 23} 24 25def VCIX_X : VCIXType<0b0000>; 26def VCIX_XV : VCIXType<0b0010>; 27def VCIX_XVV : VCIXType<0b1010>; 28def VCIX_XVW : VCIXType<0b1111>; 29 30// The payload and tsimm5 operands are all marked as ImmArg in the IR 31// intrinsic and will be target constant, so use TImmLeaf rather than ImmLeaf. 32class PayloadOp<int bitsNum> : RISCVOp, TImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);"> { 33 let ParserMatchClass = UImmAsmOperand<bitsNum>; 34 let DecoderMethod = "decodeUImmOperand<"# bitsNum # ">"; 35 let OperandType = "OPERAND_UIMM" # bitsNum; 36} 37 38def payload1 : PayloadOp<1>; 39def payload2 : PayloadOp<2>; 40def payload5 : PayloadOp<5>; 41 42def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> { 43 let ParserMatchClass = SImmAsmOperand<5>; 44 let EncoderMethod = "getImmOpValue"; 45 let DecoderMethod = "decodeSImmOperand<5>"; 46 let MCOperandPredicate = [{ 47 int64_t Imm; 48 if (MCOp.evaluateAsConstantImm(Imm)) 49 return isInt<5>(Imm); 50 return MCOp.isBareSymbolRef(); 51 }]; 52} 53 54class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> { 55 dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1); 56} 57 58class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins, 59 string opcodestr, string argstr> 60 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 61 bits<5> rs2; 62 bits<5> rs1; 63 bits<5> rd; 64 bits<2> funct6_lo2; 65 bit vm; 66 67 let Inst{31-28} = funct6_hi4; 68 let Inst{27-26} = funct6_lo2; 69 let Inst{25} = vm; 70 let Inst{24-20} = rs2; 71 let Inst{19-15} = rs1; 72 let Inst{14-12} = funct3; 73 let Inst{11-7} = rd; 74 let Inst{6-0} = OPC_CUSTOM_2.Value; 75 76 let Uses = [VTYPE, VL]; 77 let RVVConstraint = NoConstraint; 78} 79 80class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins, 81 string opcodestr, string argstr> 82 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 83 bits<5> rs2; 84 bits<5> rs1; 85 bits<5> rd; 86 bit funct6_lo1; 87 bit vm; 88 89 let Inst{31-28} = funct6_hi4; 90 let Inst{27} = 1; 91 let Inst{26} = funct6_lo1; 92 let Inst{25} = vm; 93 let Inst{24-20} = rs2; 94 let Inst{19-15} = rs1; 95 let Inst{14-12} = funct3; 96 let Inst{11-7} = rd; 97 let Inst{6-0} = OPC_CUSTOM_2.Value; 98 99 let Uses = [VTYPE, VL]; 100 let RVVConstraint = NoConstraint; 101} 102 103class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd, 104 DAGOperand TyRs2, DAGOperand TyRs1, bit HaveOutputDst> { 105 string OpcodeStr = !if(HaveOutputDst, "sf.vc.v." # suffix, 106 "sf.vc." # suffix); 107 bits<4> Funct6_hi4 = type.Val; 108 bits<3> Funct3 = !cond(!eq(TyRs1, VR): 0b000, 109 !eq(TyRs1, GPR): 0b100, 110 !eq(TyRs1, FPR32): 0b101, 111 !eq(TyRs1, simm5): 0b011); 112 dag Outs = !if(!not(HaveOutputDst), (outs), 113 !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)), 114 (outs TyRd:$rd_wb), (outs TyRd:$rd))); 115 dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2), 116 (ins uimm1:$funct6_lo1)), 117 !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X), 118 !eq(type, VCIX_XV))), 119 (ins), (ins TyRd:$rd)), 120 (ins TyRs2:$rs2), 121 (ins TyRs1:$rs1), 122 !if(!eq(type, VCIX_X), 1, 0)>.Ins; 123 string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1", 124 !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1", 125 "$funct6_lo1, $rd, $rs2, $rs1")); 126 string Constraints = !if(!not(HaveOutputDst), "", 127 !if(!or(!eq(type, VCIX_XVV), 128 !eq(type, VCIX_XVW)), "$rd = $rd_wb", "")); 129 RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst), 130 !ne(type, VCIX_XVW)), NoConstraint, 131 !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2)); 132} 133 134class CustomSiFiveVCIX<VCIXInfo info> 135 : RVInstVCCustom2<info.Funct6_hi4, info.Funct3, info.Outs, 136 info.Ins, info.OpcodeStr, info.Prototype> { 137 let Constraints = info.Constraints; 138 let RVVConstraint = info.RVVConstraint; 139} 140 141class CustomSiFiveVCIF<VCIXInfo info> 142 : RVInstVCFCustom2<info.Funct6_hi4, info.Funct3, info.Outs, 143 info.Ins, info.OpcodeStr, info.Prototype> { 144 let Constraints = info.Constraints; 145 let RVVConstraint = info.RVVConstraint; 146} 147 148multiclass CustomSiFiveVCIXorVCIF<string suffix, VCIXType type, 149 DAGOperand TyRd, DAGOperand TyRs2, 150 DAGOperand TyRs1, bit HaveOutputDst> { 151 defvar info = VCIXInfo<suffix, type, TyRd, TyRs2, TyRs1, HaveOutputDst>; 152 if !eq(TyRs1, FPR32) then { 153 def NAME : CustomSiFiveVCIF<info>; 154 } else { 155 def NAME : CustomSiFiveVCIX<info>; 156 } 157} 158 159multiclass CustomSiFiveVCIX<string suffix, VCIXType type, 160 DAGOperand InTyRd, DAGOperand InTyRs2, 161 DAGOperand InTyRs1> { 162 let vm = 1 in 163 defm VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2, 164 InTyRs1, 0>; 165 let vm = 0 in 166 defm VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2, 167 InTyRs1, 1>; 168} 169 170let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 171class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr> 172 : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2), 173 opcodestr, "$rd, $rs1, $rs2"> { 174 let vm = 1; 175 let funct6_lo2 = funct6{1-0}; 176} 177} 178 179class CustomSiFiveVFNRCLIP<bits<6> funct6, RISCVVFormat opv, string opcodestr> 180 : VALUVF<funct6, opv, opcodestr> { 181 let Inst{6-0} = OPC_CUSTOM_2.Value; 182} 183 184let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0, 185 hasSideEffects = 1, hasNoSchedulingInfo = 1, DecoderNamespace = "XSfvcp" in { 186 defm X : CustomSiFiveVCIX<"x", VCIX_X, uimm5, uimm5, GPR>, Sched<[]>; 187 defm I : CustomSiFiveVCIX<"i", VCIX_X, uimm5, uimm5, simm5>, Sched<[]>; 188 defm XV : CustomSiFiveVCIX<"xv", VCIX_XV, uimm5, VR, GPR>, Sched<[]>; 189 defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, uimm5, VR, simm5>, Sched<[]>; 190 defm VV : CustomSiFiveVCIX<"vv", VCIX_XV, uimm5, VR, VR>, Sched<[]>; 191 defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, uimm5, VR, FPR32>, Sched<[]>; 192 defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR, VR, GPR>, Sched<[]>; 193 defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5>, Sched<[]>; 194 defm VVV : CustomSiFiveVCIX<"vvv", VCIX_XVV, VR, VR, VR>, Sched<[]>; 195 defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR, VR, FPR32>, Sched<[]>; 196 defm XVW : CustomSiFiveVCIX<"xvw", VCIX_XVW, VR, VR, GPR>, Sched<[]>; 197 defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR, VR, simm5>, Sched<[]>; 198 defm VVW : CustomSiFiveVCIX<"vvw", VCIX_XVW, VR, VR, VR>, Sched<[]>; 199 defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>; 200} 201 202let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod" in { 203 def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">; 204 def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">; 205 def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">; 206 def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">; 207} 208 209let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq" in { 210 def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">; 211 def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">; 212 def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">; 213 def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">; 214} 215 216let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in { 217 def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; 218} 219 220let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in { 221 def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">; 222 def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">; 223} 224 225class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> : 226 Pseudo<(outs), 227 (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, 228 AVL:$vl, ixlenimm:$sew), []>, 229 RISCVVPseudo { 230 let mayLoad = 0; 231 let mayStore = 0; 232 let HasVLOp = 1; 233 let HasSEWOp = 1; 234 let hasSideEffects = 0; 235 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 236} 237 238class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> : 239 Pseudo<(outs), 240 (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, 241 AVL:$vl, ixlenimm:$sew), []>, 242 RISCVVPseudo { 243 let mayLoad = 0; 244 let mayStore = 0; 245 let HasVLOp = 1; 246 let HasSEWOp = 1; 247 let hasSideEffects = 0; 248 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 249} 250 251class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class, 252 DAGOperand RS1Class> : 253 Pseudo<(outs), 254 (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, 255 AVL:$vl, ixlenimm:$sew), []>, 256 RISCVVPseudo { 257 let mayLoad = 0; 258 let mayStore = 0; 259 let HasVLOp = 1; 260 let HasSEWOp = 1; 261 let hasSideEffects = 0; 262 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 263} 264 265class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> : 266 Pseudo<(outs RDClass:$rd), 267 (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, 268 AVL:$vl, ixlenimm:$sew), []>, 269 RISCVVPseudo { 270 let mayLoad = 0; 271 let mayStore = 0; 272 let HasVLOp = 1; 273 let HasSEWOp = 1; 274 let hasSideEffects = 0; 275 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 276} 277 278class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class, 279 DAGOperand RS1Class> : 280 Pseudo<(outs RDClass:$rd), 281 (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, 282 AVL:$vl, ixlenimm:$sew), []>, 283 RISCVVPseudo { 284 let mayLoad = 0; 285 let mayStore = 0; 286 let HasVLOp = 1; 287 let HasSEWOp = 1; 288 let hasSideEffects = 0; 289 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 290} 291 292class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class, 293 DAGOperand RS1Class> : 294 Pseudo<(outs RDClass:$rd), 295 (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, 296 AVL:$vl, ixlenimm:$sew), []>, 297 RISCVVPseudo { 298 let mayLoad = 0; 299 let mayStore = 0; 300 let HasVLOp = 1; 301 let HasSEWOp = 1; 302 let hasSideEffects = 0; 303 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 304} 305 306multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class, 307 Operand OpClass = payload2> { 308 let VLMul = m.value in { 309 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 310 def "PseudoVC_" # NAME # "_SE_" # m.MX 311 : VPseudoVC_X<OpClass, RS1Class>, 312 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 313 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 314 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, 315 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 316 } 317 def "PseudoVC_V_" # NAME # "_" # m.MX 318 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, 319 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 320 } 321} 322 323multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class, 324 Operand OpClass = payload2> { 325 let VLMul = m.value in { 326 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 327 def "PseudoVC_" # NAME # "_SE_" # m.MX 328 : VPseudoVC_XV<OpClass, m.vrclass, RS1Class>, 329 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 330 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 331 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>, 332 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 333 } 334 def "PseudoVC_V_" # NAME # "_" # m.MX 335 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>, 336 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 337 } 338} 339 340multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class, 341 Operand OpClass = payload2> { 342 let VLMul = m.value in { 343 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 344 def "PseudoVC_" # NAME # "_SE_" # m.MX 345 : VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 346 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 347 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 348 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 349 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 350 } 351 def "PseudoVC_V_" # NAME # "_" # m.MX 352 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 353 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 354 } 355} 356 357multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class, 358 Operand OpClass = payload2> { 359 let VLMul = m.value in { 360 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in 361 def "PseudoVC_" # NAME # "_SE_" # m.MX 362 : VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 363 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 364 let Constraints = "@earlyclobber $rd, $rd = $rs3" in { 365 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in 366 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 367 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 368 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 369 def "PseudoVC_V_" # NAME # "_" # m.MX 370 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 371 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 372 } 373 } 374} 375 376multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type, 377 string Constraint = ""> { 378 def "Pseudo" # NAME # "_" # mx 379 : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type, Constraint>; 380} 381 382multiclass VPseudoSiFiveVQMACCDOD<string Constraint = ""> { 383 foreach m = MxListVF8 in 384 let VLMul = m.value in 385 defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass, Constraint>; 386} 387 388multiclass VPseudoSiFiveVQMACCQOQ<string Constraint = ""> { 389 foreach m = [V_MF2, V_M1, V_M2, V_M4] in 390 let VLMul = m.value in 391 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>; 392} 393 394multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> { 395 foreach m = MxListVF2 in 396 let VLMul = m.value in 397 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>; 398} 399 400multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> { 401 foreach i = 0-4 in 402 let hasSideEffects = 0 in 403 defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass, 404 MxListVF4[i].vrclass, 405 FPR32, MxListW[i], 406 Constraint, /*sew*/0, 407 UsesVXRM=0>; 408} 409 410let Predicates = [HasVendorXSfvcp] in { 411 foreach m = MxList in { 412 defm X : VPseudoVC_X<m, GPR>; 413 defm I : VPseudoVC_X<m, tsimm5>; 414 defm XV : VPseudoVC_XV<m, GPR>; 415 defm IV : VPseudoVC_XV<m, tsimm5>; 416 defm VV : VPseudoVC_XV<m, m.vrclass>; 417 defm XVV : VPseudoVC_XVV<m, GPR>; 418 defm IVV : VPseudoVC_XVV<m, tsimm5>; 419 defm VVV : VPseudoVC_XVV<m, m.vrclass>; 420 } 421 foreach f = FPList in { 422 foreach m = f.MxList in { 423 defm f.FX # "V" : VPseudoVC_XV<m, f.fprclass, payload1>; 424 defm f.FX # "VV" : VPseudoVC_XVV<m, f.fprclass, payload1>; 425 } 426 } 427 foreach m = MxListW in { 428 defm XVW : VPseudoVC_XVW<m, GPR>; 429 defm IVW : VPseudoVC_XVW<m, tsimm5>; 430 defm VVW : VPseudoVC_XVW<m, m.vrclass>; 431 } 432 foreach f = FPListW in { 433 foreach m = f.MxList in 434 defm f.FX # "VW" : VPseudoVC_XVW<m, f.fprclass, payload1>; 435 } 436} 437 438let Predicates = [HasVendorXSfvqmaccdod] in { 439 defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD; 440 defm VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD; 441 defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD; 442 defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD; 443} 444 445let Predicates = [HasVendorXSfvqmaccqoq] in { 446 defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ; 447 defm VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ; 448 defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ; 449 defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ; 450} 451 452let Predicates = [HasVendorXSfvfwmaccqqq] in { 453 defm VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC; 454} 455 456let Predicates = [HasVendorXSfvfnrclipxfqf] in { 457 defm VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP; 458 defm VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP; 459} 460 461// SDNode 462def SDT_SF_VC_V_X : SDTypeProfile<1, 4, [SDTCisVec<0>, 463 SDTCisVT<1, XLenVT>, 464 SDTCisSameAs<1, 2>, 465 SDTCisSameAs<1, 3>, 466 SDTCisSameAs<1, 4>]>; 467 468def SDT_SF_VC_XV : SDTypeProfile<0, 5, [SDTCisSameAs<0, 1>, 469 SDTCisVec<2>, 470 SDTCisSameAs<0, 4>, 471 SDTCisVT<0, XLenVT>]>; 472 473def SDT_SF_VC_V_XV : SDTypeProfile<1, 4, [SDTCisVec<0>, 474 SDTCisVT<1, XLenVT>, 475 SDTCisSameAs<0, 2>, 476 SDTCisSameAs<1, 4>]>; 477 478def SDT_SF_VC_XVV : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>, 479 SDTCisVec<1>, 480 SDTCisSameAs<1, 2>, 481 SDTCisSameAs<0, 4>]>; 482 483def SDT_SF_VC_V_XVV : SDTypeProfile<1, 5, [SDTCisVec<0>, 484 SDTCisVT<1, XLenVT>, 485 SDTCisSameAs<0, 2>, 486 SDTCisSameAs<0, 3>, 487 SDTCisSameAs<1, 5>]>; 488 489def SDT_SF_VC_XVW : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>, 490 SDTCisVec<1>, SDTCisVec<2>, 491 SDTCisSameAs<0, 4>]>; 492 493def SDT_SF_VC_V_XVW : SDTypeProfile<1, 5, [SDTCisVec<0>, 494 SDTCisVT<1, XLenVT>, 495 SDTCisSameAs<0, 2>, 496 SDTCisVec<3>, 497 SDTCisSameAs<1, 5>]>; 498 499def sf_vc_v_x_se : SDNode<"RISCVISD::SF_VC_V_X_SE", SDT_SF_VC_V_X, [SDNPHasChain]>; 500def sf_vc_v_i_se : SDNode<"RISCVISD::SF_VC_V_I_SE", SDT_SF_VC_V_X, [SDNPHasChain]>; 501def sf_vc_vv_se : SDNode<"RISCVISD::SF_VC_VV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 502def sf_vc_xv_se : SDNode<"RISCVISD::SF_VC_XV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 503def sf_vc_iv_se : SDNode<"RISCVISD::SF_VC_IV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 504def sf_vc_fv_se : SDNode<"RISCVISD::SF_VC_FV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 505def sf_vc_v_vv_se : SDNode<"RISCVISD::SF_VC_V_VV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 506def sf_vc_v_xv_se : SDNode<"RISCVISD::SF_VC_V_XV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 507def sf_vc_v_iv_se : SDNode<"RISCVISD::SF_VC_V_IV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 508def sf_vc_v_fv_se : SDNode<"RISCVISD::SF_VC_V_FV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 509def sf_vc_vvv_se : SDNode<"RISCVISD::SF_VC_VVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 510def sf_vc_xvv_se : SDNode<"RISCVISD::SF_VC_XVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 511def sf_vc_ivv_se : SDNode<"RISCVISD::SF_VC_IVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 512def sf_vc_fvv_se : SDNode<"RISCVISD::SF_VC_FVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 513def sf_vc_v_vvv_se : SDNode<"RISCVISD::SF_VC_V_VVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 514def sf_vc_v_xvv_se : SDNode<"RISCVISD::SF_VC_V_XVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 515def sf_vc_v_ivv_se : SDNode<"RISCVISD::SF_VC_V_IVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 516def sf_vc_v_fvv_se : SDNode<"RISCVISD::SF_VC_V_FVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 517def sf_vc_vvw_se : SDNode<"RISCVISD::SF_VC_VVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 518def sf_vc_xvw_se : SDNode<"RISCVISD::SF_VC_XVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 519def sf_vc_ivw_se : SDNode<"RISCVISD::SF_VC_IVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 520def sf_vc_fvw_se : SDNode<"RISCVISD::SF_VC_FVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 521def sf_vc_v_vvw_se : SDNode<"RISCVISD::SF_VC_V_VVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 522def sf_vc_v_xvw_se : SDNode<"RISCVISD::SF_VC_V_XVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 523def sf_vc_v_ivw_se : SDNode<"RISCVISD::SF_VC_V_IVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 524def sf_vc_v_fvw_se : SDNode<"RISCVISD::SF_VC_V_FVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 525 526class VPatVC_OP4_ISD<SDPatternOperator op, 527 string inst, 528 ValueType op2_type, 529 ValueType op3_type, 530 ValueType op4_type, 531 int sew, 532 DAGOperand op2_kind, 533 DAGOperand op3_kind, 534 DAGOperand op4_kind, 535 Operand op1_kind = payload2> : 536 Pat<(op 537 (XLenVT op1_kind:$op1), 538 (op2_type op2_kind:$op2), 539 (op3_type op3_kind:$op3), 540 (op4_type op4_kind:$op4), 541 VLOpFrag), 542 (!cast<Instruction>(inst) 543 (XLenVT op1_kind:$op1), 544 (op2_type op2_kind:$op2), 545 (op3_type op3_kind:$op3), 546 (op4_type op4_kind:$op4), 547 GPR:$vl, sew)>; 548 549class VPatVC_V_OP4_ISD<SDPatternOperator op, 550 string inst, 551 ValueType result_type, 552 ValueType op2_type, 553 ValueType op3_type, 554 ValueType op4_type, 555 int sew, 556 DAGOperand op2_kind, 557 DAGOperand op3_kind, 558 DAGOperand op4_kind, 559 Operand op1_kind = payload2> : 560 Pat<(result_type (op 561 (XLenVT op1_kind:$op1), 562 (op2_type op2_kind:$op2), 563 (op3_type op3_kind:$op3), 564 (op4_type op4_kind:$op4), 565 VLOpFrag)), 566 (!cast<Instruction>(inst) 567 (XLenVT op1_kind:$op1), 568 (op2_type op2_kind:$op2), 569 (op3_type op3_kind:$op3), 570 (op4_type op4_kind:$op4), 571 GPR:$vl, sew)>; 572 573 574class VPatVC_V_OP3_ISD<SDPatternOperator op, 575 string inst, 576 ValueType result_type, 577 ValueType op2_type, 578 ValueType op3_type, 579 int sew, 580 DAGOperand op2_kind, 581 DAGOperand op3_kind, 582 Operand op1_kind = payload2> : 583 Pat<(result_type (op 584 (XLenVT op1_kind:$op1), 585 (op2_type op2_kind:$op2), 586 (op3_type op3_kind:$op3), 587 VLOpFrag)), 588 (!cast<Instruction>(inst) 589 (XLenVT op1_kind:$op1), 590 (op2_type op2_kind:$op2), 591 (op3_type op3_kind:$op3), 592 GPR:$vl, sew)>; 593 594class VPatVC_OP4<string intrinsic_name, 595 string inst, 596 ValueType op2_type, 597 ValueType op3_type, 598 ValueType op4_type, 599 int sew, 600 DAGOperand op2_kind, 601 DAGOperand op3_kind, 602 DAGOperand op4_kind, 603 Operand op1_kind = payload2> : 604 Pat<(!cast<Intrinsic>(intrinsic_name) 605 (XLenVT op1_kind:$op1), 606 (op2_type op2_kind:$op2), 607 (op3_type op3_kind:$op3), 608 (op4_type op4_kind:$op4), 609 VLOpFrag), 610 (!cast<Instruction>(inst) 611 (XLenVT op1_kind:$op1), 612 (op2_type op2_kind:$op2), 613 (op3_type op3_kind:$op3), 614 (op4_type op4_kind:$op4), 615 GPR:$vl, sew)>; 616 617class VPatVC_V_OP4<string intrinsic_name, 618 string inst, 619 ValueType result_type, 620 ValueType op2_type, 621 ValueType op3_type, 622 ValueType op4_type, 623 int sew, 624 DAGOperand op2_kind, 625 DAGOperand op3_kind, 626 DAGOperand op4_kind, 627 Operand op1_kind = payload2> : 628 Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 629 (XLenVT op1_kind:$op1), 630 (op2_type op2_kind:$op2), 631 (op3_type op3_kind:$op3), 632 (op4_type op4_kind:$op4), 633 VLOpFrag)), 634 (!cast<Instruction>(inst) 635 (XLenVT op1_kind:$op1), 636 (op2_type op2_kind:$op2), 637 (op3_type op3_kind:$op3), 638 (op4_type op4_kind:$op4), 639 GPR:$vl, sew)>; 640 641class VPatVC_V_OP3<string intrinsic_name, 642 string inst, 643 ValueType result_type, 644 ValueType op2_type, 645 ValueType op3_type, 646 int sew, 647 DAGOperand op2_kind, 648 DAGOperand op3_kind, 649 Operand op1_kind = payload2> : 650 Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 651 (XLenVT op1_kind:$op1), 652 (op2_type op2_kind:$op2), 653 (op3_type op3_kind:$op3), 654 VLOpFrag)), 655 (!cast<Instruction>(inst) 656 (XLenVT op1_kind:$op1), 657 (op2_type op2_kind:$op2), 658 (op3_type op3_kind:$op3), 659 GPR:$vl, sew)>; 660 661multiclass VPatVC_X<string intrinsic_suffix, string instruction_suffix, 662 VTypeInfo vti, ValueType type, DAGOperand kind> { 663 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 664 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 665 vti.Vector, XLenVT, type, vti.Log2SEW, 666 payload5, kind>; 667 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix, 668 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 669 vti.Vector, XLenVT, type, vti.Log2SEW, 670 payload5, kind>; 671} 672 673multiclass VPatVC_XV<string intrinsic_suffix, string instruction_suffix, 674 VTypeInfo vti, ValueType type, DAGOperand kind, 675 Operand op1_kind = payload2> { 676 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"), 677 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX, 678 XLenVT, vti.Vector, type, vti.Log2SEW, 679 payload5, vti.RegClass, kind, op1_kind>; 680 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 681 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 682 vti.Vector, vti.Vector, type, vti.Log2SEW, 683 vti.RegClass, kind, op1_kind>; 684 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix, 685 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 686 vti.Vector, vti.Vector, type, vti.Log2SEW, 687 vti.RegClass, kind, op1_kind>; 688} 689 690multiclass VPatVC_XVV<string intrinsic_suffix, string instruction_suffix, 691 VTypeInfo wti, VTypeInfo vti, ValueType type, DAGOperand kind, 692 Operand op1_kind = payload2> { 693 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"), 694 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX, 695 wti.Vector, vti.Vector, type, vti.Log2SEW, 696 wti.RegClass, vti.RegClass, kind, op1_kind>; 697 def : VPatVC_V_OP4_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 698 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 699 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW, 700 wti.RegClass, vti.RegClass, kind, op1_kind>; 701 def : VPatVC_V_OP4<"int_riscv_sf_vc_v_" # intrinsic_suffix, 702 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 703 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW, 704 wti.RegClass, vti.RegClass, kind, op1_kind>; 705} 706 707class GetFTypeInfo<int Sew> { 708 ValueType Scalar = !cond(!eq(Sew, 16) : f16, 709 !eq(Sew, 32) : f32, 710 !eq(Sew, 64) : f64); 711 RegisterClass ScalarRegClass = !cond(!eq(Sew, 16) : FPR16, 712 !eq(Sew, 32) : FPR32, 713 !eq(Sew, 64) : FPR64); 714 715 string ScalarSuffix = !cond(!eq(Scalar, f16) : "FPR16", 716 !eq(Scalar, f32) : "FPR32", 717 !eq(Scalar, f64) : "FPR64"); 718} 719 720multiclass VPatVMACC<string intrinsic, string instruction, string kind, 721 list<VTypeInfoToWide> info_pairs, ValueType vec_m1> { 722 foreach pair = info_pairs in { 723 defvar VdInfo = pair.Wti; 724 defvar Vs2Info = pair.Vti; 725 let Predicates = [HasVInstructions] in 726 def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic, 727 "Pseudo" # instruction, kind, VdInfo.Vector, 728 vec_m1, Vs2Info.Vector, 729 Vs2Info.Log2SEW, Vs2Info.LMul, 730 VdInfo.RegClass, VR, Vs2Info.RegClass>; 731 } 732} 733 734defset list<VTypeInfoToWide> VQMACCDODInfoPairs = { 735 def : VTypeInfoToWide<VI8M1, VI32M1>; 736 def : VTypeInfoToWide<VI8M2, VI32M2>; 737 def : VTypeInfoToWide<VI8M4, VI32M4>; 738 def : VTypeInfoToWide<VI8M8, VI32M8>; 739} 740 741defset list<VTypeInfoToWide> VQMACCQOQInfoPairs = { 742 def : VTypeInfoToWide<VI8MF2, VI32M1>; 743 def : VTypeInfoToWide<VI8M1, VI32M2>; 744 def : VTypeInfoToWide<VI8M2, VI32M4>; 745 def : VTypeInfoToWide<VI8M4, VI32M8>; 746} 747 748multiclass VPatVQMACCDOD<string intrinsic, string instruction, string kind> 749 : VPatVMACC<intrinsic, instruction, kind, VQMACCDODInfoPairs, vint8m1_t>; 750 751multiclass VPatVQMACCQOQ<string intrinsic, string instruction, string kind> 752 : VPatVMACC<intrinsic, instruction, kind, VQMACCQOQInfoPairs, vint8m1_t>; 753 754multiclass VPatVFWMACC<string intrinsic, string instruction, string kind> 755 : VPatVMACC<intrinsic, instruction, kind, AllWidenableBFloatToFloatVectors, 756 vbfloat16m1_t>; 757 758defset list<VTypeInfoToWide> VFNRCLIPInfoPairs = { 759 def : VTypeInfoToWide<VI8MF8, VF32MF2>; 760 def : VTypeInfoToWide<VI8MF4, VF32M1>; 761 def : VTypeInfoToWide<VI8MF2, VF32M2>; 762 def : VTypeInfoToWide<VI8M1, VF32M4>; 763 def : VTypeInfoToWide<VI8M2, VF32M8>; 764} 765 766multiclass VPatVFNRCLIP<string intrinsic, string instruction> { 767 foreach pair = VFNRCLIPInfoPairs in { 768 defvar Vti = pair.Vti; 769 defvar Wti = pair.Wti; 770 defm : VPatBinaryRoundingMode<"int_riscv_sf_" # intrinsic, 771 "Pseudo" # instruction # "_" # Vti.LMul.MX, 772 Vti.Vector, Wti.Vector, Wti.Scalar, Vti.Mask, 773 Vti.Log2SEW, Vti.RegClass, 774 Wti.RegClass, Wti.ScalarRegClass>; 775 } 776} 777 778let Predicates = [HasVendorXSfvcp] in { 779 foreach vti = AllIntegerVectors in { 780 defm : VPatVC_X<"x", "X", vti, XLenVT, GPR>; 781 defm : VPatVC_X<"i", "I", vti, XLenVT, tsimm5>; 782 defm : VPatVC_XV<"xv", "XV", vti, XLenVT, GPR>; 783 defm : VPatVC_XV<"iv", "IV", vti, XLenVT, tsimm5>; 784 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>; 785 defm : VPatVC_XVV<"xvv", "XVV", vti, vti, XLenVT, GPR>; 786 defm : VPatVC_XVV<"ivv", "IVV", vti, vti, XLenVT, tsimm5>; 787 defm : VPatVC_XVV<"vvv", "VVV", vti, vti, vti.Vector, vti.RegClass>; 788 789 if !ne(vti.SEW, 8) then { 790 defvar finfo = GetFTypeInfo<vti.SEW>; 791 defm : VPatVC_XV<"fv", finfo.ScalarSuffix # "V", vti, finfo.Scalar, 792 finfo.ScalarRegClass, payload1>; 793 defm : VPatVC_XVV<"fvv", finfo.ScalarSuffix # "VV", vti, vti, finfo.Scalar, 794 finfo.ScalarRegClass, payload1>; 795 } 796 } 797 foreach VtiToWti = AllWidenableIntVectors in { 798 defvar vti = VtiToWti.Vti; 799 defvar wti = VtiToWti.Wti; 800 defvar iinfo = GetIntVTypeInfo<vti>.Vti; 801 defm : VPatVC_XVV<"xvw", "XVW", wti, vti, iinfo.Scalar, iinfo.ScalarRegClass>; 802 defm : VPatVC_XVV<"ivw", "IVW", wti, vti, XLenVT, tsimm5>; 803 defm : VPatVC_XVV<"vvw", "VVW", wti, vti, vti.Vector, vti.RegClass>; 804 805 if !ne(vti.SEW, 8) then { 806 defvar finfo = GetFTypeInfo<vti.SEW>; 807 defm : VPatVC_XVV<"fvw", finfo.ScalarSuffix # "VW", wti, vti, finfo.Scalar, 808 finfo.ScalarRegClass, payload1>; 809 } 810 } 811} 812 813let Predicates = [HasVendorXSfvqmaccdod] in { 814 defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">; 815 defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">; 816 defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">; 817 defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">; 818} 819 820let Predicates = [HasVendorXSfvqmaccqoq] in { 821 defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">; 822 defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">; 823 defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">; 824 defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">; 825} 826 827let Predicates = [HasVendorXSfvfwmaccqqq] in { 828 defm : VPatVFWMACC<"vfwmacc_4x4x4", "VFWMACC", "4x4x4">; 829} 830 831let Predicates = [HasVendorXSfvfnrclipxfqf] in { 832 defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">; 833 defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">; 834} 835 836let Predicates = [HasVendorXSiFivecdiscarddlone] in { 837 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 838 DecoderNamespace = "XSiFivecdiscarddlone" in 839 def SF_CDISCARD_D_L1 840 : RVInstIUnary<0b111111000010, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 841 "sf.cdiscard.d.l1", "$rs1">, Sched<[]> { 842 let rd = 0; 843 } 844 def : InstAlias<"sf.cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>; 845} // Predicates = [HasVendorXSifivecdiscarddlone] 846 847let Predicates = [HasVendorXSiFivecflushdlone] in { 848 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 849 DecoderNamespace = "XSiFivecflushdlone" in 850 def SF_CFLUSH_D_L1 851 : RVInstIUnary<0b111111000000, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 852 "sf.cflush.d.l1", "$rs1">, Sched<[]> { 853 let rd = 0; 854 } 855 def : InstAlias<"sf.cflush.d.l1", (SF_CFLUSH_D_L1 X0)>; 856} // Predicates = [HasVendorXSifivecflushdlone] 857 858let Predicates = [HasVendorXSfcease] in { 859 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 860 DecoderNamespace = "XSfcease" in 861 def SF_CEASE : RVInstIUnary<0b001100000101, 0b000, OPC_SYSTEM, (outs), (ins), 862 "sf.cease", "">, Sched<[]> { 863 let rs1 = 0b00000; 864 let rd = 0b00000; 865} 866} 867