Lines Matching refs:XLenVT

26     : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>,
27                            SDTCisVT<2, XLenVT>]>;
31                            SDTCisVT<3, XLenVT>]>;
33     : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
129 def frmarg : Operand<XLenVT> {
149 def frmarglegacy : Operand<XLenVT> {
482     : Pat<(XLenVT (OpNode (vt Ty:$rs1), Ty:$rs2, Cond)), (Inst $rs1, $rs2)>;
619 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
620           (AND (XLenVT (FLE_S $rs1, $rs2)),
621                (XLenVT (FLE_S $rs2, $rs1)))>;
622 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
623           (AND (XLenVT (FLE_S $rs1, $rs2)),
624                (XLenVT (FLE_S $rs2, $rs1)))>;
626 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
628 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ)),
634 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ)),
635           (AND (XLenVT (FLE_S_INX $rs1, $rs2)),
636                (XLenVT (FLE_S_INX $rs2, $rs1)))>;
637 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ)),
638           (AND (XLenVT (FLE_S_INX $rs1, $rs2)),
639                (XLenVT (FLE_S_INX $rs2, $rs1)))>;
641 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ)),
643 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETOEQ)),
675 def : Pat<(f32 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
679 def : Pat<(store (f32 FPR32INX:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),