Lines Matching refs:XLenVT
24 def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
150 class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
161 RISCVUImmOp<bitsNum>, ImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);">;
171 RISCVSImmOp<bitsNum>, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);">;
192 def uimmlog2xlen : RISCVOp, ImmLeaf<XLenVT, [{
249 def simm12_no6 : ImmLeaf<XLenVT, [{
326 def bare_symbol : Operand<XLenVT> {
338 def call_symbol : Operand<XLenVT> {
350 def pseudo_jump_symbol : Operand<XLenVT> {
362 def tprel_add_symbol : Operand<XLenVT> {
372 def csr_sysreg : RISCVOp, TImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
380 def ixlenimm : Operand<XLenVT>;
382 def ixlenimm_li : Operand<XLenVT> {
387 def ixlenimm_li_restricted : Operand<XLenVT> {
394 def uimm6gt32 : ImmLeaf<XLenVT, [{
1085 def AnyReg : Operand<XLenVT> {
1189 class PatGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
1191 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt1 = XLenVT,
1192 ValueType vt2 = XLenVT>
1196 ValueType vt = XLenVT>
1209 def sexti16 : ComplexPattern<XLenVT, 1, "selectSExtBits<16>">;
1216 def zexti16 : ComplexPattern<XLenVT, 1, "selectZExtBits<16>">;
1218 def zexti8 : ComplexPattern<XLenVT, 1, "selectZExtBits<8>">;
1287 def : Pat<(XLenVT (sub 0, (and_oneuse GPR:$rs, 1))),
1288 (SRAI (XLenVT (SLLI $rs, (ImmSubFromXLen (XLenVT 1)))),
1289 (ImmSubFromXLen (XLenVT 1)))>;
1294 def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
1295 (SRLI (XLenVT (SLLI $rs, TrailingOnesMask:$mask)), TrailingOnesMask:$mask)>;
1301 def shiftMaskXLen : ComplexPattern<XLenVT, 1, "selectShiftMaskXLen", [], [], 0>;
1306 (operator node:$val, (XLenVT (shiftMaskXLen node:$count)))>;
1384 def riscv_setne : ComplexPattern<XLenVT, 1, "selectSETNE", [setcc]>;
1385 def riscv_seteq : ComplexPattern<XLenVT, 1, "selectSETEQ", [setcc]>;
1389 def : Pat<(riscv_seteq (XLenVT GPR:$rs1)), (SLTIU GPR:$rs1, 1)>;
1390 def : Pat<(riscv_setne (XLenVT GPR:$rs1)), (SLTU (XLenVT X0), GPR:$rs1)>;
1391 def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), -1)), (SLTIU GPR:$rs1, -1)>;
1412 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,
1416 def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 0, cond, (vt valty:$truev),
1418 (!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, (XLenVT X0),
1423 defm Select_GPR : SelectCC_GPR_rrirr<GPR, XLenVT>;
1426 : Pat<(riscv_selectcc_frag:$select (XLenVT GPR:$lhs), simm12_no6:$Constant, Cond,
1427 (XLenVT GPR:$truev), GPR:$falsev),
1428 (Select_GPR_Using_CC_GPR (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))), (XLenVT X0),
1442 def : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12),
1445 def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
1446 (Inst GPR:$rs1, (XLenVT X0), simm13_lsb0:$imm12)>;
1451 (Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))),
1452 (XLenVT X0), bb:$place)>;
1546 def : Pat<(riscv_sret_glue), (SRET (XLenVT X0), (XLenVT X0))>;
1547 def : Pat<(riscv_mret_glue), (MRET (XLenVT X0), (XLenVT X0))>;
1658 def tlsdesc_call_symbol : Operand<XLenVT> {
1696 class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
1697 : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
1712 : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPR:$rs1),
1716 def : StPat<truncstorei8, SB, GPR, XLenVT>;
1717 def : StPat<truncstorei16, SH, GPR, XLenVT>;
1726 def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>;
1728 def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>;
1730 def : Pat<(atomic_fence (XLenVT 6), (timm)), (FENCE_TSO)>;
1732 def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>;
1748 [(set GPR:$rd, (XLenVT (riscv_read_csr (XLenVT SR.Encoding))))]>,
1756 [(riscv_write_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>,
1764 [(riscv_write_csr (XLenVT SR.Encoding), uimm5:$val)]>,
1772 [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val)))]>,
1781 [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val)))]>,
1822 (XLenVT (operator node:$lhs, node:$rhs)), [{
1845 def u32simm12 : ImmLeaf<XLenVT, [{
1857 def : Pat<(sexti32_allwusers GPR:$rs1), (XLenVT GPR:$rs1)>;
1916 def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, (XLenVT X0))>;
1918 def : Pat<(i64 (readsteadycounter)), (CSRRS TIME.Encoding, (XLenVT X0))>;
1954 def : Pat<(XLenVT (add GPR:$rs1, (AddiPair:$rs2))),
1955 (ADDI (XLenVT (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2))),