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Searched refs:WriteRes (Results 1 – 25 of 67) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedXiangShanNanHu.td47 def : WriteRes<WriteJmp, [XS2MISC]>;
48 def : WriteRes<WriteJal, [XS2MISC]>;
49 def : WriteRes<WriteJalr, [XS2MISC]>;
53 def : WriteRes<WriteIALU, [XS2ALU]>;
54 def : WriteRes<WriteIALU32, [XS2ALU]>;
55 def : WriteRes<WriteShiftImm, [XS2ALU]>;
56 def : WriteRes<WriteShiftImm32, [XS2ALU]>;
57 def : WriteRes<WriteShiftReg, [XS2ALU]>;
58 def : WriteRes<WriteShiftReg32, [XS2ALU]>;
63 def : WriteRes<WriteIMul, [XS2MDU]>;
[all …]
H A DRISCVSchedSiFiveP400.td50 def : WriteRes<WriteIALU, [SiFiveP400IntArith]>;
51 def : WriteRes<WriteIALU32, [SiFiveP400IntArith]>;
52 def : WriteRes<WriteShiftImm, [SiFiveP400IntArith]>;
53 def : WriteRes<WriteShiftImm32, [SiFiveP400IntArith]>;
54 def : WriteRes<WriteShiftReg, [SiFiveP400IntArith]>;
55 def : WriteRes<WriteShiftReg32, [SiFiveP400IntArith]>;
57 def : WriteRes<WriteJmp, [SiFiveP400Branch]>;
58 def : WriteRes<WriteJal, [SiFiveP400Branch]>;
59 def : WriteRes<WriteJalr, [SiFiveP400Branch]>;
71 def : WriteRes<WriteIMul, [SiFiveP400MulDiv]>;
[all …]
H A DRISCVSchedRocket.td51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
53 def : WriteRes<WriteJalr, [RocketUnitB]>;
56 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
57 def : WriteRes<WriteIALU, [RocketUnitALU]>;
58 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
59 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
60 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
61 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
65 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
[all …]
H A DRISCVSchedSyntacoreSCR3.td30 def : WriteRes<WriteJmp, [BRU]>;
31 def : WriteRes<WriteJal, [BRU]>;
32 def : WriteRes<WriteJalr, [BRU]>;
37 def : WriteRes<WriteIALU, [ALU]>;
38 def : WriteRes<WriteIALU32, [ALU]>;
39 def : WriteRes<WriteShiftImm, [ALU]>;
40 def : WriteRes<WriteShiftImm32, [ALU]>;
41 def : WriteRes<WriteShiftReg, [ALU]>;
42 def : WriteRes<WriteShiftReg32, [ALU]>;
48 def : WriteRes<WriteIMul, [MUL]>;
[all …]
H A DRISCVSchedSyntacoreSCR1.td41 def : WriteRes<WriteJmp, [SCR1_CFU]>;
42 def : WriteRes<WriteJal, [SCR1_CFU]>;
43 def : WriteRes<WriteJalr, [SCR1_CFU]>;
46 def : WriteRes<WriteIALU32, [SCR1_ALU]>;
47 def : WriteRes<WriteIALU, [SCR1_ALU]>;
48 def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
49 def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
50 def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
51 def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
54 def : WriteRes<WriteIMul, [SCR1_MUL]>;
[all …]
H A DRISCVSchedule.td216 def : WriteRes<WriteFAdd16, []>;
217 def : WriteRes<WriteFClass16, []>;
218 def : WriteRes<WriteFCvtF16ToF64, []>;
219 def : WriteRes<WriteFCvtF64ToF16, []>;
220 def : WriteRes<WriteFCvtI64ToF16, []>;
221 def : WriteRes<WriteFCvtF32ToF16, []>;
222 def : WriteRes<WriteFCvtI32ToF16, []>;
223 def : WriteRes<WriteFCvtF16ToI64, []>;
224 def : WriteRes<WriteFCvtF16ToF32, []>;
225 def : WriteRes<WriteFCvtF16ToI32, []>;
[all …]
H A DRISCVScheduleZb.td89 def : WriteRes<WriteSHXADD, []>;
90 def : WriteRes<WriteSHXADD32, []>;
99 def : WriteRes<WriteRotateImm, []>;
100 def : WriteRes<WriteRotateImm32, []>;
101 def : WriteRes<WriteRotateReg, []>;
102 def : WriteRes<WriteRotateReg32, []>;
103 def : WriteRes<WriteCLZ, []>;
104 def : WriteRes<WriteCLZ32, []>;
105 def : WriteRes<WriteCTZ, []>;
106 def : WriteRes<WriteCTZ32, []>;
[all …]
H A DRISCVSchedSiFiveP600.td104 def : WriteRes<WriteIALU, [SiFiveP600IntArith]>;
105 def : WriteRes<WriteIALU32, [SiFiveP600IntArith]>;
106 def : WriteRes<WriteShiftImm, [SiFiveP600IntArith]>;
107 def : WriteRes<WriteShiftImm32, [SiFiveP600IntArith]>;
108 def : WriteRes<WriteShiftReg, [SiFiveP600IntArith]>;
109 def : WriteRes<WriteShiftReg32, [SiFiveP600IntArith]>;
111 def : WriteRes<WriteJmp, [SiFiveP600Branch]>;
112 def : WriteRes<WriteJal, [SiFiveP600Branch]>;
113 def : WriteRes<WriteJalr, [SiFiveP600Branch]>;
124 def : WriteRes<WriteIMul, [SiFiveP600MulI2F]>;
[all …]
H A DRISCVSchedSiFive7.td239 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
240 def : WriteRes<WriteJal, [SiFive7PipeB]>;
241 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
245 def : WriteRes<WriteSFB, [SiFive7PipeA, SiFive7PipeB]> {
252 def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
253 def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
254 def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>;
255 def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>;
256 def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>;
257 def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td70 // These WriteRes entries are not used in the Falkor sched model.
71 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
73 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
75 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
76 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
78 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM3
[all...]
H A DAArch64SchedKryo.td66 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
68 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
70 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
72 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
74 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
75 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
77 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
79 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM6
[all...]
H A DAArch64SchedThunderX.td52 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
53 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
54 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
56 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
57 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
60 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
65 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
71 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
76 def : WriteRes<WriteID6
[all...]
H A DAArch64SchedA53.td61 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
66 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
69 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
70 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
73 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
74 def : WriteRes<WriteID6
[all...]
H A DAArch64SchedA55.td66 def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
70 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
71 def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; } // Shift/Scale
74 def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; } // 32-bit Multiply
75 def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit Multiply
78 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
81 def : WriteRes<WriteID6
[all...]
H A DAArch64SchedCyclone.td134 def : WriteRes<WriteImm, [CyUnitI]>;
153 def : WriteRes<WriteI, [CyUnitI]>;
159 def : WriteRes<WriteISReg, [CyUnitIS]> {
167 def : WriteRes<WriteIEReg, [CyUnitIS]> {
174 def : WriteRes<WriteIS, [CyUnitIS]>;
179 def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> {
195 def : WriteRes<WriteIM32, [CyUnitIM]> {
199 def : WriteRes<WriteIM64, [CyUnitIM]> {
210 def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
217 def : WriteRes<WriteID6
[all...]
H A DAArch64SchedTSV110.td60 def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
61 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
62 def : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; }
63 def : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; }
64 def : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; }
65 def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
68 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
70 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
72 def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
73 def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
[all …]
H A DAArch64SchedAmpere1.td586 def : WriteRes<WriteImm, [Ampere1UnitAB]>; // MOVN, MOVZ
587 def : WriteRes<WriteI, [Ampere1UnitAB]>; // ALU
588 def : WriteRes<WriteISReg, [Ampere1UnitB, Ampere1UnitA]> {
592 def : WriteRes<WriteIEReg, [Ampere1UnitAB, Ampere1UnitA]> {
596 def : WriteRes<WriteExtr, [Ampere1UnitB]>; // EXTR shifts a reg pair
597 def : WriteRes<WriteIS, [Ampere1UnitB]>; // Shift/Scale
598 def : WriteRes<WriteID32, [Ampere1UnitBS]> {
601 def : WriteRes<WriteID64, [Ampere1UnitBS]> {
604 def : WriteRes<WriteIM32, [Ampere1UnitBS]> {
607 def : WriteRes<WriteIM64, [Ampere1UnitBS]> {
[all …]
H A DAArch64SchedAmpere1B.td542 def : WriteRes<WriteImm, [Ampere1BUnitAB]>; // MOVN, MOVZ
543 def : WriteRes<WriteI, [Ampere1BUnitAB]>; // ALU
544 def : WriteRes<WriteISReg, [Ampere1BUnitB, Ampere1BUnitAB]> {
548 def : WriteRes<WriteIEReg, [Ampere1BUnitAB, Ampere1BUnitAB]> {
552 def : WriteRes<WriteExtr, [Ampere1BUnitB]>; // EXTR shifts a reg pair
553 def : WriteRes<WriteIS, [Ampere1BUnitB]>; // Shift/Scale
554 def : WriteRes<WriteID32, [Ampere1BUnitBS, Ampere1BUnitX]> {
557 def : WriteRes<WriteID64, [Ampere1BUnitBS, Ampere1BUnitX]> {
560 def : WriteRes<WriteIM32, [Ampere1BUnitBS]> {
563 def : WriteRes<WriteIM64, [Ampere1BUnitBS, Ampere1BUnitAB]> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
84 def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; }
86 def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
87 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
88 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
139 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
140 def : WriteRes<WriteSETCCStor
[all...]
H A DX86ScheduleAtom.td63 def : WriteRes<SchedRW, RRPorts> {
70 def : WriteRes<SchedRW.Folded, RMPorts> {
78 def : WriteRes<WriteRMW, [AtomPort0]>;
122 def : WriteRes<WriteSETCC, [AtomPort01]>;
123 def : WriteRes<WriteSETCCStore, [AtomPort01]> {
127 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
139 def : WriteRes<WriteLEA, [AtomPort1]>;
171 def : WriteRes<WriteLoad, [AtomPort0]>;
172 def : WriteRes<WriteStore, [AtomPort0]>;
173 def : WriteRes<WriteStoreN
[all...]
H A DX86SchedSandyBridge.td91 def : WriteRes<SchedRW, ExePorts> {
99 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
108 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
110 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
111 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
113 def : WriteRes<WriteMove, [SBPort015]>;
120 def : WriteRes<WriteZero, []>;
143 def SBWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
144 def : WriteRes<WriteIMulHL
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
60 def : WriteRes<WriteALUsi, [M7UnitALU, M7UnitShift1]>;
61 def : WriteRes<WriteALUsr, [M7UnitALU, M7UnitShift1]>;
62 def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
66 def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
74 def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
[all …]
H A DARMScheduleM55.td135 def : WriteRes<WriteALU, [M55UnitALU]>;
136 def : WriteRes<WriteCMP, [M55UnitALU]>;
137 def : WriteRes<WriteBr, [M55UnitALU]>;
138 def : WriteRes<WriteBrL, [M55UnitALU]>;
139 def : WriteRes<WriteBrTbl, [M55UnitALU]>;
140 def : WriteRes<WriteST, [M55UnitALU]>;
144 def : WriteRes<WritePreLd, [M55UnitALU]>;
178 def : WriteRes<WriteLd, [M55UnitALU]>;
182 def : WriteRes<WriteALUsi, [M55UnitALU]>;
183 def : WriteRes<WriteALUs
[all...]
H A DARMScheduleR52.td61 def : WriteRes<WriteALU, [R52UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteALUsi, [R52UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteALUsr, [R52UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteALUSsr, [R52UnitALU]> { let Latency = 3; }
67 def : WriteRes<WriteCMP, [R52UnitALU]> { let Latency = 0; }
68 def : WriteRes<WriteCMPsi, [R52UnitALU]> { let Latency = 0; }
69 def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }
74 def : WriteRes<WriteDIV, [R52UnitDiv]> {
79 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
80 def : WriteRes<WriteBr
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }

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