Lines Matching refs:WriteRes

67   def : WriteRes<SchedRW, ExePorts> {
75   def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
84 def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; }
86 def : WriteRes<WriteStore,   [SLM_IEC_RSV01, SLM_MEC_RSV]>;
87 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
88 def : WriteRes<WriteLoad,    [SLM_MEC_RSV]> { let Latency = 3; }
89 def : WriteRes<WriteMove,    [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero,    []>;
139 def  : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
140 def  : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
155 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
182 def  : WriteRes<WriteFLoad,         [SLM_MEC_RSV]> { let Latency = 3; }
183 def  : WriteRes<WriteFLoadX,        [SLM_MEC_RSV]> { let Latency = 3; }
185 def  : WriteRes<WriteFMaskedLoad,   [SLM_MEC_RSV]> { let Latency = 3; }
187 def  : WriteRes<WriteFStore,        [SLM_MEC_RSV]>;
188 def  : WriteRes<WriteFStoreX,       [SLM_MEC_RSV]>;
190 def  : WriteRes<WriteFStoreNT,      [SLM_MEC_RSV]>;
191 def  : WriteRes<WriteFStoreNTX,     [SLM_MEC_RSV]>;
194 def  : WriteRes<WriteFMaskedStore32,    [SLM_MEC_RSV]>;
196 def  : WriteRes<WriteFMaskedStore64,    [SLM_MEC_RSV]>;
199 def  : WriteRes<WriteFMove,         [SLM_FPC_RSV01]>;
200 def  : WriteRes<WriteFMoveX,        [SLM_FPC_RSV01]>;
328 def  : WriteRes<WriteVecLoad,         [SLM_MEC_RSV]> { let Latency = 3; }
329 def  : WriteRes<WriteVecLoadX,        [SLM_MEC_RSV]> { let Latency = 3; }
331 def  : WriteRes<WriteVecLoadNT,       [SLM_MEC_RSV]> { let Latency = 3; }
333 def  : WriteRes<WriteVecMaskedLoad,   [SLM_MEC_RSV]> { let Latency = 3; }
335 def  : WriteRes<WriteVecStore,        [SLM_MEC_RSV]>;
336 def  : WriteRes<WriteVecStoreX,       [SLM_MEC_RSV]>;
338 def  : WriteRes<WriteVecStoreNT,      [SLM_MEC_RSV]>;
340 def  : WriteRes<WriteVecMaskedStore32,    [SLM_MEC_RSV]>;
342 def  : WriteRes<WriteVecMaskedStore64,    [SLM_MEC_RSV]>;
344 def  : WriteRes<WriteVecMove,         [SLM_FPC_RSV01]>;
345 def  : WriteRes<WriteVecMoveX,        [SLM_FPC_RSV01]>;
348 def  : WriteRes<WriteVecMoveToGpr,    [SLM_IEC_RSV01]>;
349 def  : WriteRes<WriteVecMoveFromGpr,  [SLM_IEC_RSV01]>;
410 def  : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {
413 def  : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
445 def : WriteRes<WriteFMOVMSK,    [SLM_FPC_RSV1]> { let Latency = 4; }
446 def : WriteRes<WriteVecMOVMSK,  [SLM_FPC_RSV1]> { let Latency = 4; }
447 def : WriteRes<WriteMMXMOVMSK,  [SLM_FPC_RSV1]> { let Latency = 4; }
458 def : WriteRes<WriteSystem,     [SLM_FPC_RSV0]> { let Latency = 100; }
459 def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
460 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
461 def : WriteRes<WriteNop, []>;