Lines Matching refs:WriteRes

56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
60   def : WriteRes<WriteALUsi,  [M7UnitALU, M7UnitShift1]>;
61   def : WriteRes<WriteALUsr,  [M7UnitALU, M7UnitShift1]>;
62   def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
66 def : WriteRes<WriteCMP,   [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
72   def : WriteRes<WriteMUL16,   [M7UnitMAC]>;
73   def : WriteRes<WriteMUL32,   [M7UnitMAC]>;
74   def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
75   def : WriteRes<WriteMUL64Hi, []> { let NumMicroOps = 0; }
80   def : WriteRes<WriteMAC16,   [M7UnitMAC]>;
81   def : WriteRes<WriteMAC32,   [M7UnitMAC]>;
82   def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
83   def : WriteRes<WriteMAC64Hi, []> { let NumMicroOps = 0; }
88 def : WriteRes<WriteDIV, [M7UnitALU]> {
94 def : WriteRes<WriteLd,    [M7UnitLoad]> { let Latency = 1; }
95 def : WriteRes<WritePreLd, [M7UnitLoad]> { let Latency = 2; }
96 def : WriteRes<WriteST,    [M7UnitStore]> { let Latency = 2; }
99 def : WriteRes<WriteBr,    [M7UnitBranch]> { let Latency = 2; }
100 def : WriteRes<WriteBrL,   [M7UnitBranch]> { let Latency = 2; }
101 def : WriteRes<WriteBrTbl, [M7UnitBranch]> { let Latency = 2; }
104 def : WriteRes<WriteNoop, []> { let Latency = 0; }
110 def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
111 def : WriteRes<WriteFPMOV, [M7UnitVPort]>            { let Latency = 3; }
118 def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]>  { let Latency = 3; }
119 def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
125 def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
126 def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
132 def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
133 def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
139 def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]>  { let Latency = 16; }
140 def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
146 def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
147 def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
155 def : WriteRes<WriteVLD1, []>;
156 def : WriteRes<WriteVLD2, []>;
157 def : WriteRes<WriteVLD3, []>;
158 def : WriteRes<WriteVLD4, []>;
159 def : WriteRes<WriteVST1, []>;
160 def : WriteRes<WriteVST2, []>;
161 def : WriteRes<WriteVST3, []>;
162 def : WriteRes<WriteVST4, []>;