Lines Matching refs:WriteRes

66 def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; }    // MOVN, MOVZ
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; }      // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; }  // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; }  // ALU of Extended-Reg
70 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; }   // EXTR from a reg pair
71 def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; }     // Shift/Scale
74 def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; }   // 32-bit Multiply
75 def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; }   // 64-bit Multiply
78 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
81 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
86 def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
87 def : WriteRes<WriteLDIdx, [CortexA55UnitLd]> { let Latency = 4; }
88 def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }
93 def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
117 def : WriteRes<WriteAdr, []> { let Latency = 0; }
121 def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 1; }
122 def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 1; }
123 def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 1; }
125 def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
128 def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
138 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
141 def : WriteRes<WriteBr, [CortexA55UnitB]>;
142 def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
143 def : WriteRes<WriteSys, [CortexA55UnitB]>;
144 def : WriteRes<WriteBarrier, [CortexA55UnitB]>;
145 def : WriteRes<WriteHint, [CortexA55UnitB]>;
150 def : WriteRes<WriteF, [CortexA55UnitFPALU]> { let Latency = 4; }
151 def : WriteRes<WriteFCmp, [CortexA55UnitFPALU]> { let Latency = 3; }
152 def : WriteRes<WriteFCvt, [CortexA55UnitFPALU]> { let Latency = 4; }
153 def : WriteRes<WriteFCopy, [CortexA55UnitFPALU]> { let Latency = 3; }
154 def : WriteRes<WriteFImm, [CortexA55UnitFPALU]> { let Latency = 3; }
188 def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
191 def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;